linux/drivers/interconnect/qcom/sdm845.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
   4 */
   5
   6#include <linux/device.h>
   7#include <linux/interconnect.h>
   8#include <linux/interconnect-provider.h>
   9#include <linux/module.h>
  10#include <linux/of_device.h>
  11
  12#include <dt-bindings/interconnect/qcom,sdm845.h>
  13
  14#include "bcm-voter.h"
  15#include "icc-rpmh.h"
  16#include "sdm845.h"
  17
  18DEFINE_QNODE(qhm_a1noc_cfg, SDM845_MASTER_A1NOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_A1NOC);
  19DEFINE_QNODE(qhm_qup1, SDM845_MASTER_BLSP_1, 1, 4, SDM845_SLAVE_A1NOC_SNOC);
  20DEFINE_QNODE(qhm_tsif, SDM845_MASTER_TSIF, 1, 4, SDM845_SLAVE_A1NOC_SNOC);
  21DEFINE_QNODE(xm_sdc2, SDM845_MASTER_SDCC_2, 1, 8, SDM845_SLAVE_A1NOC_SNOC);
  22DEFINE_QNODE(xm_sdc4, SDM845_MASTER_SDCC_4, 1, 8, SDM845_SLAVE_A1NOC_SNOC);
  23DEFINE_QNODE(xm_ufs_card, SDM845_MASTER_UFS_CARD, 1, 8, SDM845_SLAVE_A1NOC_SNOC);
  24DEFINE_QNODE(xm_ufs_mem, SDM845_MASTER_UFS_MEM, 1, 8, SDM845_SLAVE_A1NOC_SNOC);
  25DEFINE_QNODE(xm_pcie_0, SDM845_MASTER_PCIE_0, 1, 8, SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC);
  26DEFINE_QNODE(qhm_a2noc_cfg, SDM845_MASTER_A2NOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_A2NOC);
  27DEFINE_QNODE(qhm_qdss_bam, SDM845_MASTER_QDSS_BAM, 1, 4, SDM845_SLAVE_A2NOC_SNOC);
  28DEFINE_QNODE(qhm_qup2, SDM845_MASTER_BLSP_2, 1, 4, SDM845_SLAVE_A2NOC_SNOC);
  29DEFINE_QNODE(qnm_cnoc, SDM845_MASTER_CNOC_A2NOC, 1, 8, SDM845_SLAVE_A2NOC_SNOC);
  30DEFINE_QNODE(qxm_crypto, SDM845_MASTER_CRYPTO, 1, 8, SDM845_SLAVE_A2NOC_SNOC);
  31DEFINE_QNODE(qxm_ipa, SDM845_MASTER_IPA, 1, 8, SDM845_SLAVE_A2NOC_SNOC);
  32DEFINE_QNODE(xm_pcie3_1, SDM845_MASTER_PCIE_1, 1, 8, SDM845_SLAVE_ANOC_PCIE_SNOC);
  33DEFINE_QNODE(xm_qdss_etr, SDM845_MASTER_QDSS_ETR, 1, 8, SDM845_SLAVE_A2NOC_SNOC);
  34DEFINE_QNODE(xm_usb3_0, SDM845_MASTER_USB3_0, 1, 8, SDM845_SLAVE_A2NOC_SNOC);
  35DEFINE_QNODE(xm_usb3_1, SDM845_MASTER_USB3_1, 1, 8, SDM845_SLAVE_A2NOC_SNOC);
  36DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SDM845_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SDM845_SLAVE_CAMNOC_UNCOMP);
  37DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SDM845_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SDM845_SLAVE_CAMNOC_UNCOMP);
  38DEFINE_QNODE(qxm_camnoc_sf_uncomp, SDM845_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SDM845_SLAVE_CAMNOC_UNCOMP);
  39DEFINE_QNODE(qhm_spdm, SDM845_MASTER_SPDM, 1, 4, SDM845_SLAVE_CNOC_A2NOC);
  40DEFINE_QNODE(qhm_tic, SDM845_MASTER_TIC, 1, 4, SDM845_SLAVE_A1NOC_CFG, SDM845_SLAVE_A2NOC_CFG, SDM845_SLAVE_AOP, SDM845_SLAVE_AOSS, SDM845_SLAVE_CAMERA_CFG, SDM845_SLAVE_CLK_CTL, SDM845_SLAVE_CDSP_CFG, SDM845_SLAVE_RBCPR_CX_CFG, SDM845_SLAVE_CRYPTO_0_CFG, SDM845_SLAVE_DCC_CFG, SDM845_SLAVE_CNOC_DDRSS, SDM845_SLAVE_DISPLAY_CFG, SDM845_SLAVE_GLM, SDM845_SLAVE_GFX3D_CFG, SDM845_SLAVE_IMEM_CFG, SDM845_SLAVE_IPA_CFG, SDM845_SLAVE_CNOC_MNOC_CFG, SDM845_SLAVE_PCIE_0_CFG, SDM845_SLAVE_PCIE_1_CFG, SDM845_SLAVE_PDM, SDM845_SLAVE_SOUTH_PHY_CFG, SDM845_SLAVE_PIMEM_CFG, SDM845_SLAVE_PRNG, SDM845_SLAVE_QDSS_CFG, SDM845_SLAVE_BLSP_2, SDM845_SLAVE_BLSP_1, SDM845_SLAVE_SDCC_2, SDM845_SLAVE_SDCC_4, SDM845_SLAVE_SNOC_CFG, SDM845_SLAVE_SPDM_WRAPPER, SDM845_SLAVE_SPSS_CFG, SDM845_SLAVE_TCSR, SDM845_SLAVE_TLMM_NORTH, SDM845_SLAVE_TLMM_SOUTH, SDM845_SLAVE_TSIF, SDM845_SLAVE_UFS_CARD_CFG, SDM845_SLAVE_UFS_MEM_CFG, SDM845_SLAVE_USB3_0, SDM845_SLAVE_USB3_1, SDM845_SLAVE_VENUS_CFG, SDM845_SLAVE_VSENSE_CTRL_CFG, SDM845_SLAVE_CNOC_A2NOC, SDM845_SLAVE_SERVICE_CNOC);
  41DEFINE_QNODE(qnm_snoc, SDM845_MASTER_SNOC_CNOC, 1, 8, SDM845_SLAVE_A1NOC_CFG, SDM845_SLAVE_A2NOC_CFG, SDM845_SLAVE_AOP, SDM845_SLAVE_AOSS, SDM845_SLAVE_CAMERA_CFG, SDM845_SLAVE_CLK_CTL, SDM845_SLAVE_CDSP_CFG, SDM845_SLAVE_RBCPR_CX_CFG, SDM845_SLAVE_CRYPTO_0_CFG, SDM845_SLAVE_DCC_CFG, SDM845_SLAVE_CNOC_DDRSS, SDM845_SLAVE_DISPLAY_CFG, SDM845_SLAVE_GLM, SDM845_SLAVE_GFX3D_CFG, SDM845_SLAVE_IMEM_CFG, SDM845_SLAVE_IPA_CFG, SDM845_SLAVE_CNOC_MNOC_CFG, SDM845_SLAVE_PCIE_0_CFG, SDM845_SLAVE_PCIE_1_CFG, SDM845_SLAVE_PDM, SDM845_SLAVE_SOUTH_PHY_CFG, SDM845_SLAVE_PIMEM_CFG, SDM845_SLAVE_PRNG, SDM845_SLAVE_QDSS_CFG, SDM845_SLAVE_BLSP_2, SDM845_SLAVE_BLSP_1, SDM845_SLAVE_SDCC_2, SDM845_SLAVE_SDCC_4, SDM845_SLAVE_SNOC_CFG, SDM845_SLAVE_SPDM_WRAPPER, SDM845_SLAVE_SPSS_CFG, SDM845_SLAVE_TCSR, SDM845_SLAVE_TLMM_NORTH, SDM845_SLAVE_TLMM_SOUTH, SDM845_SLAVE_TSIF, SDM845_SLAVE_UFS_CARD_CFG, SDM845_SLAVE_UFS_MEM_CFG, SDM845_SLAVE_USB3_0, SDM845_SLAVE_USB3_1, SDM845_SLAVE_VENUS_CFG, SDM845_SLAVE_VSENSE_CTRL_CFG, SDM845_SLAVE_SERVICE_CNOC);
  42DEFINE_QNODE(xm_qdss_dap, SDM845_MASTER_QDSS_DAP, 1, 8, SDM845_SLAVE_A1NOC_CFG, SDM845_SLAVE_A2NOC_CFG, SDM845_SLAVE_AOP, SDM845_SLAVE_AOSS, SDM845_SLAVE_CAMERA_CFG, SDM845_SLAVE_CLK_CTL, SDM845_SLAVE_CDSP_CFG, SDM845_SLAVE_RBCPR_CX_CFG, SDM845_SLAVE_CRYPTO_0_CFG, SDM845_SLAVE_DCC_CFG, SDM845_SLAVE_CNOC_DDRSS, SDM845_SLAVE_DISPLAY_CFG, SDM845_SLAVE_GLM, SDM845_SLAVE_GFX3D_CFG, SDM845_SLAVE_IMEM_CFG, SDM845_SLAVE_IPA_CFG, SDM845_SLAVE_CNOC_MNOC_CFG, SDM845_SLAVE_PCIE_0_CFG, SDM845_SLAVE_PCIE_1_CFG, SDM845_SLAVE_PDM, SDM845_SLAVE_SOUTH_PHY_CFG, SDM845_SLAVE_PIMEM_CFG, SDM845_SLAVE_PRNG, SDM845_SLAVE_QDSS_CFG, SDM845_SLAVE_BLSP_2, SDM845_SLAVE_BLSP_1, SDM845_SLAVE_SDCC_2, SDM845_SLAVE_SDCC_4, SDM845_SLAVE_SNOC_CFG, SDM845_SLAVE_SPDM_WRAPPER, SDM845_SLAVE_SPSS_CFG, SDM845_SLAVE_TCSR, SDM845_SLAVE_TLMM_NORTH, SDM845_SLAVE_TLMM_SOUTH, SDM845_SLAVE_TSIF, SDM845_SLAVE_UFS_CARD_CFG, SDM845_SLAVE_UFS_MEM_CFG, SDM845_SLAVE_USB3_0, SDM845_SLAVE_USB3_1, SDM845_SLAVE_VENUS_CFG, SDM845_SLAVE_VSENSE_CTRL_CFG, SDM845_SLAVE_CNOC_A2NOC, SDM845_SLAVE_SERVICE_CNOC);
  43DEFINE_QNODE(qhm_cnoc, SDM845_MASTER_CNOC_DC_NOC, 1, 4, SDM845_SLAVE_LLCC_CFG, SDM845_SLAVE_MEM_NOC_CFG);
  44DEFINE_QNODE(acm_l3, SDM845_MASTER_APPSS_PROC, 1, 16, SDM845_SLAVE_GNOC_SNOC, SDM845_SLAVE_GNOC_MEM_NOC, SDM845_SLAVE_SERVICE_GNOC);
  45DEFINE_QNODE(pm_gnoc_cfg, SDM845_MASTER_GNOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_GNOC);
  46DEFINE_QNODE(llcc_mc, SDM845_MASTER_LLCC, 4, 4, SDM845_SLAVE_EBI1);
  47DEFINE_QNODE(acm_tcu, SDM845_MASTER_TCU_0, 1, 8, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC, SDM845_SLAVE_MEM_NOC_SNOC);
  48DEFINE_QNODE(qhm_memnoc_cfg, SDM845_MASTER_MEM_NOC_CFG, 1, 4, SDM845_SLAVE_MSS_PROC_MS_MPU_CFG, SDM845_SLAVE_SERVICE_MEM_NOC);
  49DEFINE_QNODE(qnm_apps, SDM845_MASTER_GNOC_MEM_NOC, 2, 32, SDM845_SLAVE_LLCC);
  50DEFINE_QNODE(qnm_mnoc_hf, SDM845_MASTER_MNOC_HF_MEM_NOC, 2, 32, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC);
  51DEFINE_QNODE(qnm_mnoc_sf, SDM845_MASTER_MNOC_SF_MEM_NOC, 1, 32, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC, SDM845_SLAVE_MEM_NOC_SNOC);
  52DEFINE_QNODE(qnm_snoc_gc, SDM845_MASTER_SNOC_GC_MEM_NOC, 1, 8, SDM845_SLAVE_LLCC);
  53DEFINE_QNODE(qnm_snoc_sf, SDM845_MASTER_SNOC_SF_MEM_NOC, 1, 16, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC);
  54DEFINE_QNODE(qxm_gpu, SDM845_MASTER_GFX3D, 2, 32, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC, SDM845_SLAVE_MEM_NOC_SNOC);
  55DEFINE_QNODE(qhm_mnoc_cfg, SDM845_MASTER_CNOC_MNOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_MNOC);
  56DEFINE_QNODE(qxm_camnoc_hf0, SDM845_MASTER_CAMNOC_HF0, 1, 32, SDM845_SLAVE_MNOC_HF_MEM_NOC);
  57DEFINE_QNODE(qxm_camnoc_hf1, SDM845_MASTER_CAMNOC_HF1, 1, 32, SDM845_SLAVE_MNOC_HF_MEM_NOC);
  58DEFINE_QNODE(qxm_camnoc_sf, SDM845_MASTER_CAMNOC_SF, 1, 32, SDM845_SLAVE_MNOC_SF_MEM_NOC);
  59DEFINE_QNODE(qxm_mdp0, SDM845_MASTER_MDP0, 1, 32, SDM845_SLAVE_MNOC_HF_MEM_NOC);
  60DEFINE_QNODE(qxm_mdp1, SDM845_MASTER_MDP1, 1, 32, SDM845_SLAVE_MNOC_HF_MEM_NOC);
  61DEFINE_QNODE(qxm_rot, SDM845_MASTER_ROTATOR, 1, 32, SDM845_SLAVE_MNOC_SF_MEM_NOC);
  62DEFINE_QNODE(qxm_venus0, SDM845_MASTER_VIDEO_P0, 1, 32, SDM845_SLAVE_MNOC_SF_MEM_NOC);
  63DEFINE_QNODE(qxm_venus1, SDM845_MASTER_VIDEO_P1, 1, 32, SDM845_SLAVE_MNOC_SF_MEM_NOC);
  64DEFINE_QNODE(qxm_venus_arm9, SDM845_MASTER_VIDEO_PROC, 1, 8, SDM845_SLAVE_MNOC_SF_MEM_NOC);
  65DEFINE_QNODE(qhm_snoc_cfg, SDM845_MASTER_SNOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_SNOC);
  66DEFINE_QNODE(qnm_aggre1_noc, SDM845_MASTER_A1NOC_SNOC, 1, 16, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_SNOC_MEM_NOC_SF, SDM845_SLAVE_IMEM, SDM845_SLAVE_PIMEM, SDM845_SLAVE_QDSS_STM);
  67DEFINE_QNODE(qnm_aggre2_noc, SDM845_MASTER_A2NOC_SNOC, 1, 16, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_SNOC_MEM_NOC_SF, SDM845_SLAVE_IMEM, SDM845_SLAVE_PCIE_0, SDM845_SLAVE_PCIE_1, SDM845_SLAVE_PIMEM, SDM845_SLAVE_QDSS_STM, SDM845_SLAVE_TCU);
  68DEFINE_QNODE(qnm_gladiator_sodv, SDM845_MASTER_GNOC_SNOC, 1, 8, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_IMEM, SDM845_SLAVE_PCIE_0, SDM845_SLAVE_PCIE_1, SDM845_SLAVE_PIMEM, SDM845_SLAVE_QDSS_STM, SDM845_SLAVE_TCU);
  69DEFINE_QNODE(qnm_memnoc, SDM845_MASTER_MEM_NOC_SNOC, 1, 8, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_IMEM, SDM845_SLAVE_PIMEM, SDM845_SLAVE_QDSS_STM);
  70DEFINE_QNODE(qnm_pcie_anoc, SDM845_MASTER_ANOC_PCIE_SNOC, 1, 16, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_SNOC_MEM_NOC_SF, SDM845_SLAVE_IMEM, SDM845_SLAVE_QDSS_STM);
  71DEFINE_QNODE(qxm_pimem, SDM845_MASTER_PIMEM, 1, 8, SDM845_SLAVE_SNOC_MEM_NOC_GC, SDM845_SLAVE_IMEM);
  72DEFINE_QNODE(xm_gic, SDM845_MASTER_GIC, 1, 8, SDM845_SLAVE_SNOC_MEM_NOC_GC, SDM845_SLAVE_IMEM);
  73DEFINE_QNODE(qns_a1noc_snoc, SDM845_SLAVE_A1NOC_SNOC, 1, 16, SDM845_MASTER_A1NOC_SNOC);
  74DEFINE_QNODE(srvc_aggre1_noc, SDM845_SLAVE_SERVICE_A1NOC, 1, 4, 0);
  75DEFINE_QNODE(qns_pcie_a1noc_snoc, SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC, 1, 16, SDM845_MASTER_ANOC_PCIE_SNOC);
  76DEFINE_QNODE(qns_a2noc_snoc, SDM845_SLAVE_A2NOC_SNOC, 1, 16, SDM845_MASTER_A2NOC_SNOC);
  77DEFINE_QNODE(qns_pcie_snoc, SDM845_SLAVE_ANOC_PCIE_SNOC, 1, 16, SDM845_MASTER_ANOC_PCIE_SNOC);
  78DEFINE_QNODE(srvc_aggre2_noc, SDM845_SLAVE_SERVICE_A2NOC, 1, 4);
  79DEFINE_QNODE(qns_camnoc_uncomp, SDM845_SLAVE_CAMNOC_UNCOMP, 1, 32);
  80DEFINE_QNODE(qhs_a1_noc_cfg, SDM845_SLAVE_A1NOC_CFG, 1, 4, SDM845_MASTER_A1NOC_CFG);
  81DEFINE_QNODE(qhs_a2_noc_cfg, SDM845_SLAVE_A2NOC_CFG, 1, 4, SDM845_MASTER_A2NOC_CFG);
  82DEFINE_QNODE(qhs_aop, SDM845_SLAVE_AOP, 1, 4);
  83DEFINE_QNODE(qhs_aoss, SDM845_SLAVE_AOSS, 1, 4);
  84DEFINE_QNODE(qhs_camera_cfg, SDM845_SLAVE_CAMERA_CFG, 1, 4);
  85DEFINE_QNODE(qhs_clk_ctl, SDM845_SLAVE_CLK_CTL, 1, 4);
  86DEFINE_QNODE(qhs_compute_dsp_cfg, SDM845_SLAVE_CDSP_CFG, 1, 4);
  87DEFINE_QNODE(qhs_cpr_cx, SDM845_SLAVE_RBCPR_CX_CFG, 1, 4);
  88DEFINE_QNODE(qhs_crypto0_cfg, SDM845_SLAVE_CRYPTO_0_CFG, 1, 4);
  89DEFINE_QNODE(qhs_dcc_cfg, SDM845_SLAVE_DCC_CFG, 1, 4, SDM845_MASTER_CNOC_DC_NOC);
  90DEFINE_QNODE(qhs_ddrss_cfg, SDM845_SLAVE_CNOC_DDRSS, 1, 4);
  91DEFINE_QNODE(qhs_display_cfg, SDM845_SLAVE_DISPLAY_CFG, 1, 4);
  92DEFINE_QNODE(qhs_glm, SDM845_SLAVE_GLM, 1, 4);
  93DEFINE_QNODE(qhs_gpuss_cfg, SDM845_SLAVE_GFX3D_CFG, 1, 8);
  94DEFINE_QNODE(qhs_imem_cfg, SDM845_SLAVE_IMEM_CFG, 1, 4);
  95DEFINE_QNODE(qhs_ipa, SDM845_SLAVE_IPA_CFG, 1, 4);
  96DEFINE_QNODE(qhs_mnoc_cfg, SDM845_SLAVE_CNOC_MNOC_CFG, 1, 4, SDM845_MASTER_CNOC_MNOC_CFG);
  97DEFINE_QNODE(qhs_pcie0_cfg, SDM845_SLAVE_PCIE_0_CFG, 1, 4);
  98DEFINE_QNODE(qhs_pcie_gen3_cfg, SDM845_SLAVE_PCIE_1_CFG, 1, 4);
  99DEFINE_QNODE(qhs_pdm, SDM845_SLAVE_PDM, 1, 4);
 100DEFINE_QNODE(qhs_phy_refgen_south, SDM845_SLAVE_SOUTH_PHY_CFG, 1, 4);
 101DEFINE_QNODE(qhs_pimem_cfg, SDM845_SLAVE_PIMEM_CFG, 1, 4);
 102DEFINE_QNODE(qhs_prng, SDM845_SLAVE_PRNG, 1, 4);
 103DEFINE_QNODE(qhs_qdss_cfg, SDM845_SLAVE_QDSS_CFG, 1, 4);
 104DEFINE_QNODE(qhs_qupv3_north, SDM845_SLAVE_BLSP_2, 1, 4);
 105DEFINE_QNODE(qhs_qupv3_south, SDM845_SLAVE_BLSP_1, 1, 4);
 106DEFINE_QNODE(qhs_sdc2, SDM845_SLAVE_SDCC_2, 1, 4);
 107DEFINE_QNODE(qhs_sdc4, SDM845_SLAVE_SDCC_4, 1, 4);
 108DEFINE_QNODE(qhs_snoc_cfg, SDM845_SLAVE_SNOC_CFG, 1, 4, SDM845_MASTER_SNOC_CFG);
 109DEFINE_QNODE(qhs_spdm, SDM845_SLAVE_SPDM_WRAPPER, 1, 4);
 110DEFINE_QNODE(qhs_spss_cfg, SDM845_SLAVE_SPSS_CFG, 1, 4);
 111DEFINE_QNODE(qhs_tcsr, SDM845_SLAVE_TCSR, 1, 4);
 112DEFINE_QNODE(qhs_tlmm_north, SDM845_SLAVE_TLMM_NORTH, 1, 4);
 113DEFINE_QNODE(qhs_tlmm_south, SDM845_SLAVE_TLMM_SOUTH, 1, 4);
 114DEFINE_QNODE(qhs_tsif, SDM845_SLAVE_TSIF, 1, 4);
 115DEFINE_QNODE(qhs_ufs_card_cfg, SDM845_SLAVE_UFS_CARD_CFG, 1, 4);
 116DEFINE_QNODE(qhs_ufs_mem_cfg, SDM845_SLAVE_UFS_MEM_CFG, 1, 4);
 117DEFINE_QNODE(qhs_usb3_0, SDM845_SLAVE_USB3_0, 1, 4);
 118DEFINE_QNODE(qhs_usb3_1, SDM845_SLAVE_USB3_1, 1, 4);
 119DEFINE_QNODE(qhs_venus_cfg, SDM845_SLAVE_VENUS_CFG, 1, 4);
 120DEFINE_QNODE(qhs_vsense_ctrl_cfg, SDM845_SLAVE_VSENSE_CTRL_CFG, 1, 4);
 121DEFINE_QNODE(qns_cnoc_a2noc, SDM845_SLAVE_CNOC_A2NOC, 1, 8, SDM845_MASTER_CNOC_A2NOC);
 122DEFINE_QNODE(srvc_cnoc, SDM845_SLAVE_SERVICE_CNOC, 1, 4);
 123DEFINE_QNODE(qhs_llcc, SDM845_SLAVE_LLCC_CFG, 1, 4);
 124DEFINE_QNODE(qhs_memnoc, SDM845_SLAVE_MEM_NOC_CFG, 1, 4, SDM845_MASTER_MEM_NOC_CFG);
 125DEFINE_QNODE(qns_gladiator_sodv, SDM845_SLAVE_GNOC_SNOC, 1, 8, SDM845_MASTER_GNOC_SNOC);
 126DEFINE_QNODE(qns_gnoc_memnoc, SDM845_SLAVE_GNOC_MEM_NOC, 2, 32, SDM845_MASTER_GNOC_MEM_NOC);
 127DEFINE_QNODE(srvc_gnoc, SDM845_SLAVE_SERVICE_GNOC, 1, 4);
 128DEFINE_QNODE(ebi, SDM845_SLAVE_EBI1, 4, 4);
 129DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SDM845_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
 130DEFINE_QNODE(qns_apps_io, SDM845_SLAVE_MEM_NOC_GNOC, 1, 32);
 131DEFINE_QNODE(qns_llcc, SDM845_SLAVE_LLCC, 4, 16, SDM845_MASTER_LLCC);
 132DEFINE_QNODE(qns_memnoc_snoc, SDM845_SLAVE_MEM_NOC_SNOC, 1, 8, SDM845_MASTER_MEM_NOC_SNOC);
 133DEFINE_QNODE(srvc_memnoc, SDM845_SLAVE_SERVICE_MEM_NOC, 1, 4);
 134DEFINE_QNODE(qns2_mem_noc, SDM845_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SDM845_MASTER_MNOC_SF_MEM_NOC);
 135DEFINE_QNODE(qns_mem_noc_hf, SDM845_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SDM845_MASTER_MNOC_HF_MEM_NOC);
 136DEFINE_QNODE(srvc_mnoc, SDM845_SLAVE_SERVICE_MNOC, 1, 4);
 137DEFINE_QNODE(qhs_apss, SDM845_SLAVE_APPSS, 1, 8);
 138DEFINE_QNODE(qns_cnoc, SDM845_SLAVE_SNOC_CNOC, 1, 8, SDM845_MASTER_SNOC_CNOC);
 139DEFINE_QNODE(qns_memnoc_gc, SDM845_SLAVE_SNOC_MEM_NOC_GC, 1, 8, SDM845_MASTER_SNOC_GC_MEM_NOC);
 140DEFINE_QNODE(qns_memnoc_sf, SDM845_SLAVE_SNOC_MEM_NOC_SF, 1, 16, SDM845_MASTER_SNOC_SF_MEM_NOC);
 141DEFINE_QNODE(qxs_imem, SDM845_SLAVE_IMEM, 1, 8);
 142DEFINE_QNODE(qxs_pcie, SDM845_SLAVE_PCIE_0, 1, 8);
 143DEFINE_QNODE(qxs_pcie_gen3, SDM845_SLAVE_PCIE_1, 1, 8);
 144DEFINE_QNODE(qxs_pimem, SDM845_SLAVE_PIMEM, 1, 8);
 145DEFINE_QNODE(srvc_snoc, SDM845_SLAVE_SERVICE_SNOC, 1, 4);
 146DEFINE_QNODE(xs_qdss_stm, SDM845_SLAVE_QDSS_STM, 1, 4);
 147DEFINE_QNODE(xs_sys_tcu_cfg, SDM845_SLAVE_TCU, 1, 8);
 148
 149DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
 150DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
 151DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
 152DEFINE_QBCM(bcm_mm0, "MM0", false, &qns_mem_noc_hf);
 153DEFINE_QBCM(bcm_sh1, "SH1", false, &qns_apps_io);
 154DEFINE_QBCM(bcm_mm1, "MM1", true, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, &qxm_camnoc_hf1, &qxm_mdp0, &qxm_mdp1);
 155DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_memnoc_snoc);
 156DEFINE_QBCM(bcm_mm2, "MM2", false, &qns2_mem_noc);
 157DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_tcu);
 158DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9);
 159DEFINE_QBCM(bcm_sh5, "SH5", false, &qnm_apps);
 160DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_memnoc_sf);
 161DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
 162DEFINE_QBCM(bcm_cn0, "CN0", false, &qhm_spdm, &qhm_tic, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp_cfg, &qhs_cpr_cx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_pcie0_cfg, &qhs_pcie_gen3_cfg, &qhs_pdm, &qhs_phy_refgen_south, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_spss_cfg, &qhs_tcsr, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
 163DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2);
 164DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
 165DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_memnoc_gc);
 166DEFINE_QBCM(bcm_sn3, "SN3", false, &qns_cnoc);
 167DEFINE_QBCM(bcm_sn4, "SN4", false, &qxm_pimem);
 168DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm);
 169DEFINE_QBCM(bcm_sn6, "SN6", false, &qhs_apss, &srvc_snoc, &xs_sys_tcu_cfg);
 170DEFINE_QBCM(bcm_sn7, "SN7", false, &qxs_pcie);
 171DEFINE_QBCM(bcm_sn8, "SN8", false, &qxs_pcie_gen3);
 172DEFINE_QBCM(bcm_sn9, "SN9", false, &srvc_aggre1_noc, &qnm_aggre1_noc);
 173DEFINE_QBCM(bcm_sn11, "SN11", false, &srvc_aggre2_noc, &qnm_aggre2_noc);
 174DEFINE_QBCM(bcm_sn12, "SN12", false, &qnm_gladiator_sodv, &xm_gic);
 175DEFINE_QBCM(bcm_sn14, "SN14", false, &qnm_pcie_anoc);
 176DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_memnoc);
 177
 178static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
 179        &bcm_sn9,
 180        &bcm_qup0,
 181};
 182
 183static struct qcom_icc_node *aggre1_noc_nodes[] = {
 184        [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
 185        [MASTER_TSIF] = &qhm_tsif,
 186        [MASTER_SDCC_2] = &xm_sdc2,
 187        [MASTER_SDCC_4] = &xm_sdc4,
 188        [MASTER_UFS_CARD] = &xm_ufs_card,
 189        [MASTER_UFS_MEM] = &xm_ufs_mem,
 190        [MASTER_PCIE_0] = &xm_pcie_0,
 191        [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
 192        [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
 193        [SLAVE_ANOC_PCIE_A1NOC_SNOC] = &qns_pcie_a1noc_snoc,
 194        [MASTER_QUP_1] = &qhm_qup1,
 195};
 196
 197static const struct qcom_icc_desc sdm845_aggre1_noc = {
 198        .nodes = aggre1_noc_nodes,
 199        .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
 200        .bcms = aggre1_noc_bcms,
 201        .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
 202};
 203
 204static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
 205        &bcm_ce0,
 206        &bcm_sn11,
 207        &bcm_qup0,
 208};
 209
 210static struct qcom_icc_node *aggre2_noc_nodes[] = {
 211        [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
 212        [MASTER_QDSS_BAM] = &qhm_qdss_bam,
 213        [MASTER_CNOC_A2NOC] = &qnm_cnoc,
 214        [MASTER_CRYPTO] = &qxm_crypto,
 215        [MASTER_IPA] = &qxm_ipa,
 216        [MASTER_PCIE_1] = &xm_pcie3_1,
 217        [MASTER_QDSS_ETR] = &xm_qdss_etr,
 218        [MASTER_USB3_0] = &xm_usb3_0,
 219        [MASTER_USB3_1] = &xm_usb3_1,
 220        [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
 221        [SLAVE_ANOC_PCIE_SNOC] = &qns_pcie_snoc,
 222        [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
 223        [MASTER_QUP_2] = &qhm_qup2,
 224};
 225
 226static const struct qcom_icc_desc sdm845_aggre2_noc = {
 227        .nodes = aggre2_noc_nodes,
 228        .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
 229        .bcms = aggre2_noc_bcms,
 230        .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
 231};
 232
 233static struct qcom_icc_bcm *config_noc_bcms[] = {
 234        &bcm_cn0,
 235};
 236
 237static struct qcom_icc_node *config_noc_nodes[] = {
 238        [MASTER_SPDM] = &qhm_spdm,
 239        [MASTER_TIC] = &qhm_tic,
 240        [MASTER_SNOC_CNOC] = &qnm_snoc,
 241        [MASTER_QDSS_DAP] = &xm_qdss_dap,
 242        [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
 243        [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
 244        [SLAVE_AOP] = &qhs_aop,
 245        [SLAVE_AOSS] = &qhs_aoss,
 246        [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
 247        [SLAVE_CLK_CTL] = &qhs_clk_ctl,
 248        [SLAVE_CDSP_CFG] = &qhs_compute_dsp_cfg,
 249        [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
 250        [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
 251        [SLAVE_DCC_CFG] = &qhs_dcc_cfg,
 252        [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
 253        [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
 254        [SLAVE_GLM] = &qhs_glm,
 255        [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
 256        [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
 257        [SLAVE_IPA_CFG] = &qhs_ipa,
 258        [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
 259        [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
 260        [SLAVE_PCIE_1_CFG] = &qhs_pcie_gen3_cfg,
 261        [SLAVE_PDM] = &qhs_pdm,
 262        [SLAVE_SOUTH_PHY_CFG] = &qhs_phy_refgen_south,
 263        [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
 264        [SLAVE_PRNG] = &qhs_prng,
 265        [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
 266        [SLAVE_BLSP_2] = &qhs_qupv3_north,
 267        [SLAVE_BLSP_1] = &qhs_qupv3_south,
 268        [SLAVE_SDCC_2] = &qhs_sdc2,
 269        [SLAVE_SDCC_4] = &qhs_sdc4,
 270        [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
 271        [SLAVE_SPDM_WRAPPER] = &qhs_spdm,
 272        [SLAVE_SPSS_CFG] = &qhs_spss_cfg,
 273        [SLAVE_TCSR] = &qhs_tcsr,
 274        [SLAVE_TLMM_NORTH] = &qhs_tlmm_north,
 275        [SLAVE_TLMM_SOUTH] = &qhs_tlmm_south,
 276        [SLAVE_TSIF] = &qhs_tsif,
 277        [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
 278        [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
 279        [SLAVE_USB3_0] = &qhs_usb3_0,
 280        [SLAVE_USB3_1] = &qhs_usb3_1,
 281        [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
 282        [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
 283        [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
 284        [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
 285};
 286
 287static const struct qcom_icc_desc sdm845_config_noc = {
 288        .nodes = config_noc_nodes,
 289        .num_nodes = ARRAY_SIZE(config_noc_nodes),
 290        .bcms = config_noc_bcms,
 291        .num_bcms = ARRAY_SIZE(config_noc_bcms),
 292};
 293
 294static struct qcom_icc_bcm *dc_noc_bcms[] = {
 295};
 296
 297static struct qcom_icc_node *dc_noc_nodes[] = {
 298        [MASTER_CNOC_DC_NOC] = &qhm_cnoc,
 299        [SLAVE_LLCC_CFG] = &qhs_llcc,
 300        [SLAVE_MEM_NOC_CFG] = &qhs_memnoc,
 301};
 302
 303static const struct qcom_icc_desc sdm845_dc_noc = {
 304        .nodes = dc_noc_nodes,
 305        .num_nodes = ARRAY_SIZE(dc_noc_nodes),
 306        .bcms = dc_noc_bcms,
 307        .num_bcms = ARRAY_SIZE(dc_noc_bcms),
 308};
 309
 310static struct qcom_icc_bcm *gladiator_noc_bcms[] = {
 311};
 312
 313static struct qcom_icc_node *gladiator_noc_nodes[] = {
 314        [MASTER_APPSS_PROC] = &acm_l3,
 315        [MASTER_GNOC_CFG] = &pm_gnoc_cfg,
 316        [SLAVE_GNOC_SNOC] = &qns_gladiator_sodv,
 317        [SLAVE_GNOC_MEM_NOC] = &qns_gnoc_memnoc,
 318        [SLAVE_SERVICE_GNOC] = &srvc_gnoc,
 319};
 320
 321static const struct qcom_icc_desc sdm845_gladiator_noc = {
 322        .nodes = gladiator_noc_nodes,
 323        .num_nodes = ARRAY_SIZE(gladiator_noc_nodes),
 324        .bcms = gladiator_noc_bcms,
 325        .num_bcms = ARRAY_SIZE(gladiator_noc_bcms),
 326};
 327
 328static struct qcom_icc_bcm *mem_noc_bcms[] = {
 329        &bcm_mc0,
 330        &bcm_acv,
 331        &bcm_sh0,
 332        &bcm_sh1,
 333        &bcm_sh2,
 334        &bcm_sh3,
 335        &bcm_sh5,
 336};
 337
 338static struct qcom_icc_node *mem_noc_nodes[] = {
 339        [MASTER_TCU_0] = &acm_tcu,
 340        [MASTER_MEM_NOC_CFG] = &qhm_memnoc_cfg,
 341        [MASTER_GNOC_MEM_NOC] = &qnm_apps,
 342        [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
 343        [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
 344        [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
 345        [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
 346        [MASTER_GFX3D] = &qxm_gpu,
 347        [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
 348        [SLAVE_MEM_NOC_GNOC] = &qns_apps_io,
 349        [SLAVE_LLCC] = &qns_llcc,
 350        [SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc,
 351        [SLAVE_SERVICE_MEM_NOC] = &srvc_memnoc,
 352        [MASTER_LLCC] = &llcc_mc,
 353        [SLAVE_EBI1] = &ebi,
 354};
 355
 356static const struct qcom_icc_desc sdm845_mem_noc = {
 357        .nodes = mem_noc_nodes,
 358        .num_nodes = ARRAY_SIZE(mem_noc_nodes),
 359        .bcms = mem_noc_bcms,
 360        .num_bcms = ARRAY_SIZE(mem_noc_bcms),
 361};
 362
 363static struct qcom_icc_bcm *mmss_noc_bcms[] = {
 364        &bcm_mm0,
 365        &bcm_mm1,
 366        &bcm_mm2,
 367        &bcm_mm3,
 368};
 369
 370static struct qcom_icc_node *mmss_noc_nodes[] = {
 371        [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
 372        [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0,
 373        [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1,
 374        [MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
 375        [MASTER_MDP0] = &qxm_mdp0,
 376        [MASTER_MDP1] = &qxm_mdp1,
 377        [MASTER_ROTATOR] = &qxm_rot,
 378        [MASTER_VIDEO_P0] = &qxm_venus0,
 379        [MASTER_VIDEO_P1] = &qxm_venus1,
 380        [MASTER_VIDEO_PROC] = &qxm_venus_arm9,
 381        [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc,
 382        [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
 383        [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
 384        [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
 385        [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp,
 386        [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
 387        [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
 388};
 389
 390static const struct qcom_icc_desc sdm845_mmss_noc = {
 391        .nodes = mmss_noc_nodes,
 392        .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
 393        .bcms = mmss_noc_bcms,
 394        .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
 395};
 396
 397static struct qcom_icc_bcm *system_noc_bcms[] = {
 398        &bcm_sn0,
 399        &bcm_sn1,
 400        &bcm_sn2,
 401        &bcm_sn3,
 402        &bcm_sn4,
 403        &bcm_sn5,
 404        &bcm_sn6,
 405        &bcm_sn7,
 406        &bcm_sn8,
 407        &bcm_sn9,
 408        &bcm_sn11,
 409        &bcm_sn12,
 410        &bcm_sn14,
 411        &bcm_sn15,
 412};
 413
 414static struct qcom_icc_node *system_noc_nodes[] = {
 415        [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
 416        [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
 417        [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
 418        [MASTER_GNOC_SNOC] = &qnm_gladiator_sodv,
 419        [MASTER_MEM_NOC_SNOC] = &qnm_memnoc,
 420        [MASTER_ANOC_PCIE_SNOC] = &qnm_pcie_anoc,
 421        [MASTER_PIMEM] = &qxm_pimem,
 422        [MASTER_GIC] = &xm_gic,
 423        [SLAVE_APPSS] = &qhs_apss,
 424        [SLAVE_SNOC_CNOC] = &qns_cnoc,
 425        [SLAVE_SNOC_MEM_NOC_GC] = &qns_memnoc_gc,
 426        [SLAVE_SNOC_MEM_NOC_SF] = &qns_memnoc_sf,
 427        [SLAVE_IMEM] = &qxs_imem,
 428        [SLAVE_PCIE_0] = &qxs_pcie,
 429        [SLAVE_PCIE_1] = &qxs_pcie_gen3,
 430        [SLAVE_PIMEM] = &qxs_pimem,
 431        [SLAVE_SERVICE_SNOC] = &srvc_snoc,
 432        [SLAVE_QDSS_STM] = &xs_qdss_stm,
 433        [SLAVE_TCU] = &xs_sys_tcu_cfg,
 434};
 435
 436static const struct qcom_icc_desc sdm845_system_noc = {
 437        .nodes = system_noc_nodes,
 438        .num_nodes = ARRAY_SIZE(system_noc_nodes),
 439        .bcms = system_noc_bcms,
 440        .num_bcms = ARRAY_SIZE(system_noc_bcms),
 441};
 442
 443static int qnoc_probe(struct platform_device *pdev)
 444{
 445        const struct qcom_icc_desc *desc;
 446        struct icc_onecell_data *data;
 447        struct icc_provider *provider;
 448        struct qcom_icc_node **qnodes;
 449        struct qcom_icc_provider *qp;
 450        struct icc_node *node;
 451        size_t num_nodes, i;
 452        int ret;
 453
 454        desc = device_get_match_data(&pdev->dev);
 455        if (!desc)
 456                return -EINVAL;
 457
 458        qnodes = desc->nodes;
 459        num_nodes = desc->num_nodes;
 460
 461        qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
 462        if (!qp)
 463                return -ENOMEM;
 464
 465        data = devm_kzalloc(&pdev->dev, struct_size(data, nodes, num_nodes),
 466                            GFP_KERNEL);
 467        if (!data)
 468                return -ENOMEM;
 469
 470        provider = &qp->provider;
 471        provider->dev = &pdev->dev;
 472        provider->set = qcom_icc_set;
 473        provider->pre_aggregate = qcom_icc_pre_aggregate;
 474        provider->aggregate = qcom_icc_aggregate;
 475        provider->xlate_extended = qcom_icc_xlate_extended;
 476        INIT_LIST_HEAD(&provider->nodes);
 477        provider->data = data;
 478
 479        qp->dev = &pdev->dev;
 480        qp->bcms = desc->bcms;
 481        qp->num_bcms = desc->num_bcms;
 482
 483        qp->voter = of_bcm_voter_get(qp->dev, NULL);
 484        if (IS_ERR(qp->voter)) {
 485                dev_err(&pdev->dev, "bcm_voter err:%ld\n", PTR_ERR(qp->voter));
 486                return PTR_ERR(qp->voter);
 487        }
 488
 489        ret = icc_provider_add(provider);
 490        if (ret) {
 491                dev_err(&pdev->dev, "error adding interconnect provider\n");
 492                return ret;
 493        }
 494
 495        for (i = 0; i < qp->num_bcms; i++)
 496                qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
 497
 498        for (i = 0; i < num_nodes; i++) {
 499                size_t j;
 500
 501                if (!qnodes[i])
 502                        continue;
 503
 504                node = icc_node_create(qnodes[i]->id);
 505                if (IS_ERR(node)) {
 506                        ret = PTR_ERR(node);
 507                        goto err;
 508                }
 509
 510                node->name = qnodes[i]->name;
 511                node->data = qnodes[i];
 512                icc_node_add(node, provider);
 513
 514                for (j = 0; j < qnodes[i]->num_links; j++)
 515                        icc_link_create(node, qnodes[i]->links[j]);
 516
 517                data->nodes[i] = node;
 518        }
 519        data->num_nodes = num_nodes;
 520
 521        platform_set_drvdata(pdev, qp);
 522
 523        return 0;
 524err:
 525        icc_nodes_remove(provider);
 526        icc_provider_del(provider);
 527        return ret;
 528}
 529
 530static int qnoc_remove(struct platform_device *pdev)
 531{
 532        struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
 533
 534        icc_nodes_remove(&qp->provider);
 535        return icc_provider_del(&qp->provider);
 536}
 537
 538static const struct of_device_id qnoc_of_match[] = {
 539        { .compatible = "qcom,sdm845-aggre1-noc",
 540          .data = &sdm845_aggre1_noc},
 541        { .compatible = "qcom,sdm845-aggre2-noc",
 542          .data = &sdm845_aggre2_noc},
 543        { .compatible = "qcom,sdm845-config-noc",
 544          .data = &sdm845_config_noc},
 545        { .compatible = "qcom,sdm845-dc-noc",
 546          .data = &sdm845_dc_noc},
 547        { .compatible = "qcom,sdm845-gladiator-noc",
 548          .data = &sdm845_gladiator_noc},
 549        { .compatible = "qcom,sdm845-mem-noc",
 550          .data = &sdm845_mem_noc},
 551        { .compatible = "qcom,sdm845-mmss-noc",
 552          .data = &sdm845_mmss_noc},
 553        { .compatible = "qcom,sdm845-system-noc",
 554          .data = &sdm845_system_noc},
 555        { }
 556};
 557MODULE_DEVICE_TABLE(of, qnoc_of_match);
 558
 559static struct platform_driver qnoc_driver = {
 560        .probe = qnoc_probe,
 561        .remove = qnoc_remove,
 562        .driver = {
 563                .name = "qnoc-sdm845",
 564                .of_match_table = qnoc_of_match,
 565                .sync_state = icc_sync_state,
 566        },
 567};
 568module_platform_driver(qnoc_driver);
 569
 570MODULE_AUTHOR("David Dai <daidavid1@codeaurora.org>");
 571MODULE_DESCRIPTION("Qualcomm sdm845 NoC driver");
 572MODULE_LICENSE("GPL v2");
 573