linux/drivers/interconnect/qcom/qcs404.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (C) 2019 Linaro Ltd
   4 */
   5
   6#include <dt-bindings/interconnect/qcom,qcs404.h>
   7#include <linux/clk.h>
   8#include <linux/device.h>
   9#include <linux/interconnect-provider.h>
  10#include <linux/io.h>
  11#include <linux/module.h>
  12#include <linux/platform_device.h>
  13#include <linux/of_device.h>
  14
  15
  16#include "smd-rpm.h"
  17#include "icc-rpm.h"
  18
  19enum {
  20        QCS404_MASTER_AMPSS_M0 = 1,
  21        QCS404_MASTER_GRAPHICS_3D,
  22        QCS404_MASTER_MDP_PORT0,
  23        QCS404_SNOC_BIMC_1_MAS,
  24        QCS404_MASTER_TCU_0,
  25        QCS404_MASTER_SPDM,
  26        QCS404_MASTER_BLSP_1,
  27        QCS404_MASTER_BLSP_2,
  28        QCS404_MASTER_XM_USB_HS1,
  29        QCS404_MASTER_CRYPTO_CORE0,
  30        QCS404_MASTER_SDCC_1,
  31        QCS404_MASTER_SDCC_2,
  32        QCS404_SNOC_PNOC_MAS,
  33        QCS404_MASTER_QPIC,
  34        QCS404_MASTER_QDSS_BAM,
  35        QCS404_BIMC_SNOC_MAS,
  36        QCS404_PNOC_SNOC_MAS,
  37        QCS404_MASTER_QDSS_ETR,
  38        QCS404_MASTER_EMAC,
  39        QCS404_MASTER_PCIE,
  40        QCS404_MASTER_USB3,
  41        QCS404_PNOC_INT_0,
  42        QCS404_PNOC_INT_2,
  43        QCS404_PNOC_INT_3,
  44        QCS404_PNOC_SLV_0,
  45        QCS404_PNOC_SLV_1,
  46        QCS404_PNOC_SLV_2,
  47        QCS404_PNOC_SLV_3,
  48        QCS404_PNOC_SLV_4,
  49        QCS404_PNOC_SLV_6,
  50        QCS404_PNOC_SLV_7,
  51        QCS404_PNOC_SLV_8,
  52        QCS404_PNOC_SLV_9,
  53        QCS404_PNOC_SLV_10,
  54        QCS404_PNOC_SLV_11,
  55        QCS404_SNOC_QDSS_INT,
  56        QCS404_SNOC_INT_0,
  57        QCS404_SNOC_INT_1,
  58        QCS404_SNOC_INT_2,
  59        QCS404_SLAVE_EBI_CH0,
  60        QCS404_BIMC_SNOC_SLV,
  61        QCS404_SLAVE_SPDM_WRAPPER,
  62        QCS404_SLAVE_PDM,
  63        QCS404_SLAVE_PRNG,
  64        QCS404_SLAVE_TCSR,
  65        QCS404_SLAVE_SNOC_CFG,
  66        QCS404_SLAVE_MESSAGE_RAM,
  67        QCS404_SLAVE_DISPLAY_CFG,
  68        QCS404_SLAVE_GRAPHICS_3D_CFG,
  69        QCS404_SLAVE_BLSP_1,
  70        QCS404_SLAVE_TLMM_NORTH,
  71        QCS404_SLAVE_PCIE_1,
  72        QCS404_SLAVE_EMAC_CFG,
  73        QCS404_SLAVE_BLSP_2,
  74        QCS404_SLAVE_TLMM_EAST,
  75        QCS404_SLAVE_TCU,
  76        QCS404_SLAVE_PMIC_ARB,
  77        QCS404_SLAVE_SDCC_1,
  78        QCS404_SLAVE_SDCC_2,
  79        QCS404_SLAVE_TLMM_SOUTH,
  80        QCS404_SLAVE_USB_HS,
  81        QCS404_SLAVE_USB3,
  82        QCS404_SLAVE_CRYPTO_0_CFG,
  83        QCS404_PNOC_SNOC_SLV,
  84        QCS404_SLAVE_APPSS,
  85        QCS404_SLAVE_WCSS,
  86        QCS404_SNOC_BIMC_1_SLV,
  87        QCS404_SLAVE_OCIMEM,
  88        QCS404_SNOC_PNOC_SLV,
  89        QCS404_SLAVE_QDSS_STM,
  90        QCS404_SLAVE_CATS_128,
  91        QCS404_SLAVE_OCMEM_64,
  92        QCS404_SLAVE_LPASS,
  93};
  94
  95static const struct clk_bulk_data qcs404_bus_clocks[] = {
  96        { .id = "bus" },
  97        { .id = "bus_a" },
  98};
  99
 100DEFINE_QNODE(mas_apps_proc, QCS404_MASTER_AMPSS_M0, 8, 0, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV);
 101DEFINE_QNODE(mas_oxili, QCS404_MASTER_GRAPHICS_3D, 8, -1, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV);
 102DEFINE_QNODE(mas_mdp, QCS404_MASTER_MDP_PORT0, 8, -1, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV);
 103DEFINE_QNODE(mas_snoc_bimc_1, QCS404_SNOC_BIMC_1_MAS, 8, 76, -1, QCS404_SLAVE_EBI_CH0);
 104DEFINE_QNODE(mas_tcu_0, QCS404_MASTER_TCU_0, 8, -1, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV);
 105DEFINE_QNODE(mas_spdm, QCS404_MASTER_SPDM, 4, -1, -1, QCS404_PNOC_INT_3);
 106DEFINE_QNODE(mas_blsp_1, QCS404_MASTER_BLSP_1, 4, 41, -1, QCS404_PNOC_INT_3);
 107DEFINE_QNODE(mas_blsp_2, QCS404_MASTER_BLSP_2, 4, 39, -1, QCS404_PNOC_INT_3);
 108DEFINE_QNODE(mas_xi_usb_hs1, QCS404_MASTER_XM_USB_HS1, 8, 138, -1, QCS404_PNOC_INT_0);
 109DEFINE_QNODE(mas_crypto, QCS404_MASTER_CRYPTO_CORE0, 8, 23, -1, QCS404_PNOC_SNOC_SLV, QCS404_PNOC_INT_2);
 110DEFINE_QNODE(mas_sdcc_1, QCS404_MASTER_SDCC_1, 8, 33, -1, QCS404_PNOC_INT_0);
 111DEFINE_QNODE(mas_sdcc_2, QCS404_MASTER_SDCC_2, 8, 35, -1, QCS404_PNOC_INT_0);
 112DEFINE_QNODE(mas_snoc_pcnoc, QCS404_SNOC_PNOC_MAS, 8, 77, -1, QCS404_PNOC_INT_2);
 113DEFINE_QNODE(mas_qpic, QCS404_MASTER_QPIC, 4, -1, -1, QCS404_PNOC_INT_0);
 114DEFINE_QNODE(mas_qdss_bam, QCS404_MASTER_QDSS_BAM, 4, -1, -1, QCS404_SNOC_QDSS_INT);
 115DEFINE_QNODE(mas_bimc_snoc, QCS404_BIMC_SNOC_MAS, 8, 21, -1, QCS404_SLAVE_OCMEM_64, QCS404_SLAVE_CATS_128, QCS404_SNOC_INT_0, QCS404_SNOC_INT_1);
 116DEFINE_QNODE(mas_pcnoc_snoc, QCS404_PNOC_SNOC_MAS, 8, 29, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_2, QCS404_SNOC_INT_0);
 117DEFINE_QNODE(mas_qdss_etr, QCS404_MASTER_QDSS_ETR, 8, -1, -1, QCS404_SNOC_QDSS_INT);
 118DEFINE_QNODE(mas_emac, QCS404_MASTER_EMAC, 8, -1, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_1);
 119DEFINE_QNODE(mas_pcie, QCS404_MASTER_PCIE, 8, -1, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_1);
 120DEFINE_QNODE(mas_usb3, QCS404_MASTER_USB3, 8, -1, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_1);
 121DEFINE_QNODE(pcnoc_int_0, QCS404_PNOC_INT_0, 8, 85, 114, QCS404_PNOC_SNOC_SLV, QCS404_PNOC_INT_2);
 122DEFINE_QNODE(pcnoc_int_2, QCS404_PNOC_INT_2, 8, 124, 184, QCS404_PNOC_SLV_10, QCS404_SLAVE_TCU, QCS404_PNOC_SLV_11, QCS404_PNOC_SLV_2, QCS404_PNOC_SLV_3, QCS404_PNOC_SLV_0, QCS404_PNOC_SLV_1, QCS404_PNOC_SLV_6, QCS404_PNOC_SLV_7, QCS404_PNOC_SLV_4, QCS404_PNOC_SLV_8, QCS404_PNOC_SLV_9);
 123DEFINE_QNODE(pcnoc_int_3, QCS404_PNOC_INT_3, 8, 125, 185, QCS404_PNOC_SNOC_SLV);
 124DEFINE_QNODE(pcnoc_s_0, QCS404_PNOC_SLV_0, 4, 89, 118, QCS404_SLAVE_PRNG, QCS404_SLAVE_SPDM_WRAPPER, QCS404_SLAVE_PDM);
 125DEFINE_QNODE(pcnoc_s_1, QCS404_PNOC_SLV_1, 4, 90, 119, QCS404_SLAVE_TCSR);
 126DEFINE_QNODE(pcnoc_s_2, QCS404_PNOC_SLV_2, 4, -1, -1, QCS404_SLAVE_GRAPHICS_3D_CFG);
 127DEFINE_QNODE(pcnoc_s_3, QCS404_PNOC_SLV_3, 4, 92, 121, QCS404_SLAVE_MESSAGE_RAM);
 128DEFINE_QNODE(pcnoc_s_4, QCS404_PNOC_SLV_4, 4, 93, 122, QCS404_SLAVE_SNOC_CFG);
 129DEFINE_QNODE(pcnoc_s_6, QCS404_PNOC_SLV_6, 4, 94, 123, QCS404_SLAVE_BLSP_1, QCS404_SLAVE_TLMM_NORTH, QCS404_SLAVE_EMAC_CFG);
 130DEFINE_QNODE(pcnoc_s_7, QCS404_PNOC_SLV_7, 4, 95, 124, QCS404_SLAVE_TLMM_SOUTH, QCS404_SLAVE_DISPLAY_CFG, QCS404_SLAVE_SDCC_1, QCS404_SLAVE_PCIE_1, QCS404_SLAVE_SDCC_2);
 131DEFINE_QNODE(pcnoc_s_8, QCS404_PNOC_SLV_8, 4, 96, 125, QCS404_SLAVE_CRYPTO_0_CFG);
 132DEFINE_QNODE(pcnoc_s_9, QCS404_PNOC_SLV_9, 4, 97, 126, QCS404_SLAVE_BLSP_2, QCS404_SLAVE_TLMM_EAST, QCS404_SLAVE_PMIC_ARB);
 133DEFINE_QNODE(pcnoc_s_10, QCS404_PNOC_SLV_10, 4, 157, -1, QCS404_SLAVE_USB_HS);
 134DEFINE_QNODE(pcnoc_s_11, QCS404_PNOC_SLV_11, 4, 158, 246, QCS404_SLAVE_USB3);
 135DEFINE_QNODE(qdss_int, QCS404_SNOC_QDSS_INT, 8, -1, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_1);
 136DEFINE_QNODE(snoc_int_0, QCS404_SNOC_INT_0, 8, 99, 130, QCS404_SLAVE_LPASS, QCS404_SLAVE_APPSS, QCS404_SLAVE_WCSS);
 137DEFINE_QNODE(snoc_int_1, QCS404_SNOC_INT_1, 8, 100, 131, QCS404_SNOC_PNOC_SLV, QCS404_SNOC_INT_2);
 138DEFINE_QNODE(snoc_int_2, QCS404_SNOC_INT_2, 8, 134, 197, QCS404_SLAVE_QDSS_STM, QCS404_SLAVE_OCIMEM);
 139DEFINE_QNODE(slv_ebi, QCS404_SLAVE_EBI_CH0, 8, -1, 0, 0);
 140DEFINE_QNODE(slv_bimc_snoc, QCS404_BIMC_SNOC_SLV, 8, -1, 2, QCS404_BIMC_SNOC_MAS);
 141DEFINE_QNODE(slv_spdm, QCS404_SLAVE_SPDM_WRAPPER, 4, -1, -1, 0);
 142DEFINE_QNODE(slv_pdm, QCS404_SLAVE_PDM, 4, -1, 41, 0);
 143DEFINE_QNODE(slv_prng, QCS404_SLAVE_PRNG, 4, -1, 44, 0);
 144DEFINE_QNODE(slv_tcsr, QCS404_SLAVE_TCSR, 4, -1, 50, 0);
 145DEFINE_QNODE(slv_snoc_cfg, QCS404_SLAVE_SNOC_CFG, 4, -1, 70, 0);
 146DEFINE_QNODE(slv_message_ram, QCS404_SLAVE_MESSAGE_RAM, 4, -1, 55, 0);
 147DEFINE_QNODE(slv_disp_ss_cfg, QCS404_SLAVE_DISPLAY_CFG, 4, -1, -1, 0);
 148DEFINE_QNODE(slv_gpu_cfg, QCS404_SLAVE_GRAPHICS_3D_CFG, 4, -1, -1, 0);
 149DEFINE_QNODE(slv_blsp_1, QCS404_SLAVE_BLSP_1, 4, -1, 39, 0);
 150DEFINE_QNODE(slv_tlmm_north, QCS404_SLAVE_TLMM_NORTH, 4, -1, 214, 0);
 151DEFINE_QNODE(slv_pcie, QCS404_SLAVE_PCIE_1, 4, -1, -1, 0);
 152DEFINE_QNODE(slv_ethernet, QCS404_SLAVE_EMAC_CFG, 4, -1, -1, 0);
 153DEFINE_QNODE(slv_blsp_2, QCS404_SLAVE_BLSP_2, 4, -1, 37, 0);
 154DEFINE_QNODE(slv_tlmm_east, QCS404_SLAVE_TLMM_EAST, 4, -1, 213, 0);
 155DEFINE_QNODE(slv_tcu, QCS404_SLAVE_TCU, 8, -1, -1, 0);
 156DEFINE_QNODE(slv_pmic_arb, QCS404_SLAVE_PMIC_ARB, 4, -1, 59, 0);
 157DEFINE_QNODE(slv_sdcc_1, QCS404_SLAVE_SDCC_1, 4, -1, 31, 0);
 158DEFINE_QNODE(slv_sdcc_2, QCS404_SLAVE_SDCC_2, 4, -1, 33, 0);
 159DEFINE_QNODE(slv_tlmm_south, QCS404_SLAVE_TLMM_SOUTH, 4, -1, -1, 0);
 160DEFINE_QNODE(slv_usb_hs, QCS404_SLAVE_USB_HS, 4, -1, 40, 0);
 161DEFINE_QNODE(slv_usb3, QCS404_SLAVE_USB3, 4, -1, 22, 0);
 162DEFINE_QNODE(slv_crypto_0_cfg, QCS404_SLAVE_CRYPTO_0_CFG, 4, -1, 52, 0);
 163DEFINE_QNODE(slv_pcnoc_snoc, QCS404_PNOC_SNOC_SLV, 8, -1, 45, QCS404_PNOC_SNOC_MAS);
 164DEFINE_QNODE(slv_kpss_ahb, QCS404_SLAVE_APPSS, 4, -1, -1, 0);
 165DEFINE_QNODE(slv_wcss, QCS404_SLAVE_WCSS, 4, -1, 23, 0);
 166DEFINE_QNODE(slv_snoc_bimc_1, QCS404_SNOC_BIMC_1_SLV, 8, -1, 104, QCS404_SNOC_BIMC_1_MAS);
 167DEFINE_QNODE(slv_imem, QCS404_SLAVE_OCIMEM, 8, -1, 26, 0);
 168DEFINE_QNODE(slv_snoc_pcnoc, QCS404_SNOC_PNOC_SLV, 8, -1, 28, QCS404_SNOC_PNOC_MAS);
 169DEFINE_QNODE(slv_qdss_stm, QCS404_SLAVE_QDSS_STM, 4, -1, 30, 0);
 170DEFINE_QNODE(slv_cats_0, QCS404_SLAVE_CATS_128, 16, -1, -1, 0);
 171DEFINE_QNODE(slv_cats_1, QCS404_SLAVE_OCMEM_64, 8, -1, -1, 0);
 172DEFINE_QNODE(slv_lpass, QCS404_SLAVE_LPASS, 4, -1, -1, 0);
 173
 174static struct qcom_icc_node *qcs404_bimc_nodes[] = {
 175        [MASTER_AMPSS_M0] = &mas_apps_proc,
 176        [MASTER_OXILI] = &mas_oxili,
 177        [MASTER_MDP_PORT0] = &mas_mdp,
 178        [MASTER_SNOC_BIMC_1] = &mas_snoc_bimc_1,
 179        [MASTER_TCU_0] = &mas_tcu_0,
 180        [SLAVE_EBI_CH0] = &slv_ebi,
 181        [SLAVE_BIMC_SNOC] = &slv_bimc_snoc,
 182};
 183
 184static struct qcom_icc_desc qcs404_bimc = {
 185        .nodes = qcs404_bimc_nodes,
 186        .num_nodes = ARRAY_SIZE(qcs404_bimc_nodes),
 187};
 188
 189static struct qcom_icc_node *qcs404_pcnoc_nodes[] = {
 190        [MASTER_SPDM] = &mas_spdm,
 191        [MASTER_BLSP_1] = &mas_blsp_1,
 192        [MASTER_BLSP_2] = &mas_blsp_2,
 193        [MASTER_XI_USB_HS1] = &mas_xi_usb_hs1,
 194        [MASTER_CRYPT0] = &mas_crypto,
 195        [MASTER_SDCC_1] = &mas_sdcc_1,
 196        [MASTER_SDCC_2] = &mas_sdcc_2,
 197        [MASTER_SNOC_PCNOC] = &mas_snoc_pcnoc,
 198        [MASTER_QPIC] = &mas_qpic,
 199        [PCNOC_INT_0] = &pcnoc_int_0,
 200        [PCNOC_INT_2] = &pcnoc_int_2,
 201        [PCNOC_INT_3] = &pcnoc_int_3,
 202        [PCNOC_S_0] = &pcnoc_s_0,
 203        [PCNOC_S_1] = &pcnoc_s_1,
 204        [PCNOC_S_2] = &pcnoc_s_2,
 205        [PCNOC_S_3] = &pcnoc_s_3,
 206        [PCNOC_S_4] = &pcnoc_s_4,
 207        [PCNOC_S_6] = &pcnoc_s_6,
 208        [PCNOC_S_7] = &pcnoc_s_7,
 209        [PCNOC_S_8] = &pcnoc_s_8,
 210        [PCNOC_S_9] = &pcnoc_s_9,
 211        [PCNOC_S_10] = &pcnoc_s_10,
 212        [PCNOC_S_11] = &pcnoc_s_11,
 213        [SLAVE_SPDM] = &slv_spdm,
 214        [SLAVE_PDM] = &slv_pdm,
 215        [SLAVE_PRNG] = &slv_prng,
 216        [SLAVE_TCSR] = &slv_tcsr,
 217        [SLAVE_SNOC_CFG] = &slv_snoc_cfg,
 218        [SLAVE_MESSAGE_RAM] = &slv_message_ram,
 219        [SLAVE_DISP_SS_CFG] = &slv_disp_ss_cfg,
 220        [SLAVE_GPU_CFG] = &slv_gpu_cfg,
 221        [SLAVE_BLSP_1] = &slv_blsp_1,
 222        [SLAVE_BLSP_2] = &slv_blsp_2,
 223        [SLAVE_TLMM_NORTH] = &slv_tlmm_north,
 224        [SLAVE_PCIE] = &slv_pcie,
 225        [SLAVE_ETHERNET] = &slv_ethernet,
 226        [SLAVE_TLMM_EAST] = &slv_tlmm_east,
 227        [SLAVE_TCU] = &slv_tcu,
 228        [SLAVE_PMIC_ARB] = &slv_pmic_arb,
 229        [SLAVE_SDCC_1] = &slv_sdcc_1,
 230        [SLAVE_SDCC_2] = &slv_sdcc_2,
 231        [SLAVE_TLMM_SOUTH] = &slv_tlmm_south,
 232        [SLAVE_USB_HS] = &slv_usb_hs,
 233        [SLAVE_USB3] = &slv_usb3,
 234        [SLAVE_CRYPTO_0_CFG] = &slv_crypto_0_cfg,
 235        [SLAVE_PCNOC_SNOC] = &slv_pcnoc_snoc,
 236};
 237
 238static struct qcom_icc_desc qcs404_pcnoc = {
 239        .nodes = qcs404_pcnoc_nodes,
 240        .num_nodes = ARRAY_SIZE(qcs404_pcnoc_nodes),
 241};
 242
 243static struct qcom_icc_node *qcs404_snoc_nodes[] = {
 244        [MASTER_QDSS_BAM] = &mas_qdss_bam,
 245        [MASTER_BIMC_SNOC] = &mas_bimc_snoc,
 246        [MASTER_PCNOC_SNOC] = &mas_pcnoc_snoc,
 247        [MASTER_QDSS_ETR] = &mas_qdss_etr,
 248        [MASTER_EMAC] = &mas_emac,
 249        [MASTER_PCIE] = &mas_pcie,
 250        [MASTER_USB3] = &mas_usb3,
 251        [QDSS_INT] = &qdss_int,
 252        [SNOC_INT_0] = &snoc_int_0,
 253        [SNOC_INT_1] = &snoc_int_1,
 254        [SNOC_INT_2] = &snoc_int_2,
 255        [SLAVE_KPSS_AHB] = &slv_kpss_ahb,
 256        [SLAVE_WCSS] = &slv_wcss,
 257        [SLAVE_SNOC_BIMC_1] = &slv_snoc_bimc_1,
 258        [SLAVE_IMEM] = &slv_imem,
 259        [SLAVE_SNOC_PCNOC] = &slv_snoc_pcnoc,
 260        [SLAVE_QDSS_STM] = &slv_qdss_stm,
 261        [SLAVE_CATS_0] = &slv_cats_0,
 262        [SLAVE_CATS_1] = &slv_cats_1,
 263        [SLAVE_LPASS] = &slv_lpass,
 264};
 265
 266static struct qcom_icc_desc qcs404_snoc = {
 267        .nodes = qcs404_snoc_nodes,
 268        .num_nodes = ARRAY_SIZE(qcs404_snoc_nodes),
 269};
 270
 271
 272static int qcs404_qnoc_probe(struct platform_device *pdev)
 273{
 274        return qnoc_probe(pdev, sizeof(qcs404_bus_clocks),
 275                          ARRAY_SIZE(qcs404_bus_clocks), qcs404_bus_clocks);
 276}
 277
 278static const struct of_device_id qcs404_noc_of_match[] = {
 279        { .compatible = "qcom,qcs404-bimc", .data = &qcs404_bimc },
 280        { .compatible = "qcom,qcs404-pcnoc", .data = &qcs404_pcnoc },
 281        { .compatible = "qcom,qcs404-snoc", .data = &qcs404_snoc },
 282        { },
 283};
 284MODULE_DEVICE_TABLE(of, qcs404_noc_of_match);
 285
 286static struct platform_driver qcs404_noc_driver = {
 287        .probe = qcs404_qnoc_probe,
 288        .remove = qnoc_remove,
 289        .driver = {
 290                .name = "qnoc-qcs404",
 291                .of_match_table = qcs404_noc_of_match,
 292        },
 293};
 294module_platform_driver(qcs404_noc_driver);
 295MODULE_DESCRIPTION("Qualcomm QCS404 NoC driver");
 296MODULE_LICENSE("GPL v2");
 297