linux/drivers/edac/skx_common.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 *
   4 * Shared code by both skx_edac and i10nm_edac. Originally split out
   5 * from the skx_edac driver.
   6 *
   7 * This file is linked into both skx_edac and i10nm_edac drivers. In
   8 * order to avoid link errors, this file must be like a pure library
   9 * without including symbols and defines which would otherwise conflict,
  10 * when linked once into a module and into a built-in object, at the
  11 * same time. For example, __this_module symbol references when that
  12 * file is being linked into a built-in object.
  13 *
  14 * Copyright (c) 2018, Intel Corporation.
  15 */
  16
  17#include <linux/acpi.h>
  18#include <linux/dmi.h>
  19#include <linux/adxl.h>
  20#include <acpi/nfit.h>
  21#include <asm/mce.h>
  22#include "edac_module.h"
  23#include "skx_common.h"
  24
  25static const char * const component_names[] = {
  26        [INDEX_SOCKET]          = "ProcessorSocketId",
  27        [INDEX_MEMCTRL]         = "MemoryControllerId",
  28        [INDEX_CHANNEL]         = "ChannelId",
  29        [INDEX_DIMM]            = "DimmSlotId",
  30        [INDEX_NM_MEMCTRL]      = "NmMemoryControllerId",
  31        [INDEX_NM_CHANNEL]      = "NmChannelId",
  32        [INDEX_NM_DIMM]         = "NmDimmSlotId",
  33};
  34
  35static int component_indices[ARRAY_SIZE(component_names)];
  36static int adxl_component_count;
  37static const char * const *adxl_component_names;
  38static u64 *adxl_values;
  39static char *adxl_msg;
  40static unsigned long adxl_nm_bitmap;
  41
  42static char skx_msg[MSG_SIZE];
  43static skx_decode_f skx_decode;
  44static skx_show_retry_log_f skx_show_retry_rd_err_log;
  45static u64 skx_tolm, skx_tohm;
  46static LIST_HEAD(dev_edac_list);
  47static bool skx_mem_cfg_2lm;
  48
  49int __init skx_adxl_get(void)
  50{
  51        const char * const *names;
  52        int i, j;
  53
  54        names = adxl_get_component_names();
  55        if (!names) {
  56                skx_printk(KERN_NOTICE, "No firmware support for address translation.\n");
  57                return -ENODEV;
  58        }
  59
  60        for (i = 0; i < INDEX_MAX; i++) {
  61                for (j = 0; names[j]; j++) {
  62                        if (!strcmp(component_names[i], names[j])) {
  63                                component_indices[i] = j;
  64
  65                                if (i >= INDEX_NM_FIRST)
  66                                        adxl_nm_bitmap |= 1 << i;
  67
  68                                break;
  69                        }
  70                }
  71
  72                if (!names[j] && i < INDEX_NM_FIRST)
  73                        goto err;
  74        }
  75
  76        if (skx_mem_cfg_2lm) {
  77                if (!adxl_nm_bitmap)
  78                        skx_printk(KERN_NOTICE, "Not enough ADXL components for 2-level memory.\n");
  79                else
  80                        edac_dbg(2, "adxl_nm_bitmap: 0x%lx\n", adxl_nm_bitmap);
  81        }
  82
  83        adxl_component_names = names;
  84        while (*names++)
  85                adxl_component_count++;
  86
  87        adxl_values = kcalloc(adxl_component_count, sizeof(*adxl_values),
  88                              GFP_KERNEL);
  89        if (!adxl_values) {
  90                adxl_component_count = 0;
  91                return -ENOMEM;
  92        }
  93
  94        adxl_msg = kzalloc(MSG_SIZE, GFP_KERNEL);
  95        if (!adxl_msg) {
  96                adxl_component_count = 0;
  97                kfree(adxl_values);
  98                return -ENOMEM;
  99        }
 100
 101        return 0;
 102err:
 103        skx_printk(KERN_ERR, "'%s' is not matched from DSM parameters: ",
 104                   component_names[i]);
 105        for (j = 0; names[j]; j++)
 106                skx_printk(KERN_CONT, "%s ", names[j]);
 107        skx_printk(KERN_CONT, "\n");
 108
 109        return -ENODEV;
 110}
 111
 112void __exit skx_adxl_put(void)
 113{
 114        kfree(adxl_values);
 115        kfree(adxl_msg);
 116}
 117
 118static bool skx_adxl_decode(struct decoded_addr *res, bool error_in_1st_level_mem)
 119{
 120        struct skx_dev *d;
 121        int i, len = 0;
 122
 123        if (res->addr >= skx_tohm || (res->addr >= skx_tolm &&
 124                                      res->addr < BIT_ULL(32))) {
 125                edac_dbg(0, "Address 0x%llx out of range\n", res->addr);
 126                return false;
 127        }
 128
 129        if (adxl_decode(res->addr, adxl_values)) {
 130                edac_dbg(0, "Failed to decode 0x%llx\n", res->addr);
 131                return false;
 132        }
 133
 134        res->socket  = (int)adxl_values[component_indices[INDEX_SOCKET]];
 135        if (error_in_1st_level_mem) {
 136                res->imc     = (adxl_nm_bitmap & BIT_NM_MEMCTRL) ?
 137                               (int)adxl_values[component_indices[INDEX_NM_MEMCTRL]] : -1;
 138                res->channel = (adxl_nm_bitmap & BIT_NM_CHANNEL) ?
 139                               (int)adxl_values[component_indices[INDEX_NM_CHANNEL]] : -1;
 140                res->dimm    = (adxl_nm_bitmap & BIT_NM_DIMM) ?
 141                               (int)adxl_values[component_indices[INDEX_NM_DIMM]] : -1;
 142        } else {
 143                res->imc     = (int)adxl_values[component_indices[INDEX_MEMCTRL]];
 144                res->channel = (int)adxl_values[component_indices[INDEX_CHANNEL]];
 145                res->dimm    = (int)adxl_values[component_indices[INDEX_DIMM]];
 146        }
 147
 148        if (res->imc > NUM_IMC - 1 || res->imc < 0) {
 149                skx_printk(KERN_ERR, "Bad imc %d\n", res->imc);
 150                return false;
 151        }
 152
 153        list_for_each_entry(d, &dev_edac_list, list) {
 154                if (d->imc[0].src_id == res->socket) {
 155                        res->dev = d;
 156                        break;
 157                }
 158        }
 159
 160        if (!res->dev) {
 161                skx_printk(KERN_ERR, "No device for src_id %d imc %d\n",
 162                           res->socket, res->imc);
 163                return false;
 164        }
 165
 166        for (i = 0; i < adxl_component_count; i++) {
 167                if (adxl_values[i] == ~0x0ull)
 168                        continue;
 169
 170                len += snprintf(adxl_msg + len, MSG_SIZE - len, " %s:0x%llx",
 171                                adxl_component_names[i], adxl_values[i]);
 172                if (MSG_SIZE - len <= 0)
 173                        break;
 174        }
 175
 176        return true;
 177}
 178
 179void skx_set_mem_cfg(bool mem_cfg_2lm)
 180{
 181        skx_mem_cfg_2lm = mem_cfg_2lm;
 182}
 183
 184void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log)
 185{
 186        skx_decode = decode;
 187        skx_show_retry_rd_err_log = show_retry_log;
 188}
 189
 190int skx_get_src_id(struct skx_dev *d, int off, u8 *id)
 191{
 192        u32 reg;
 193
 194        if (pci_read_config_dword(d->util_all, off, &reg)) {
 195                skx_printk(KERN_ERR, "Failed to read src id\n");
 196                return -ENODEV;
 197        }
 198
 199        *id = GET_BITFIELD(reg, 12, 14);
 200        return 0;
 201}
 202
 203int skx_get_node_id(struct skx_dev *d, u8 *id)
 204{
 205        u32 reg;
 206
 207        if (pci_read_config_dword(d->util_all, 0xf4, &reg)) {
 208                skx_printk(KERN_ERR, "Failed to read node id\n");
 209                return -ENODEV;
 210        }
 211
 212        *id = GET_BITFIELD(reg, 0, 2);
 213        return 0;
 214}
 215
 216static int get_width(u32 mtr)
 217{
 218        switch (GET_BITFIELD(mtr, 8, 9)) {
 219        case 0:
 220                return DEV_X4;
 221        case 1:
 222                return DEV_X8;
 223        case 2:
 224                return DEV_X16;
 225        }
 226        return DEV_UNKNOWN;
 227}
 228
 229/*
 230 * We use the per-socket device @cfg->did to count how many sockets are present,
 231 * and to detemine which PCI buses are associated with each socket. Allocate
 232 * and build the full list of all the skx_dev structures that we need here.
 233 */
 234int skx_get_all_bus_mappings(struct res_config *cfg, struct list_head **list)
 235{
 236        struct pci_dev *pdev, *prev;
 237        struct skx_dev *d;
 238        u32 reg;
 239        int ndev = 0;
 240
 241        prev = NULL;
 242        for (;;) {
 243                pdev = pci_get_device(PCI_VENDOR_ID_INTEL, cfg->decs_did, prev);
 244                if (!pdev)
 245                        break;
 246                ndev++;
 247                d = kzalloc(sizeof(*d), GFP_KERNEL);
 248                if (!d) {
 249                        pci_dev_put(pdev);
 250                        return -ENOMEM;
 251                }
 252
 253                if (pci_read_config_dword(pdev, cfg->busno_cfg_offset, &reg)) {
 254                        kfree(d);
 255                        pci_dev_put(pdev);
 256                        skx_printk(KERN_ERR, "Failed to read bus idx\n");
 257                        return -ENODEV;
 258                }
 259
 260                d->bus[0] = GET_BITFIELD(reg, 0, 7);
 261                d->bus[1] = GET_BITFIELD(reg, 8, 15);
 262                if (cfg->type == SKX) {
 263                        d->seg = pci_domain_nr(pdev->bus);
 264                        d->bus[2] = GET_BITFIELD(reg, 16, 23);
 265                        d->bus[3] = GET_BITFIELD(reg, 24, 31);
 266                } else {
 267                        d->seg = GET_BITFIELD(reg, 16, 23);
 268                }
 269
 270                edac_dbg(2, "busses: 0x%x, 0x%x, 0x%x, 0x%x\n",
 271                         d->bus[0], d->bus[1], d->bus[2], d->bus[3]);
 272                list_add_tail(&d->list, &dev_edac_list);
 273                prev = pdev;
 274        }
 275
 276        if (list)
 277                *list = &dev_edac_list;
 278        return ndev;
 279}
 280
 281int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm)
 282{
 283        struct pci_dev *pdev;
 284        u32 reg;
 285
 286        pdev = pci_get_device(PCI_VENDOR_ID_INTEL, did, NULL);
 287        if (!pdev) {
 288                edac_dbg(2, "Can't get tolm/tohm\n");
 289                return -ENODEV;
 290        }
 291
 292        if (pci_read_config_dword(pdev, off[0], &reg)) {
 293                skx_printk(KERN_ERR, "Failed to read tolm\n");
 294                goto fail;
 295        }
 296        skx_tolm = reg;
 297
 298        if (pci_read_config_dword(pdev, off[1], &reg)) {
 299                skx_printk(KERN_ERR, "Failed to read lower tohm\n");
 300                goto fail;
 301        }
 302        skx_tohm = reg;
 303
 304        if (pci_read_config_dword(pdev, off[2], &reg)) {
 305                skx_printk(KERN_ERR, "Failed to read upper tohm\n");
 306                goto fail;
 307        }
 308        skx_tohm |= (u64)reg << 32;
 309
 310        pci_dev_put(pdev);
 311        *tolm = skx_tolm;
 312        *tohm = skx_tohm;
 313        edac_dbg(2, "tolm = 0x%llx tohm = 0x%llx\n", skx_tolm, skx_tohm);
 314        return 0;
 315fail:
 316        pci_dev_put(pdev);
 317        return -ENODEV;
 318}
 319
 320static int skx_get_dimm_attr(u32 reg, int lobit, int hibit, int add,
 321                             int minval, int maxval, const char *name)
 322{
 323        u32 val = GET_BITFIELD(reg, lobit, hibit);
 324
 325        if (val < minval || val > maxval) {
 326                edac_dbg(2, "bad %s = %d (raw=0x%x)\n", name, val, reg);
 327                return -EINVAL;
 328        }
 329        return val + add;
 330}
 331
 332#define numrank(reg)    skx_get_dimm_attr(reg, 12, 13, 0, 0, 2, "ranks")
 333#define numrow(reg)     skx_get_dimm_attr(reg, 2, 4, 12, 1, 6, "rows")
 334#define numcol(reg)     skx_get_dimm_attr(reg, 0, 1, 10, 0, 2, "cols")
 335
 336int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,
 337                      struct skx_imc *imc, int chan, int dimmno,
 338                      struct res_config *cfg)
 339{
 340        int  banks, ranks, rows, cols, npages;
 341        enum mem_type mtype;
 342        u64 size;
 343
 344        ranks = numrank(mtr);
 345        rows = numrow(mtr);
 346        cols = imc->hbm_mc ? 6 : numcol(mtr);
 347
 348        if (cfg->support_ddr5 && ((amap & 0x8) || imc->hbm_mc)) {
 349                banks = 32;
 350                mtype = MEM_DDR5;
 351        } else {
 352                banks = 16;
 353                mtype = MEM_DDR4;
 354        }
 355
 356        /*
 357         * Compute size in 8-byte (2^3) words, then shift to MiB (2^20)
 358         */
 359        size = ((1ull << (rows + cols + ranks)) * banks) >> (20 - 3);
 360        npages = MiB_TO_PAGES(size);
 361
 362        edac_dbg(0, "mc#%d: channel %d, dimm %d, %lld MiB (%d pages) bank: %d, rank: %d, row: 0x%x, col: 0x%x\n",
 363                 imc->mc, chan, dimmno, size, npages,
 364                 banks, 1 << ranks, rows, cols);
 365
 366        imc->chan[chan].dimms[dimmno].close_pg = GET_BITFIELD(mcmtr, 0, 0);
 367        imc->chan[chan].dimms[dimmno].bank_xor_enable = GET_BITFIELD(mcmtr, 9, 9);
 368        imc->chan[chan].dimms[dimmno].fine_grain_bank = GET_BITFIELD(amap, 0, 0);
 369        imc->chan[chan].dimms[dimmno].rowbits = rows;
 370        imc->chan[chan].dimms[dimmno].colbits = cols;
 371
 372        dimm->nr_pages = npages;
 373        dimm->grain = 32;
 374        dimm->dtype = get_width(mtr);
 375        dimm->mtype = mtype;
 376        dimm->edac_mode = EDAC_SECDED; /* likely better than this */
 377
 378        if (imc->hbm_mc)
 379                snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_HBMC#%u_Chan#%u",
 380                         imc->src_id, imc->lmc, chan);
 381        else
 382                snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u",
 383                         imc->src_id, imc->lmc, chan, dimmno);
 384
 385        return 1;
 386}
 387
 388int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc,
 389                        int chan, int dimmno, const char *mod_str)
 390{
 391        int smbios_handle;
 392        u32 dev_handle;
 393        u16 flags;
 394        u64 size = 0;
 395
 396        dev_handle = ACPI_NFIT_BUILD_DEVICE_HANDLE(dimmno, chan, imc->lmc,
 397                                                   imc->src_id, 0);
 398
 399        smbios_handle = nfit_get_smbios_id(dev_handle, &flags);
 400        if (smbios_handle == -EOPNOTSUPP) {
 401                pr_warn_once("%s: Can't find size of NVDIMM. Try enabling CONFIG_ACPI_NFIT\n", mod_str);
 402                goto unknown_size;
 403        }
 404
 405        if (smbios_handle < 0) {
 406                skx_printk(KERN_ERR, "Can't find handle for NVDIMM ADR=0x%x\n", dev_handle);
 407                goto unknown_size;
 408        }
 409
 410        if (flags & ACPI_NFIT_MEM_MAP_FAILED) {
 411                skx_printk(KERN_ERR, "NVDIMM ADR=0x%x is not mapped\n", dev_handle);
 412                goto unknown_size;
 413        }
 414
 415        size = dmi_memdev_size(smbios_handle);
 416        if (size == ~0ull)
 417                skx_printk(KERN_ERR, "Can't find size for NVDIMM ADR=0x%x/SMBIOS=0x%x\n",
 418                           dev_handle, smbios_handle);
 419
 420unknown_size:
 421        dimm->nr_pages = size >> PAGE_SHIFT;
 422        dimm->grain = 32;
 423        dimm->dtype = DEV_UNKNOWN;
 424        dimm->mtype = MEM_NVDIMM;
 425        dimm->edac_mode = EDAC_SECDED; /* likely better than this */
 426
 427        edac_dbg(0, "mc#%d: channel %d, dimm %d, %llu MiB (%u pages)\n",
 428                 imc->mc, chan, dimmno, size >> 20, dimm->nr_pages);
 429
 430        snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u",
 431                 imc->src_id, imc->lmc, chan, dimmno);
 432
 433        return (size == 0 || size == ~0ull) ? 0 : 1;
 434}
 435
 436int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev,
 437                     const char *ctl_name, const char *mod_str,
 438                     get_dimm_config_f get_dimm_config,
 439                     struct res_config *cfg)
 440{
 441        struct mem_ctl_info *mci;
 442        struct edac_mc_layer layers[2];
 443        struct skx_pvt *pvt;
 444        int rc;
 445
 446        /* Allocate a new MC control structure */
 447        layers[0].type = EDAC_MC_LAYER_CHANNEL;
 448        layers[0].size = NUM_CHANNELS;
 449        layers[0].is_virt_csrow = false;
 450        layers[1].type = EDAC_MC_LAYER_SLOT;
 451        layers[1].size = NUM_DIMMS;
 452        layers[1].is_virt_csrow = true;
 453        mci = edac_mc_alloc(imc->mc, ARRAY_SIZE(layers), layers,
 454                            sizeof(struct skx_pvt));
 455
 456        if (unlikely(!mci))
 457                return -ENOMEM;
 458
 459        edac_dbg(0, "MC#%d: mci = %p\n", imc->mc, mci);
 460
 461        /* Associate skx_dev and mci for future usage */
 462        imc->mci = mci;
 463        pvt = mci->pvt_info;
 464        pvt->imc = imc;
 465
 466        mci->ctl_name = kasprintf(GFP_KERNEL, "%s#%d IMC#%d", ctl_name,
 467                                  imc->node_id, imc->lmc);
 468        if (!mci->ctl_name) {
 469                rc = -ENOMEM;
 470                goto fail0;
 471        }
 472
 473        mci->mtype_cap = MEM_FLAG_DDR4 | MEM_FLAG_NVDIMM;
 474        if (cfg->support_ddr5)
 475                mci->mtype_cap |= MEM_FLAG_DDR5;
 476        mci->edac_ctl_cap = EDAC_FLAG_NONE;
 477        mci->edac_cap = EDAC_FLAG_NONE;
 478        mci->mod_name = mod_str;
 479        mci->dev_name = pci_name(pdev);
 480        mci->ctl_page_to_phys = NULL;
 481
 482        rc = get_dimm_config(mci, cfg);
 483        if (rc < 0)
 484                goto fail;
 485
 486        /* Record ptr to the generic device */
 487        mci->pdev = &pdev->dev;
 488
 489        /* Add this new MC control structure to EDAC's list of MCs */
 490        if (unlikely(edac_mc_add_mc(mci))) {
 491                edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
 492                rc = -EINVAL;
 493                goto fail;
 494        }
 495
 496        return 0;
 497
 498fail:
 499        kfree(mci->ctl_name);
 500fail0:
 501        edac_mc_free(mci);
 502        imc->mci = NULL;
 503        return rc;
 504}
 505
 506static void skx_unregister_mci(struct skx_imc *imc)
 507{
 508        struct mem_ctl_info *mci = imc->mci;
 509
 510        if (!mci)
 511                return;
 512
 513        edac_dbg(0, "MC%d: mci = %p\n", imc->mc, mci);
 514
 515        /* Remove MC sysfs nodes */
 516        edac_mc_del_mc(mci->pdev);
 517
 518        edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
 519        kfree(mci->ctl_name);
 520        edac_mc_free(mci);
 521}
 522
 523static void skx_mce_output_error(struct mem_ctl_info *mci,
 524                                 const struct mce *m,
 525                                 struct decoded_addr *res)
 526{
 527        enum hw_event_mc_err_type tp_event;
 528        char *optype;
 529        bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
 530        bool overflow = GET_BITFIELD(m->status, 62, 62);
 531        bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
 532        bool recoverable;
 533        int len;
 534        u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
 535        u32 mscod = GET_BITFIELD(m->status, 16, 31);
 536        u32 errcode = GET_BITFIELD(m->status, 0, 15);
 537        u32 optypenum = GET_BITFIELD(m->status, 4, 6);
 538
 539        recoverable = GET_BITFIELD(m->status, 56, 56);
 540
 541        if (uncorrected_error) {
 542                core_err_cnt = 1;
 543                if (ripv) {
 544                        tp_event = HW_EVENT_ERR_UNCORRECTED;
 545                } else {
 546                        tp_event = HW_EVENT_ERR_FATAL;
 547                }
 548        } else {
 549                tp_event = HW_EVENT_ERR_CORRECTED;
 550        }
 551
 552        /*
 553         * According to Intel Architecture spec vol 3B,
 554         * Table 15-10 "IA32_MCi_Status [15:0] Compound Error Code Encoding"
 555         * memory errors should fit one of these masks:
 556         *      000f 0000 1mmm cccc (binary)
 557         *      000f 0010 1mmm cccc (binary)    [RAM used as cache]
 558         * where:
 559         *      f = Correction Report Filtering Bit. If 1, subsequent errors
 560         *          won't be shown
 561         *      mmm = error type
 562         *      cccc = channel
 563         * If the mask doesn't match, report an error to the parsing logic
 564         */
 565        if (!((errcode & 0xef80) == 0x80 || (errcode & 0xef80) == 0x280)) {
 566                optype = "Can't parse: it is not a mem";
 567        } else {
 568                switch (optypenum) {
 569                case 0:
 570                        optype = "generic undef request error";
 571                        break;
 572                case 1:
 573                        optype = "memory read error";
 574                        break;
 575                case 2:
 576                        optype = "memory write error";
 577                        break;
 578                case 3:
 579                        optype = "addr/cmd error";
 580                        break;
 581                case 4:
 582                        optype = "memory scrubbing error";
 583                        break;
 584                default:
 585                        optype = "reserved";
 586                        break;
 587                }
 588        }
 589        if (adxl_component_count) {
 590                len = snprintf(skx_msg, MSG_SIZE, "%s%s err_code:0x%04x:0x%04x %s",
 591                         overflow ? " OVERFLOW" : "",
 592                         (uncorrected_error && recoverable) ? " recoverable" : "",
 593                         mscod, errcode, adxl_msg);
 594        } else {
 595                len = snprintf(skx_msg, MSG_SIZE,
 596                         "%s%s err_code:0x%04x:0x%04x socket:%d imc:%d rank:%d bg:%d ba:%d row:0x%x col:0x%x",
 597                         overflow ? " OVERFLOW" : "",
 598                         (uncorrected_error && recoverable) ? " recoverable" : "",
 599                         mscod, errcode,
 600                         res->socket, res->imc, res->rank,
 601                         res->bank_group, res->bank_address, res->row, res->column);
 602        }
 603
 604        if (skx_show_retry_rd_err_log)
 605                skx_show_retry_rd_err_log(res, skx_msg + len, MSG_SIZE - len);
 606
 607        edac_dbg(0, "%s\n", skx_msg);
 608
 609        /* Call the helper to output message */
 610        edac_mc_handle_error(tp_event, mci, core_err_cnt,
 611                             m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
 612                             res->channel, res->dimm, -1,
 613                             optype, skx_msg);
 614}
 615
 616static bool skx_error_in_1st_level_mem(const struct mce *m)
 617{
 618        u32 errcode;
 619
 620        if (!skx_mem_cfg_2lm)
 621                return false;
 622
 623        errcode = GET_BITFIELD(m->status, 0, 15);
 624
 625        if ((errcode & 0xef80) != 0x280)
 626                return false;
 627
 628        return true;
 629}
 630
 631int skx_mce_check_error(struct notifier_block *nb, unsigned long val,
 632                        void *data)
 633{
 634        struct mce *mce = (struct mce *)data;
 635        struct decoded_addr res;
 636        struct mem_ctl_info *mci;
 637        char *type;
 638
 639        if (mce->kflags & MCE_HANDLED_CEC)
 640                return NOTIFY_DONE;
 641
 642        /* ignore unless this is memory related with an address */
 643        if ((mce->status & 0xefff) >> 7 != 1 || !(mce->status & MCI_STATUS_ADDRV))
 644                return NOTIFY_DONE;
 645
 646        memset(&res, 0, sizeof(res));
 647        res.addr = mce->addr;
 648
 649        if (adxl_component_count) {
 650                if (!skx_adxl_decode(&res, skx_error_in_1st_level_mem(mce)))
 651                        return NOTIFY_DONE;
 652        } else if (!skx_decode || !skx_decode(&res)) {
 653                return NOTIFY_DONE;
 654        }
 655
 656        mci = res.dev->imc[res.imc].mci;
 657
 658        if (!mci)
 659                return NOTIFY_DONE;
 660
 661        if (mce->mcgstatus & MCG_STATUS_MCIP)
 662                type = "Exception";
 663        else
 664                type = "Event";
 665
 666        skx_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
 667
 668        skx_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: 0x%llx "
 669                           "Bank %d: 0x%llx\n", mce->extcpu, type,
 670                           mce->mcgstatus, mce->bank, mce->status);
 671        skx_mc_printk(mci, KERN_DEBUG, "TSC 0x%llx ", mce->tsc);
 672        skx_mc_printk(mci, KERN_DEBUG, "ADDR 0x%llx ", mce->addr);
 673        skx_mc_printk(mci, KERN_DEBUG, "MISC 0x%llx ", mce->misc);
 674
 675        skx_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:0x%x TIME %llu SOCKET "
 676                           "%u APIC 0x%x\n", mce->cpuvendor, mce->cpuid,
 677                           mce->time, mce->socketid, mce->apicid);
 678
 679        skx_mce_output_error(mci, mce, &res);
 680
 681        mce->kflags |= MCE_HANDLED_EDAC;
 682        return NOTIFY_DONE;
 683}
 684
 685void skx_remove(void)
 686{
 687        int i, j;
 688        struct skx_dev *d, *tmp;
 689
 690        edac_dbg(0, "\n");
 691
 692        list_for_each_entry_safe(d, tmp, &dev_edac_list, list) {
 693                list_del(&d->list);
 694                for (i = 0; i < NUM_IMC; i++) {
 695                        if (d->imc[i].mci)
 696                                skx_unregister_mci(&d->imc[i]);
 697
 698                        if (d->imc[i].mdev)
 699                                pci_dev_put(d->imc[i].mdev);
 700
 701                        if (d->imc[i].mbase)
 702                                iounmap(d->imc[i].mbase);
 703
 704                        for (j = 0; j < NUM_CHANNELS; j++) {
 705                                if (d->imc[i].chan[j].cdev)
 706                                        pci_dev_put(d->imc[i].chan[j].cdev);
 707                        }
 708                }
 709                if (d->util_all)
 710                        pci_dev_put(d->util_all);
 711                if (d->pcu_cr3)
 712                        pci_dev_put(d->pcu_cr3);
 713                if (d->sad_all)
 714                        pci_dev_put(d->sad_all);
 715                if (d->uracu)
 716                        pci_dev_put(d->uracu);
 717
 718                kfree(d);
 719        }
 720}
 721