linux/drivers/edac/altera_edac.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 *  Copyright (C) 2017-2018, Intel Corporation. All rights reserved
   4 *  Copyright Altera Corporation (C) 2014-2016. All rights reserved.
   5 *  Copyright 2011-2012 Calxeda, Inc.
   6 */
   7
   8#include <asm/cacheflush.h>
   9#include <linux/ctype.h>
  10#include <linux/delay.h>
  11#include <linux/edac.h>
  12#include <linux/firmware/intel/stratix10-smc.h>
  13#include <linux/genalloc.h>
  14#include <linux/interrupt.h>
  15#include <linux/irqchip/chained_irq.h>
  16#include <linux/kernel.h>
  17#include <linux/mfd/altera-sysmgr.h>
  18#include <linux/mfd/syscon.h>
  19#include <linux/notifier.h>
  20#include <linux/of_address.h>
  21#include <linux/of_irq.h>
  22#include <linux/of_platform.h>
  23#include <linux/panic_notifier.h>
  24#include <linux/platform_device.h>
  25#include <linux/regmap.h>
  26#include <linux/types.h>
  27#include <linux/uaccess.h>
  28
  29#include "altera_edac.h"
  30#include "edac_module.h"
  31
  32#define EDAC_MOD_STR            "altera_edac"
  33#define EDAC_DEVICE             "Altera"
  34
  35#ifdef CONFIG_EDAC_ALTERA_SDRAM
  36static const struct altr_sdram_prv_data c5_data = {
  37        .ecc_ctrl_offset    = CV_CTLCFG_OFST,
  38        .ecc_ctl_en_mask    = CV_CTLCFG_ECC_AUTO_EN,
  39        .ecc_stat_offset    = CV_DRAMSTS_OFST,
  40        .ecc_stat_ce_mask   = CV_DRAMSTS_SBEERR,
  41        .ecc_stat_ue_mask   = CV_DRAMSTS_DBEERR,
  42        .ecc_saddr_offset   = CV_ERRADDR_OFST,
  43        .ecc_daddr_offset   = CV_ERRADDR_OFST,
  44        .ecc_cecnt_offset   = CV_SBECOUNT_OFST,
  45        .ecc_uecnt_offset   = CV_DBECOUNT_OFST,
  46        .ecc_irq_en_offset  = CV_DRAMINTR_OFST,
  47        .ecc_irq_en_mask    = CV_DRAMINTR_INTREN,
  48        .ecc_irq_clr_offset = CV_DRAMINTR_OFST,
  49        .ecc_irq_clr_mask   = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN),
  50        .ecc_cnt_rst_offset = CV_DRAMINTR_OFST,
  51        .ecc_cnt_rst_mask   = CV_DRAMINTR_INTRCLR,
  52        .ce_ue_trgr_offset  = CV_CTLCFG_OFST,
  53        .ce_set_mask        = CV_CTLCFG_GEN_SB_ERR,
  54        .ue_set_mask        = CV_CTLCFG_GEN_DB_ERR,
  55};
  56
  57static const struct altr_sdram_prv_data a10_data = {
  58        .ecc_ctrl_offset    = A10_ECCCTRL1_OFST,
  59        .ecc_ctl_en_mask    = A10_ECCCTRL1_ECC_EN,
  60        .ecc_stat_offset    = A10_INTSTAT_OFST,
  61        .ecc_stat_ce_mask   = A10_INTSTAT_SBEERR,
  62        .ecc_stat_ue_mask   = A10_INTSTAT_DBEERR,
  63        .ecc_saddr_offset   = A10_SERRADDR_OFST,
  64        .ecc_daddr_offset   = A10_DERRADDR_OFST,
  65        .ecc_irq_en_offset  = A10_ERRINTEN_OFST,
  66        .ecc_irq_en_mask    = A10_ECC_IRQ_EN_MASK,
  67        .ecc_irq_clr_offset = A10_INTSTAT_OFST,
  68        .ecc_irq_clr_mask   = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),
  69        .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST,
  70        .ecc_cnt_rst_mask   = A10_ECC_CNT_RESET_MASK,
  71        .ce_ue_trgr_offset  = A10_DIAGINTTEST_OFST,
  72        .ce_set_mask        = A10_DIAGINT_TSERRA_MASK,
  73        .ue_set_mask        = A10_DIAGINT_TDERRA_MASK,
  74};
  75
  76/*********************** EDAC Memory Controller Functions ****************/
  77
  78/* The SDRAM controller uses the EDAC Memory Controller framework.       */
  79
  80static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
  81{
  82        struct mem_ctl_info *mci = dev_id;
  83        struct altr_sdram_mc_data *drvdata = mci->pvt_info;
  84        const struct altr_sdram_prv_data *priv = drvdata->data;
  85        u32 status, err_count = 1, err_addr;
  86
  87        regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status);
  88
  89        if (status & priv->ecc_stat_ue_mask) {
  90                regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset,
  91                            &err_addr);
  92                if (priv->ecc_uecnt_offset)
  93                        regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset,
  94                                    &err_count);
  95                panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
  96                      err_count, err_addr);
  97        }
  98        if (status & priv->ecc_stat_ce_mask) {
  99                regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset,
 100                            &err_addr);
 101                if (priv->ecc_uecnt_offset)
 102                        regmap_read(drvdata->mc_vbase,  priv->ecc_cecnt_offset,
 103                                    &err_count);
 104                edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
 105                                     err_addr >> PAGE_SHIFT,
 106                                     err_addr & ~PAGE_MASK, 0,
 107                                     0, 0, -1, mci->ctl_name, "");
 108                /* Clear IRQ to resume */
 109                regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset,
 110                             priv->ecc_irq_clr_mask);
 111
 112                return IRQ_HANDLED;
 113        }
 114        return IRQ_NONE;
 115}
 116
 117static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
 118                                            const char __user *data,
 119                                            size_t count, loff_t *ppos)
 120{
 121        struct mem_ctl_info *mci = file->private_data;
 122        struct altr_sdram_mc_data *drvdata = mci->pvt_info;
 123        const struct altr_sdram_prv_data *priv = drvdata->data;
 124        u32 *ptemp;
 125        dma_addr_t dma_handle;
 126        u32 reg, read_reg;
 127
 128        ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL);
 129        if (!ptemp) {
 130                dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
 131                edac_printk(KERN_ERR, EDAC_MC,
 132                            "Inject: Buffer Allocation error\n");
 133                return -ENOMEM;
 134        }
 135
 136        regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
 137                    &read_reg);
 138        read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask);
 139
 140        /* Error are injected by writing a word while the SBE or DBE
 141         * bit in the CTLCFG register is set. Reading the word will
 142         * trigger the SBE or DBE error and the corresponding IRQ.
 143         */
 144        if (count == 3) {
 145                edac_printk(KERN_ALERT, EDAC_MC,
 146                            "Inject Double bit error\n");
 147                local_irq_disable();
 148                regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
 149                             (read_reg | priv->ue_set_mask));
 150                local_irq_enable();
 151        } else {
 152                edac_printk(KERN_ALERT, EDAC_MC,
 153                            "Inject Single bit error\n");
 154                local_irq_disable();
 155                regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
 156                             (read_reg | priv->ce_set_mask));
 157                local_irq_enable();
 158        }
 159
 160        ptemp[0] = 0x5A5A5A5A;
 161        ptemp[1] = 0xA5A5A5A5;
 162
 163        /* Clear the error injection bits */
 164        regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg);
 165        /* Ensure it has been written out */
 166        wmb();
 167
 168        /*
 169         * To trigger the error, we need to read the data back
 170         * (the data was written with errors above).
 171         * The READ_ONCE macros and printk are used to prevent the
 172         * the compiler optimizing these reads out.
 173         */
 174        reg = READ_ONCE(ptemp[0]);
 175        read_reg = READ_ONCE(ptemp[1]);
 176        /* Force Read */
 177        rmb();
 178
 179        edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n",
 180                    reg, read_reg);
 181
 182        dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
 183
 184        return count;
 185}
 186
 187static const struct file_operations altr_sdr_mc_debug_inject_fops = {
 188        .open = simple_open,
 189        .write = altr_sdr_mc_err_inject_write,
 190        .llseek = generic_file_llseek,
 191};
 192
 193static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
 194{
 195        if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
 196                return;
 197
 198        if (!mci->debugfs)
 199                return;
 200
 201        edac_debugfs_create_file("altr_trigger", S_IWUSR, mci->debugfs, mci,
 202                                 &altr_sdr_mc_debug_inject_fops);
 203}
 204
 205/* Get total memory size from Open Firmware DTB */
 206static unsigned long get_total_mem(void)
 207{
 208        struct device_node *np = NULL;
 209        struct resource res;
 210        int ret;
 211        unsigned long total_mem = 0;
 212
 213        for_each_node_by_type(np, "memory") {
 214                ret = of_address_to_resource(np, 0, &res);
 215                if (ret)
 216                        continue;
 217
 218                total_mem += resource_size(&res);
 219        }
 220        edac_dbg(0, "total_mem 0x%lx\n", total_mem);
 221        return total_mem;
 222}
 223
 224static const struct of_device_id altr_sdram_ctrl_of_match[] = {
 225        { .compatible = "altr,sdram-edac", .data = &c5_data},
 226        { .compatible = "altr,sdram-edac-a10", .data = &a10_data},
 227        {},
 228};
 229MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
 230
 231static int a10_init(struct regmap *mc_vbase)
 232{
 233        if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST,
 234                               A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) {
 235                edac_printk(KERN_ERR, EDAC_MC,
 236                            "Error setting SB IRQ mode\n");
 237                return -ENODEV;
 238        }
 239
 240        if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) {
 241                edac_printk(KERN_ERR, EDAC_MC,
 242                            "Error setting trigger count\n");
 243                return -ENODEV;
 244        }
 245
 246        return 0;
 247}
 248
 249static int a10_unmask_irq(struct platform_device *pdev, u32 mask)
 250{
 251        void __iomem  *sm_base;
 252        int  ret = 0;
 253
 254        if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32),
 255                                dev_name(&pdev->dev))) {
 256                edac_printk(KERN_ERR, EDAC_MC,
 257                            "Unable to request mem region\n");
 258                return -EBUSY;
 259        }
 260
 261        sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32));
 262        if (!sm_base) {
 263                edac_printk(KERN_ERR, EDAC_MC,
 264                            "Unable to ioremap device\n");
 265
 266                ret = -ENOMEM;
 267                goto release;
 268        }
 269
 270        iowrite32(mask, sm_base);
 271
 272        iounmap(sm_base);
 273
 274release:
 275        release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32));
 276
 277        return ret;
 278}
 279
 280static int altr_sdram_probe(struct platform_device *pdev)
 281{
 282        const struct of_device_id *id;
 283        struct edac_mc_layer layers[2];
 284        struct mem_ctl_info *mci;
 285        struct altr_sdram_mc_data *drvdata;
 286        const struct altr_sdram_prv_data *priv;
 287        struct regmap *mc_vbase;
 288        struct dimm_info *dimm;
 289        u32 read_reg;
 290        int irq, irq2, res = 0;
 291        unsigned long mem_size, irqflags = 0;
 292
 293        id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev);
 294        if (!id)
 295                return -ENODEV;
 296
 297        /* Grab the register range from the sdr controller in device tree */
 298        mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
 299                                                   "altr,sdr-syscon");
 300        if (IS_ERR(mc_vbase)) {
 301                edac_printk(KERN_ERR, EDAC_MC,
 302                            "regmap for altr,sdr-syscon lookup failed.\n");
 303                return -ENODEV;
 304        }
 305
 306        /* Check specific dependencies for the module */
 307        priv = of_match_node(altr_sdram_ctrl_of_match,
 308                             pdev->dev.of_node)->data;
 309
 310        /* Validate the SDRAM controller has ECC enabled */
 311        if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) ||
 312            ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
 313                edac_printk(KERN_ERR, EDAC_MC,
 314                            "No ECC/ECC disabled [0x%08X]\n", read_reg);
 315                return -ENODEV;
 316        }
 317
 318        /* Grab memory size from device tree. */
 319        mem_size = get_total_mem();
 320        if (!mem_size) {
 321                edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
 322                return -ENODEV;
 323        }
 324
 325        /* Ensure the SDRAM Interrupt is disabled */
 326        if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset,
 327                               priv->ecc_irq_en_mask, 0)) {
 328                edac_printk(KERN_ERR, EDAC_MC,
 329                            "Error disabling SDRAM ECC IRQ\n");
 330                return -ENODEV;
 331        }
 332
 333        /* Toggle to clear the SDRAM Error count */
 334        if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
 335                               priv->ecc_cnt_rst_mask,
 336                               priv->ecc_cnt_rst_mask)) {
 337                edac_printk(KERN_ERR, EDAC_MC,
 338                            "Error clearing SDRAM ECC count\n");
 339                return -ENODEV;
 340        }
 341
 342        if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
 343                               priv->ecc_cnt_rst_mask, 0)) {
 344                edac_printk(KERN_ERR, EDAC_MC,
 345                            "Error clearing SDRAM ECC count\n");
 346                return -ENODEV;
 347        }
 348
 349        irq = platform_get_irq(pdev, 0);
 350        if (irq < 0) {
 351                edac_printk(KERN_ERR, EDAC_MC,
 352                            "No irq %d in DT\n", irq);
 353                return -ENODEV;
 354        }
 355
 356        /* Arria10 has a 2nd IRQ */
 357        irq2 = platform_get_irq(pdev, 1);
 358
 359        layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
 360        layers[0].size = 1;
 361        layers[0].is_virt_csrow = true;
 362        layers[1].type = EDAC_MC_LAYER_CHANNEL;
 363        layers[1].size = 1;
 364        layers[1].is_virt_csrow = false;
 365        mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
 366                            sizeof(struct altr_sdram_mc_data));
 367        if (!mci)
 368                return -ENOMEM;
 369
 370        mci->pdev = &pdev->dev;
 371        drvdata = mci->pvt_info;
 372        drvdata->mc_vbase = mc_vbase;
 373        drvdata->data = priv;
 374        platform_set_drvdata(pdev, mci);
 375
 376        if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
 377                edac_printk(KERN_ERR, EDAC_MC,
 378                            "Unable to get managed device resource\n");
 379                res = -ENOMEM;
 380                goto free;
 381        }
 382
 383        mci->mtype_cap = MEM_FLAG_DDR3;
 384        mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
 385        mci->edac_cap = EDAC_FLAG_SECDED;
 386        mci->mod_name = EDAC_MOD_STR;
 387        mci->ctl_name = dev_name(&pdev->dev);
 388        mci->scrub_mode = SCRUB_SW_SRC;
 389        mci->dev_name = dev_name(&pdev->dev);
 390
 391        dimm = *mci->dimms;
 392        dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
 393        dimm->grain = 8;
 394        dimm->dtype = DEV_X8;
 395        dimm->mtype = MEM_DDR3;
 396        dimm->edac_mode = EDAC_SECDED;
 397
 398        res = edac_mc_add_mc(mci);
 399        if (res < 0)
 400                goto err;
 401
 402        /* Only the Arria10 has separate IRQs */
 403        if (of_machine_is_compatible("altr,socfpga-arria10")) {
 404                /* Arria10 specific initialization */
 405                res = a10_init(mc_vbase);
 406                if (res < 0)
 407                        goto err2;
 408
 409                res = devm_request_irq(&pdev->dev, irq2,
 410                                       altr_sdram_mc_err_handler,
 411                                       IRQF_SHARED, dev_name(&pdev->dev), mci);
 412                if (res < 0) {
 413                        edac_mc_printk(mci, KERN_ERR,
 414                                       "Unable to request irq %d\n", irq2);
 415                        res = -ENODEV;
 416                        goto err2;
 417                }
 418
 419                res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK);
 420                if (res < 0)
 421                        goto err2;
 422
 423                irqflags = IRQF_SHARED;
 424        }
 425
 426        res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
 427                               irqflags, dev_name(&pdev->dev), mci);
 428        if (res < 0) {
 429                edac_mc_printk(mci, KERN_ERR,
 430                               "Unable to request irq %d\n", irq);
 431                res = -ENODEV;
 432                goto err2;
 433        }
 434
 435        /* Infrastructure ready - enable the IRQ */
 436        if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
 437                               priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
 438                edac_mc_printk(mci, KERN_ERR,
 439                               "Error enabling SDRAM ECC IRQ\n");
 440                res = -ENODEV;
 441                goto err2;
 442        }
 443
 444        altr_sdr_mc_create_debugfs_nodes(mci);
 445
 446        devres_close_group(&pdev->dev, NULL);
 447
 448        return 0;
 449
 450err2:
 451        edac_mc_del_mc(&pdev->dev);
 452err:
 453        devres_release_group(&pdev->dev, NULL);
 454free:
 455        edac_mc_free(mci);
 456        edac_printk(KERN_ERR, EDAC_MC,
 457                    "EDAC Probe Failed; Error %d\n", res);
 458
 459        return res;
 460}
 461
 462static int altr_sdram_remove(struct platform_device *pdev)
 463{
 464        struct mem_ctl_info *mci = platform_get_drvdata(pdev);
 465
 466        edac_mc_del_mc(&pdev->dev);
 467        edac_mc_free(mci);
 468        platform_set_drvdata(pdev, NULL);
 469
 470        return 0;
 471}
 472
 473/*
 474 * If you want to suspend, need to disable EDAC by removing it
 475 * from the device tree or defconfig.
 476 */
 477#ifdef CONFIG_PM
 478static int altr_sdram_prepare(struct device *dev)
 479{
 480        pr_err("Suspend not allowed when EDAC is enabled.\n");
 481
 482        return -EPERM;
 483}
 484
 485static const struct dev_pm_ops altr_sdram_pm_ops = {
 486        .prepare = altr_sdram_prepare,
 487};
 488#endif
 489
 490static struct platform_driver altr_sdram_edac_driver = {
 491        .probe = altr_sdram_probe,
 492        .remove = altr_sdram_remove,
 493        .driver = {
 494                .name = "altr_sdram_edac",
 495#ifdef CONFIG_PM
 496                .pm = &altr_sdram_pm_ops,
 497#endif
 498                .of_match_table = altr_sdram_ctrl_of_match,
 499        },
 500};
 501
 502module_platform_driver(altr_sdram_edac_driver);
 503
 504#endif  /* CONFIG_EDAC_ALTERA_SDRAM */
 505
 506/************************* EDAC Parent Probe *************************/
 507
 508static const struct of_device_id altr_edac_device_of_match[];
 509
 510static const struct of_device_id altr_edac_of_match[] = {
 511        { .compatible = "altr,socfpga-ecc-manager" },
 512        {},
 513};
 514MODULE_DEVICE_TABLE(of, altr_edac_of_match);
 515
 516static int altr_edac_probe(struct platform_device *pdev)
 517{
 518        of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match,
 519                             NULL, &pdev->dev);
 520        return 0;
 521}
 522
 523static struct platform_driver altr_edac_driver = {
 524        .probe =  altr_edac_probe,
 525        .driver = {
 526                .name = "socfpga_ecc_manager",
 527                .of_match_table = altr_edac_of_match,
 528        },
 529};
 530module_platform_driver(altr_edac_driver);
 531
 532/************************* EDAC Device Functions *************************/
 533
 534/*
 535 * EDAC Device Functions (shared between various IPs).
 536 * The discrete memories use the EDAC Device framework. The probe
 537 * and error handling functions are very similar between memories
 538 * so they are shared. The memory allocation and freeing for EDAC
 539 * trigger testing are different for each memory.
 540 */
 541
 542static const struct edac_device_prv_data ocramecc_data;
 543static const struct edac_device_prv_data l2ecc_data;
 544static const struct edac_device_prv_data a10_ocramecc_data;
 545static const struct edac_device_prv_data a10_l2ecc_data;
 546
 547static irqreturn_t altr_edac_device_handler(int irq, void *dev_id)
 548{
 549        irqreturn_t ret_value = IRQ_NONE;
 550        struct edac_device_ctl_info *dci = dev_id;
 551        struct altr_edac_device_dev *drvdata = dci->pvt_info;
 552        const struct edac_device_prv_data *priv = drvdata->data;
 553
 554        if (irq == drvdata->sb_irq) {
 555                if (priv->ce_clear_mask)
 556                        writel(priv->ce_clear_mask, drvdata->base);
 557                edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name);
 558                ret_value = IRQ_HANDLED;
 559        } else if (irq == drvdata->db_irq) {
 560                if (priv->ue_clear_mask)
 561                        writel(priv->ue_clear_mask, drvdata->base);
 562                edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name);
 563                panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
 564                ret_value = IRQ_HANDLED;
 565        } else {
 566                WARN_ON(1);
 567        }
 568
 569        return ret_value;
 570}
 571
 572static ssize_t altr_edac_device_trig(struct file *file,
 573                                     const char __user *user_buf,
 574                                     size_t count, loff_t *ppos)
 575
 576{
 577        u32 *ptemp, i, error_mask;
 578        int result = 0;
 579        u8 trig_type;
 580        unsigned long flags;
 581        struct edac_device_ctl_info *edac_dci = file->private_data;
 582        struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
 583        const struct edac_device_prv_data *priv = drvdata->data;
 584        void *generic_ptr = edac_dci->dev;
 585
 586        if (!user_buf || get_user(trig_type, user_buf))
 587                return -EFAULT;
 588
 589        if (!priv->alloc_mem)
 590                return -ENOMEM;
 591
 592        /*
 593         * Note that generic_ptr is initialized to the device * but in
 594         * some alloc_functions, this is overridden and returns data.
 595         */
 596        ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr);
 597        if (!ptemp) {
 598                edac_printk(KERN_ERR, EDAC_DEVICE,
 599                            "Inject: Buffer Allocation error\n");
 600                return -ENOMEM;
 601        }
 602
 603        if (trig_type == ALTR_UE_TRIGGER_CHAR)
 604                error_mask = priv->ue_set_mask;
 605        else
 606                error_mask = priv->ce_set_mask;
 607
 608        edac_printk(KERN_ALERT, EDAC_DEVICE,
 609                    "Trigger Error Mask (0x%X)\n", error_mask);
 610
 611        local_irq_save(flags);
 612        /* write ECC corrupted data out. */
 613        for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) {
 614                /* Read data so we're in the correct state */
 615                rmb();
 616                if (READ_ONCE(ptemp[i]))
 617                        result = -1;
 618                /* Toggle Error bit (it is latched), leave ECC enabled */
 619                writel(error_mask, (drvdata->base + priv->set_err_ofst));
 620                writel(priv->ecc_enable_mask, (drvdata->base +
 621                                               priv->set_err_ofst));
 622                ptemp[i] = i;
 623        }
 624        /* Ensure it has been written out */
 625        wmb();
 626        local_irq_restore(flags);
 627
 628        if (result)
 629                edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n");
 630
 631        /* Read out written data. ECC error caused here */
 632        for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++)
 633                if (READ_ONCE(ptemp[i]) != i)
 634                        edac_printk(KERN_ERR, EDAC_DEVICE,
 635                                    "Read doesn't match written data\n");
 636
 637        if (priv->free_mem)
 638                priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr);
 639
 640        return count;
 641}
 642
 643static const struct file_operations altr_edac_device_inject_fops = {
 644        .open = simple_open,
 645        .write = altr_edac_device_trig,
 646        .llseek = generic_file_llseek,
 647};
 648
 649static ssize_t altr_edac_a10_device_trig(struct file *file,
 650                                         const char __user *user_buf,
 651                                         size_t count, loff_t *ppos);
 652
 653static const struct file_operations altr_edac_a10_device_inject_fops = {
 654        .open = simple_open,
 655        .write = altr_edac_a10_device_trig,
 656        .llseek = generic_file_llseek,
 657};
 658
 659static ssize_t altr_edac_a10_device_trig2(struct file *file,
 660                                          const char __user *user_buf,
 661                                          size_t count, loff_t *ppos);
 662
 663static const struct file_operations altr_edac_a10_device_inject2_fops = {
 664        .open = simple_open,
 665        .write = altr_edac_a10_device_trig2,
 666        .llseek = generic_file_llseek,
 667};
 668
 669static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci,
 670                                      const struct edac_device_prv_data *priv)
 671{
 672        struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
 673
 674        if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
 675                return;
 676
 677        drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name);
 678        if (!drvdata->debugfs_dir)
 679                return;
 680
 681        if (!edac_debugfs_create_file("altr_trigger", S_IWUSR,
 682                                      drvdata->debugfs_dir, edac_dci,
 683                                      priv->inject_fops))
 684                debugfs_remove_recursive(drvdata->debugfs_dir);
 685}
 686
 687static const struct of_device_id altr_edac_device_of_match[] = {
 688#ifdef CONFIG_EDAC_ALTERA_L2C
 689        { .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data },
 690#endif
 691#ifdef CONFIG_EDAC_ALTERA_OCRAM
 692        { .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data },
 693#endif
 694        {},
 695};
 696MODULE_DEVICE_TABLE(of, altr_edac_device_of_match);
 697
 698/*
 699 * altr_edac_device_probe()
 700 *      This is a generic EDAC device driver that will support
 701 *      various Altera memory devices such as the L2 cache ECC and
 702 *      OCRAM ECC as well as the memories for other peripherals.
 703 *      Module specific initialization is done by passing the
 704 *      function index in the device tree.
 705 */
 706static int altr_edac_device_probe(struct platform_device *pdev)
 707{
 708        struct edac_device_ctl_info *dci;
 709        struct altr_edac_device_dev *drvdata;
 710        struct resource *r;
 711        int res = 0;
 712        struct device_node *np = pdev->dev.of_node;
 713        char *ecc_name = (char *)np->name;
 714        static int dev_instance;
 715
 716        if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
 717                edac_printk(KERN_ERR, EDAC_DEVICE,
 718                            "Unable to open devm\n");
 719                return -ENOMEM;
 720        }
 721
 722        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 723        if (!r) {
 724                edac_printk(KERN_ERR, EDAC_DEVICE,
 725                            "Unable to get mem resource\n");
 726                res = -ENODEV;
 727                goto fail;
 728        }
 729
 730        if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
 731                                     dev_name(&pdev->dev))) {
 732                edac_printk(KERN_ERR, EDAC_DEVICE,
 733                            "%s:Error requesting mem region\n", ecc_name);
 734                res = -EBUSY;
 735                goto fail;
 736        }
 737
 738        dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name,
 739                                         1, ecc_name, 1, 0, NULL, 0,
 740                                         dev_instance++);
 741
 742        if (!dci) {
 743                edac_printk(KERN_ERR, EDAC_DEVICE,
 744                            "%s: Unable to allocate EDAC device\n", ecc_name);
 745                res = -ENOMEM;
 746                goto fail;
 747        }
 748
 749        drvdata = dci->pvt_info;
 750        dci->dev = &pdev->dev;
 751        platform_set_drvdata(pdev, dci);
 752        drvdata->edac_dev_name = ecc_name;
 753
 754        drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
 755        if (!drvdata->base) {
 756                res = -ENOMEM;
 757                goto fail1;
 758        }
 759
 760        /* Get driver specific data for this EDAC device */
 761        drvdata->data = of_match_node(altr_edac_device_of_match, np)->data;
 762
 763        /* Check specific dependencies for the module */
 764        if (drvdata->data->setup) {
 765                res = drvdata->data->setup(drvdata);
 766                if (res)
 767                        goto fail1;
 768        }
 769
 770        drvdata->sb_irq = platform_get_irq(pdev, 0);
 771        res = devm_request_irq(&pdev->dev, drvdata->sb_irq,
 772                               altr_edac_device_handler,
 773                               0, dev_name(&pdev->dev), dci);
 774        if (res)
 775                goto fail1;
 776
 777        drvdata->db_irq = platform_get_irq(pdev, 1);
 778        res = devm_request_irq(&pdev->dev, drvdata->db_irq,
 779                               altr_edac_device_handler,
 780                               0, dev_name(&pdev->dev), dci);
 781        if (res)
 782                goto fail1;
 783
 784        dci->mod_name = "Altera ECC Manager";
 785        dci->dev_name = drvdata->edac_dev_name;
 786
 787        res = edac_device_add_device(dci);
 788        if (res)
 789                goto fail1;
 790
 791        altr_create_edacdev_dbgfs(dci, drvdata->data);
 792
 793        devres_close_group(&pdev->dev, NULL);
 794
 795        return 0;
 796
 797fail1:
 798        edac_device_free_ctl_info(dci);
 799fail:
 800        devres_release_group(&pdev->dev, NULL);
 801        edac_printk(KERN_ERR, EDAC_DEVICE,
 802                    "%s:Error setting up EDAC device: %d\n", ecc_name, res);
 803
 804        return res;
 805}
 806
 807static int altr_edac_device_remove(struct platform_device *pdev)
 808{
 809        struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);
 810        struct altr_edac_device_dev *drvdata = dci->pvt_info;
 811
 812        debugfs_remove_recursive(drvdata->debugfs_dir);
 813        edac_device_del_device(&pdev->dev);
 814        edac_device_free_ctl_info(dci);
 815
 816        return 0;
 817}
 818
 819static struct platform_driver altr_edac_device_driver = {
 820        .probe =  altr_edac_device_probe,
 821        .remove = altr_edac_device_remove,
 822        .driver = {
 823                .name = "altr_edac_device",
 824                .of_match_table = altr_edac_device_of_match,
 825        },
 826};
 827module_platform_driver(altr_edac_device_driver);
 828
 829/******************* Arria10 Device ECC Shared Functions *****************/
 830
 831/*
 832 *  Test for memory's ECC dependencies upon entry because platform specific
 833 *  startup should have initialized the memory and enabled the ECC.
 834 *  Can't turn on ECC here because accessing un-initialized memory will
 835 *  cause CE/UE errors possibly causing an ABORT.
 836 */
 837static int __maybe_unused
 838altr_check_ecc_deps(struct altr_edac_device_dev *device)
 839{
 840        void __iomem  *base = device->base;
 841        const struct edac_device_prv_data *prv = device->data;
 842
 843        if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask)
 844                return 0;
 845
 846        edac_printk(KERN_ERR, EDAC_DEVICE,
 847                    "%s: No ECC present or ECC disabled.\n",
 848                    device->edac_dev_name);
 849        return -ENODEV;
 850}
 851
 852static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id)
 853{
 854        struct altr_edac_device_dev *dci = dev_id;
 855        void __iomem  *base = dci->base;
 856
 857        if (irq == dci->sb_irq) {
 858                writel(ALTR_A10_ECC_SERRPENA,
 859                       base + ALTR_A10_ECC_INTSTAT_OFST);
 860                edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
 861
 862                return IRQ_HANDLED;
 863        } else if (irq == dci->db_irq) {
 864                writel(ALTR_A10_ECC_DERRPENA,
 865                       base + ALTR_A10_ECC_INTSTAT_OFST);
 866                edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
 867                if (dci->data->panic)
 868                        panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
 869
 870                return IRQ_HANDLED;
 871        }
 872
 873        WARN_ON(1);
 874
 875        return IRQ_NONE;
 876}
 877
 878/******************* Arria10 Memory Buffer Functions *********************/
 879
 880static inline int a10_get_irq_mask(struct device_node *np)
 881{
 882        int irq;
 883        const u32 *handle = of_get_property(np, "interrupts", NULL);
 884
 885        if (!handle)
 886                return -ENODEV;
 887        irq = be32_to_cpup(handle);
 888        return irq;
 889}
 890
 891static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr)
 892{
 893        u32 value = readl(ioaddr);
 894
 895        value |= bit_mask;
 896        writel(value, ioaddr);
 897}
 898
 899static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr)
 900{
 901        u32 value = readl(ioaddr);
 902
 903        value &= ~bit_mask;
 904        writel(value, ioaddr);
 905}
 906
 907static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr)
 908{
 909        u32 value = readl(ioaddr);
 910
 911        return (value & bit_mask) ? 1 : 0;
 912}
 913
 914/*
 915 * This function uses the memory initialization block in the Arria10 ECC
 916 * controller to initialize/clear the entire memory data and ECC data.
 917 */
 918static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port)
 919{
 920        int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US;
 921        u32 init_mask, stat_mask, clear_mask;
 922        int ret = 0;
 923
 924        if (port) {
 925                init_mask = ALTR_A10_ECC_INITB;
 926                stat_mask = ALTR_A10_ECC_INITCOMPLETEB;
 927                clear_mask = ALTR_A10_ECC_ERRPENB_MASK;
 928        } else {
 929                init_mask = ALTR_A10_ECC_INITA;
 930                stat_mask = ALTR_A10_ECC_INITCOMPLETEA;
 931                clear_mask = ALTR_A10_ECC_ERRPENA_MASK;
 932        }
 933
 934        ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST));
 935        while (limit--) {
 936                if (ecc_test_bits(stat_mask,
 937                                  (ioaddr + ALTR_A10_ECC_INITSTAT_OFST)))
 938                        break;
 939                udelay(1);
 940        }
 941        if (limit < 0)
 942                ret = -EBUSY;
 943
 944        /* Clear any pending ECC interrupts */
 945        writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST));
 946
 947        return ret;
 948}
 949
 950static __init int __maybe_unused
 951altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask,
 952                        u32 ecc_ctrl_en_mask, bool dual_port)
 953{
 954        int ret = 0;
 955        void __iomem *ecc_block_base;
 956        struct regmap *ecc_mgr_map;
 957        char *ecc_name;
 958        struct device_node *np_eccmgr;
 959
 960        ecc_name = (char *)np->name;
 961
 962        /* Get the ECC Manager - parent of the device EDACs */
 963        np_eccmgr = of_get_parent(np);
 964
 965        ecc_mgr_map =
 966                altr_sysmgr_regmap_lookup_by_phandle(np_eccmgr,
 967                                                     "altr,sysmgr-syscon");
 968
 969        of_node_put(np_eccmgr);
 970        if (IS_ERR(ecc_mgr_map)) {
 971                edac_printk(KERN_ERR, EDAC_DEVICE,
 972                            "Unable to get syscon altr,sysmgr-syscon\n");
 973                return -ENODEV;
 974        }
 975
 976        /* Map the ECC Block */
 977        ecc_block_base = of_iomap(np, 0);
 978        if (!ecc_block_base) {
 979                edac_printk(KERN_ERR, EDAC_DEVICE,
 980                            "Unable to map %s ECC block\n", ecc_name);
 981                return -ENODEV;
 982        }
 983
 984        /* Disable ECC */
 985        regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask);
 986        writel(ALTR_A10_ECC_SERRINTEN,
 987               (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST));
 988        ecc_clear_bits(ecc_ctrl_en_mask,
 989                       (ecc_block_base + ALTR_A10_ECC_CTRL_OFST));
 990        /* Ensure all writes complete */
 991        wmb();
 992        /* Use HW initialization block to initialize memory for ECC */
 993        ret = altr_init_memory_port(ecc_block_base, 0);
 994        if (ret) {
 995                edac_printk(KERN_ERR, EDAC_DEVICE,
 996                            "ECC: cannot init %s PORTA memory\n", ecc_name);
 997                goto out;
 998        }
 999
1000        if (dual_port) {
1001                ret = altr_init_memory_port(ecc_block_base, 1);
1002                if (ret) {
1003                        edac_printk(KERN_ERR, EDAC_DEVICE,
1004                                    "ECC: cannot init %s PORTB memory\n",
1005                                    ecc_name);
1006                        goto out;
1007                }
1008        }
1009
1010        /* Interrupt mode set to every SBERR */
1011        regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST,
1012                     ALTR_A10_ECC_INTMODE);
1013        /* Enable ECC */
1014        ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base +
1015                                        ALTR_A10_ECC_CTRL_OFST));
1016        writel(ALTR_A10_ECC_SERRINTEN,
1017               (ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST));
1018        regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask);
1019        /* Ensure all writes complete */
1020        wmb();
1021out:
1022        iounmap(ecc_block_base);
1023        return ret;
1024}
1025
1026static int validate_parent_available(struct device_node *np);
1027static const struct of_device_id altr_edac_a10_device_of_match[];
1028static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat)
1029{
1030        int irq;
1031        struct device_node *child, *np;
1032
1033        np = of_find_compatible_node(NULL, NULL,
1034                                     "altr,socfpga-a10-ecc-manager");
1035        if (!np) {
1036                edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n");
1037                return -ENODEV;
1038        }
1039
1040        for_each_child_of_node(np, child) {
1041                const struct of_device_id *pdev_id;
1042                const struct edac_device_prv_data *prv;
1043
1044                if (!of_device_is_available(child))
1045                        continue;
1046                if (!of_device_is_compatible(child, compat))
1047                        continue;
1048
1049                if (validate_parent_available(child))
1050                        continue;
1051
1052                irq = a10_get_irq_mask(child);
1053                if (irq < 0)
1054                        continue;
1055
1056                /* Get matching node and check for valid result */
1057                pdev_id = of_match_node(altr_edac_a10_device_of_match, child);
1058                if (IS_ERR_OR_NULL(pdev_id))
1059                        continue;
1060
1061                /* Validate private data pointer before dereferencing */
1062                prv = pdev_id->data;
1063                if (!prv)
1064                        continue;
1065
1066                altr_init_a10_ecc_block(child, BIT(irq),
1067                                        prv->ecc_enable_mask, 0);
1068        }
1069
1070        of_node_put(np);
1071        return 0;
1072}
1073
1074/*********************** SDRAM EDAC Device Functions *********************/
1075
1076#ifdef CONFIG_EDAC_ALTERA_SDRAM
1077
1078static const struct edac_device_prv_data s10_sdramecc_data = {
1079        .setup = altr_check_ecc_deps,
1080        .ce_clear_mask = ALTR_S10_ECC_SERRPENA,
1081        .ue_clear_mask = ALTR_S10_ECC_DERRPENA,
1082        .ecc_enable_mask = ALTR_S10_ECC_EN,
1083        .ecc_en_ofst = ALTR_S10_ECC_CTRL_SDRAM_OFST,
1084        .ce_set_mask = ALTR_S10_ECC_TSERRA,
1085        .ue_set_mask = ALTR_S10_ECC_TDERRA,
1086        .set_err_ofst = ALTR_S10_ECC_INTTEST_OFST,
1087        .ecc_irq_handler = altr_edac_a10_ecc_irq,
1088        .inject_fops = &altr_edac_a10_device_inject_fops,
1089};
1090#endif /* CONFIG_EDAC_ALTERA_SDRAM */
1091
1092/*********************** OCRAM EDAC Device Functions *********************/
1093
1094#ifdef CONFIG_EDAC_ALTERA_OCRAM
1095
1096static void *ocram_alloc_mem(size_t size, void **other)
1097{
1098        struct device_node *np;
1099        struct gen_pool *gp;
1100        void *sram_addr;
1101
1102        np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc");
1103        if (!np)
1104                return NULL;
1105
1106        gp = of_gen_pool_get(np, "iram", 0);
1107        of_node_put(np);
1108        if (!gp)
1109                return NULL;
1110
1111        sram_addr = (void *)gen_pool_alloc(gp, size);
1112        if (!sram_addr)
1113                return NULL;
1114
1115        memset(sram_addr, 0, size);
1116        /* Ensure data is written out */
1117        wmb();
1118
1119        /* Remember this handle for freeing  later */
1120        *other = gp;
1121
1122        return sram_addr;
1123}
1124
1125static void ocram_free_mem(void *p, size_t size, void *other)
1126{
1127        gen_pool_free((struct gen_pool *)other, (unsigned long)p, size);
1128}
1129
1130static const struct edac_device_prv_data ocramecc_data = {
1131        .setup = altr_check_ecc_deps,
1132        .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR),
1133        .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR),
1134        .alloc_mem = ocram_alloc_mem,
1135        .free_mem = ocram_free_mem,
1136        .ecc_enable_mask = ALTR_OCR_ECC_EN,
1137        .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET,
1138        .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS),
1139        .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD),
1140        .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET,
1141        .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE,
1142        .inject_fops = &altr_edac_device_inject_fops,
1143};
1144
1145static int __maybe_unused
1146altr_check_ocram_deps_init(struct altr_edac_device_dev *device)
1147{
1148        void __iomem  *base = device->base;
1149        int ret;
1150
1151        ret = altr_check_ecc_deps(device);
1152        if (ret)
1153                return ret;
1154
1155        /* Verify OCRAM has been initialized */
1156        if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA,
1157                           (base + ALTR_A10_ECC_INITSTAT_OFST)))
1158                return -ENODEV;
1159
1160        /* Enable IRQ on Single Bit Error */
1161        writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST));
1162        /* Ensure all writes complete */
1163        wmb();
1164
1165        return 0;
1166}
1167
1168static const struct edac_device_prv_data a10_ocramecc_data = {
1169        .setup = altr_check_ocram_deps_init,
1170        .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1171        .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1172        .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM,
1173        .ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL,
1174        .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1175        .ce_set_mask = ALTR_A10_ECC_TSERRA,
1176        .ue_set_mask = ALTR_A10_ECC_TDERRA,
1177        .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1178        .ecc_irq_handler = altr_edac_a10_ecc_irq,
1179        .inject_fops = &altr_edac_a10_device_inject2_fops,
1180        /*
1181         * OCRAM panic on uncorrectable error because sleep/resume
1182         * functions and FPGA contents are stored in OCRAM. Prefer
1183         * a kernel panic over executing/loading corrupted data.
1184         */
1185        .panic = true,
1186};
1187
1188#endif  /* CONFIG_EDAC_ALTERA_OCRAM */
1189
1190/********************* L2 Cache EDAC Device Functions ********************/
1191
1192#ifdef CONFIG_EDAC_ALTERA_L2C
1193
1194static void *l2_alloc_mem(size_t size, void **other)
1195{
1196        struct device *dev = *other;
1197        void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL);
1198
1199        if (!ptemp)
1200                return NULL;
1201
1202        /* Make sure everything is written out */
1203        wmb();
1204
1205        /*
1206         * Clean all cache levels up to LoC (includes L2)
1207         * This ensures the corrupted data is written into
1208         * L2 cache for readback test (which causes ECC error).
1209         */
1210        flush_cache_all();
1211
1212        return ptemp;
1213}
1214
1215static void l2_free_mem(void *p, size_t size, void *other)
1216{
1217        struct device *dev = other;
1218
1219        if (dev && p)
1220                devm_kfree(dev, p);
1221}
1222
1223/*
1224 * altr_l2_check_deps()
1225 *      Test for L2 cache ECC dependencies upon entry because
1226 *      platform specific startup should have initialized the L2
1227 *      memory and enabled the ECC.
1228 *      Bail if ECC is not enabled.
1229 *      Note that L2 Cache Enable is forced at build time.
1230 */
1231static int altr_l2_check_deps(struct altr_edac_device_dev *device)
1232{
1233        void __iomem *base = device->base;
1234        const struct edac_device_prv_data *prv = device->data;
1235
1236        if ((readl(base) & prv->ecc_enable_mask) ==
1237             prv->ecc_enable_mask)
1238                return 0;
1239
1240        edac_printk(KERN_ERR, EDAC_DEVICE,
1241                    "L2: No ECC present, or ECC disabled\n");
1242        return -ENODEV;
1243}
1244
1245static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id)
1246{
1247        struct altr_edac_device_dev *dci = dev_id;
1248
1249        if (irq == dci->sb_irq) {
1250                regmap_write(dci->edac->ecc_mgr_map,
1251                             A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1252                             A10_SYSGMR_MPU_CLEAR_L2_ECC_SB);
1253                edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
1254
1255                return IRQ_HANDLED;
1256        } else if (irq == dci->db_irq) {
1257                regmap_write(dci->edac->ecc_mgr_map,
1258                             A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1259                             A10_SYSGMR_MPU_CLEAR_L2_ECC_MB);
1260                edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
1261                panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
1262
1263                return IRQ_HANDLED;
1264        }
1265
1266        WARN_ON(1);
1267
1268        return IRQ_NONE;
1269}
1270
1271static const struct edac_device_prv_data l2ecc_data = {
1272        .setup = altr_l2_check_deps,
1273        .ce_clear_mask = 0,
1274        .ue_clear_mask = 0,
1275        .alloc_mem = l2_alloc_mem,
1276        .free_mem = l2_free_mem,
1277        .ecc_enable_mask = ALTR_L2_ECC_EN,
1278        .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS),
1279        .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD),
1280        .set_err_ofst = ALTR_L2_ECC_REG_OFFSET,
1281        .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1282        .inject_fops = &altr_edac_device_inject_fops,
1283};
1284
1285static const struct edac_device_prv_data a10_l2ecc_data = {
1286        .setup = altr_l2_check_deps,
1287        .ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR,
1288        .ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR,
1289        .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2,
1290        .alloc_mem = l2_alloc_mem,
1291        .free_mem = l2_free_mem,
1292        .ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL,
1293        .ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK,
1294        .ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK,
1295        .set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST,
1296        .ecc_irq_handler = altr_edac_a10_l2_irq,
1297        .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1298        .inject_fops = &altr_edac_device_inject_fops,
1299};
1300
1301#endif  /* CONFIG_EDAC_ALTERA_L2C */
1302
1303/********************* Ethernet Device Functions ********************/
1304
1305#ifdef CONFIG_EDAC_ALTERA_ETHERNET
1306
1307static int __init socfpga_init_ethernet_ecc(struct altr_edac_device_dev *dev)
1308{
1309        int ret;
1310
1311        ret = altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc");
1312        if (ret)
1313                return ret;
1314
1315        return altr_check_ecc_deps(dev);
1316}
1317
1318static const struct edac_device_prv_data a10_enetecc_data = {
1319        .setup = socfpga_init_ethernet_ecc,
1320        .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1321        .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1322        .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1323        .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1324        .ce_set_mask = ALTR_A10_ECC_TSERRA,
1325        .ue_set_mask = ALTR_A10_ECC_TDERRA,
1326        .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1327        .ecc_irq_handler = altr_edac_a10_ecc_irq,
1328        .inject_fops = &altr_edac_a10_device_inject2_fops,
1329};
1330
1331#endif  /* CONFIG_EDAC_ALTERA_ETHERNET */
1332
1333/********************** NAND Device Functions **********************/
1334
1335#ifdef CONFIG_EDAC_ALTERA_NAND
1336
1337static int __init socfpga_init_nand_ecc(struct altr_edac_device_dev *device)
1338{
1339        int ret;
1340
1341        ret = altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc");
1342        if (ret)
1343                return ret;
1344
1345        return altr_check_ecc_deps(device);
1346}
1347
1348static const struct edac_device_prv_data a10_nandecc_data = {
1349        .setup = socfpga_init_nand_ecc,
1350        .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1351        .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1352        .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1353        .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1354        .ce_set_mask = ALTR_A10_ECC_TSERRA,
1355        .ue_set_mask = ALTR_A10_ECC_TDERRA,
1356        .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1357        .ecc_irq_handler = altr_edac_a10_ecc_irq,
1358        .inject_fops = &altr_edac_a10_device_inject_fops,
1359};
1360
1361#endif  /* CONFIG_EDAC_ALTERA_NAND */
1362
1363/********************** DMA Device Functions **********************/
1364
1365#ifdef CONFIG_EDAC_ALTERA_DMA
1366
1367static int __init socfpga_init_dma_ecc(struct altr_edac_device_dev *device)
1368{
1369        int ret;
1370
1371        ret = altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc");
1372        if (ret)
1373                return ret;
1374
1375        return altr_check_ecc_deps(device);
1376}
1377
1378static const struct edac_device_prv_data a10_dmaecc_data = {
1379        .setup = socfpga_init_dma_ecc,
1380        .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1381        .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1382        .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1383        .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1384        .ce_set_mask = ALTR_A10_ECC_TSERRA,
1385        .ue_set_mask = ALTR_A10_ECC_TDERRA,
1386        .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1387        .ecc_irq_handler = altr_edac_a10_ecc_irq,
1388        .inject_fops = &altr_edac_a10_device_inject_fops,
1389};
1390
1391#endif  /* CONFIG_EDAC_ALTERA_DMA */
1392
1393/********************** USB Device Functions **********************/
1394
1395#ifdef CONFIG_EDAC_ALTERA_USB
1396
1397static int __init socfpga_init_usb_ecc(struct altr_edac_device_dev *device)
1398{
1399        int ret;
1400
1401        ret = altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc");
1402        if (ret)
1403                return ret;
1404
1405        return altr_check_ecc_deps(device);
1406}
1407
1408static const struct edac_device_prv_data a10_usbecc_data = {
1409        .setup = socfpga_init_usb_ecc,
1410        .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1411        .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1412        .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1413        .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1414        .ce_set_mask = ALTR_A10_ECC_TSERRA,
1415        .ue_set_mask = ALTR_A10_ECC_TDERRA,
1416        .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1417        .ecc_irq_handler = altr_edac_a10_ecc_irq,
1418        .inject_fops = &altr_edac_a10_device_inject2_fops,
1419};
1420
1421#endif  /* CONFIG_EDAC_ALTERA_USB */
1422
1423/********************** QSPI Device Functions **********************/
1424
1425#ifdef CONFIG_EDAC_ALTERA_QSPI
1426
1427static int __init socfpga_init_qspi_ecc(struct altr_edac_device_dev *device)
1428{
1429        int ret;
1430
1431        ret = altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc");
1432        if (ret)
1433                return ret;
1434
1435        return altr_check_ecc_deps(device);
1436}
1437
1438static const struct edac_device_prv_data a10_qspiecc_data = {
1439        .setup = socfpga_init_qspi_ecc,
1440        .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1441        .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1442        .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1443        .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1444        .ce_set_mask = ALTR_A10_ECC_TSERRA,
1445        .ue_set_mask = ALTR_A10_ECC_TDERRA,
1446        .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1447        .ecc_irq_handler = altr_edac_a10_ecc_irq,
1448        .inject_fops = &altr_edac_a10_device_inject_fops,
1449};
1450
1451#endif  /* CONFIG_EDAC_ALTERA_QSPI */
1452
1453/********************* SDMMC Device Functions **********************/
1454
1455#ifdef CONFIG_EDAC_ALTERA_SDMMC
1456
1457static const struct edac_device_prv_data a10_sdmmceccb_data;
1458static int altr_portb_setup(struct altr_edac_device_dev *device)
1459{
1460        struct edac_device_ctl_info *dci;
1461        struct altr_edac_device_dev *altdev;
1462        char *ecc_name = "sdmmcb-ecc";
1463        int edac_idx, rc;
1464        struct device_node *np;
1465        const struct edac_device_prv_data *prv = &a10_sdmmceccb_data;
1466
1467        rc = altr_check_ecc_deps(device);
1468        if (rc)
1469                return rc;
1470
1471        np = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1472        if (!np) {
1473                edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n");
1474                return -ENODEV;
1475        }
1476
1477        /* Create the PortB EDAC device */
1478        edac_idx = edac_device_alloc_index();
1479        dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1,
1480                                         ecc_name, 1, 0, NULL, 0, edac_idx);
1481        if (!dci) {
1482                edac_printk(KERN_ERR, EDAC_DEVICE,
1483                            "%s: Unable to allocate PortB EDAC device\n",
1484                            ecc_name);
1485                return -ENOMEM;
1486        }
1487
1488        /* Initialize the PortB EDAC device structure from PortA structure */
1489        altdev = dci->pvt_info;
1490        *altdev = *device;
1491
1492        if (!devres_open_group(&altdev->ddev, altr_portb_setup, GFP_KERNEL))
1493                return -ENOMEM;
1494
1495        /* Update PortB specific values */
1496        altdev->edac_dev_name = ecc_name;
1497        altdev->edac_idx = edac_idx;
1498        altdev->edac_dev = dci;
1499        altdev->data = prv;
1500        dci->dev = &altdev->ddev;
1501        dci->ctl_name = "Altera ECC Manager";
1502        dci->mod_name = ecc_name;
1503        dci->dev_name = ecc_name;
1504
1505        /*
1506         * Update the PortB IRQs - A10 has 4, S10 has 2, Index accordingly
1507         *
1508         * FIXME: Instead of ifdefs with different architectures the driver
1509         *        should properly use compatibles.
1510         */
1511#ifdef CONFIG_64BIT
1512        altdev->sb_irq = irq_of_parse_and_map(np, 1);
1513#else
1514        altdev->sb_irq = irq_of_parse_and_map(np, 2);
1515#endif
1516        if (!altdev->sb_irq) {
1517                edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB SBIRQ alloc\n");
1518                rc = -ENODEV;
1519                goto err_release_group_1;
1520        }
1521        rc = devm_request_irq(&altdev->ddev, altdev->sb_irq,
1522                              prv->ecc_irq_handler,
1523                              IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1524                              ecc_name, altdev);
1525        if (rc) {
1526                edac_printk(KERN_ERR, EDAC_DEVICE, "PortB SBERR IRQ error\n");
1527                goto err_release_group_1;
1528        }
1529
1530#ifdef CONFIG_64BIT
1531        /* Use IRQ to determine SError origin instead of assigning IRQ */
1532        rc = of_property_read_u32_index(np, "interrupts", 1, &altdev->db_irq);
1533        if (rc) {
1534                edac_printk(KERN_ERR, EDAC_DEVICE,
1535                            "Error PortB DBIRQ alloc\n");
1536                goto err_release_group_1;
1537        }
1538#else
1539        altdev->db_irq = irq_of_parse_and_map(np, 3);
1540        if (!altdev->db_irq) {
1541                edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n");
1542                rc = -ENODEV;
1543                goto err_release_group_1;
1544        }
1545        rc = devm_request_irq(&altdev->ddev, altdev->db_irq,
1546                              prv->ecc_irq_handler,
1547                              IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1548                              ecc_name, altdev);
1549        if (rc) {
1550                edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n");
1551                goto err_release_group_1;
1552        }
1553#endif
1554
1555        rc = edac_device_add_device(dci);
1556        if (rc) {
1557                edac_printk(KERN_ERR, EDAC_DEVICE,
1558                            "edac_device_add_device portB failed\n");
1559                rc = -ENOMEM;
1560                goto err_release_group_1;
1561        }
1562        altr_create_edacdev_dbgfs(dci, prv);
1563
1564        list_add(&altdev->next, &altdev->edac->a10_ecc_devices);
1565
1566        devres_remove_group(&altdev->ddev, altr_portb_setup);
1567
1568        return 0;
1569
1570err_release_group_1:
1571        edac_device_free_ctl_info(dci);
1572        devres_release_group(&altdev->ddev, altr_portb_setup);
1573        edac_printk(KERN_ERR, EDAC_DEVICE,
1574                    "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
1575        return rc;
1576}
1577
1578static int __init socfpga_init_sdmmc_ecc(struct altr_edac_device_dev *device)
1579{
1580        int rc = -ENODEV;
1581        struct device_node *child;
1582
1583        child = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1584        if (!child)
1585                return -ENODEV;
1586
1587        if (!of_device_is_available(child))
1588                goto exit;
1589
1590        if (validate_parent_available(child))
1591                goto exit;
1592
1593        /* Init portB */
1594        rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK,
1595                                     a10_sdmmceccb_data.ecc_enable_mask, 1);
1596        if (rc)
1597                goto exit;
1598
1599        /* Setup portB */
1600        return altr_portb_setup(device);
1601
1602exit:
1603        of_node_put(child);
1604        return rc;
1605}
1606
1607static irqreturn_t altr_edac_a10_ecc_irq_portb(int irq, void *dev_id)
1608{
1609        struct altr_edac_device_dev *ad = dev_id;
1610        void __iomem  *base = ad->base;
1611        const struct edac_device_prv_data *priv = ad->data;
1612
1613        if (irq == ad->sb_irq) {
1614                writel(priv->ce_clear_mask,
1615                       base + ALTR_A10_ECC_INTSTAT_OFST);
1616                edac_device_handle_ce(ad->edac_dev, 0, 0, ad->edac_dev_name);
1617                return IRQ_HANDLED;
1618        } else if (irq == ad->db_irq) {
1619                writel(priv->ue_clear_mask,
1620                       base + ALTR_A10_ECC_INTSTAT_OFST);
1621                edac_device_handle_ue(ad->edac_dev, 0, 0, ad->edac_dev_name);
1622                return IRQ_HANDLED;
1623        }
1624
1625        WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq);
1626
1627        return IRQ_NONE;
1628}
1629
1630static const struct edac_device_prv_data a10_sdmmcecca_data = {
1631        .setup = socfpga_init_sdmmc_ecc,
1632        .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1633        .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1634        .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1635        .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1636        .ce_set_mask = ALTR_A10_ECC_SERRPENA,
1637        .ue_set_mask = ALTR_A10_ECC_DERRPENA,
1638        .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1639        .ecc_irq_handler = altr_edac_a10_ecc_irq,
1640        .inject_fops = &altr_edac_a10_device_inject_fops,
1641};
1642
1643static const struct edac_device_prv_data a10_sdmmceccb_data = {
1644        .setup = socfpga_init_sdmmc_ecc,
1645        .ce_clear_mask = ALTR_A10_ECC_SERRPENB,
1646        .ue_clear_mask = ALTR_A10_ECC_DERRPENB,
1647        .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1648        .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1649        .ce_set_mask = ALTR_A10_ECC_TSERRB,
1650        .ue_set_mask = ALTR_A10_ECC_TDERRB,
1651        .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1652        .ecc_irq_handler = altr_edac_a10_ecc_irq_portb,
1653        .inject_fops = &altr_edac_a10_device_inject_fops,
1654};
1655
1656#endif  /* CONFIG_EDAC_ALTERA_SDMMC */
1657
1658/********************* Arria10 EDAC Device Functions *************************/
1659static const struct of_device_id altr_edac_a10_device_of_match[] = {
1660#ifdef CONFIG_EDAC_ALTERA_L2C
1661        { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data },
1662#endif
1663#ifdef CONFIG_EDAC_ALTERA_OCRAM
1664        { .compatible = "altr,socfpga-a10-ocram-ecc",
1665          .data = &a10_ocramecc_data },
1666#endif
1667#ifdef CONFIG_EDAC_ALTERA_ETHERNET
1668        { .compatible = "altr,socfpga-eth-mac-ecc",
1669          .data = &a10_enetecc_data },
1670#endif
1671#ifdef CONFIG_EDAC_ALTERA_NAND
1672        { .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data },
1673#endif
1674#ifdef CONFIG_EDAC_ALTERA_DMA
1675        { .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data },
1676#endif
1677#ifdef CONFIG_EDAC_ALTERA_USB
1678        { .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data },
1679#endif
1680#ifdef CONFIG_EDAC_ALTERA_QSPI
1681        { .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data },
1682#endif
1683#ifdef CONFIG_EDAC_ALTERA_SDMMC
1684        { .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data },
1685#endif
1686#ifdef CONFIG_EDAC_ALTERA_SDRAM
1687        { .compatible = "altr,sdram-edac-s10", .data = &s10_sdramecc_data },
1688#endif
1689        {},
1690};
1691MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match);
1692
1693/*
1694 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
1695 * because 2 IRQs are shared among the all ECC peripherals. The ECC
1696 * manager manages the IRQs and the children.
1697 * Based on xgene_edac.c peripheral code.
1698 */
1699
1700static ssize_t altr_edac_a10_device_trig(struct file *file,
1701                                         const char __user *user_buf,
1702                                         size_t count, loff_t *ppos)
1703{
1704        struct edac_device_ctl_info *edac_dci = file->private_data;
1705        struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1706        const struct edac_device_prv_data *priv = drvdata->data;
1707        void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1708        unsigned long flags;
1709        u8 trig_type;
1710
1711        if (!user_buf || get_user(trig_type, user_buf))
1712                return -EFAULT;
1713
1714        local_irq_save(flags);
1715        if (trig_type == ALTR_UE_TRIGGER_CHAR)
1716                writel(priv->ue_set_mask, set_addr);
1717        else
1718                writel(priv->ce_set_mask, set_addr);
1719
1720        /* Ensure the interrupt test bits are set */
1721        wmb();
1722        local_irq_restore(flags);
1723
1724        return count;
1725}
1726
1727/*
1728 * The Stratix10 EDAC Error Injection Functions differ from Arria10
1729 * slightly. A few Arria10 peripherals can use this injection function.
1730 * Inject the error into the memory and then readback to trigger the IRQ.
1731 */
1732static ssize_t altr_edac_a10_device_trig2(struct file *file,
1733                                          const char __user *user_buf,
1734                                          size_t count, loff_t *ppos)
1735{
1736        struct edac_device_ctl_info *edac_dci = file->private_data;
1737        struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1738        const struct edac_device_prv_data *priv = drvdata->data;
1739        void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1740        unsigned long flags;
1741        u8 trig_type;
1742
1743        if (!user_buf || get_user(trig_type, user_buf))
1744                return -EFAULT;
1745
1746        local_irq_save(flags);
1747        if (trig_type == ALTR_UE_TRIGGER_CHAR) {
1748                writel(priv->ue_set_mask, set_addr);
1749        } else {
1750                /* Setup read/write of 4 bytes */
1751                writel(ECC_WORD_WRITE, drvdata->base + ECC_BLK_DBYTECTRL_OFST);
1752                /* Setup Address to 0 */
1753                writel(0, drvdata->base + ECC_BLK_ADDRESS_OFST);
1754                /* Setup accctrl to read & ecc & data override */
1755                writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1756                /* Kick it. */
1757                writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1758                /* Setup write for single bit change */
1759                writel(readl(drvdata->base + ECC_BLK_RDATA0_OFST) ^ 0x1,
1760                       drvdata->base + ECC_BLK_WDATA0_OFST);
1761                writel(readl(drvdata->base + ECC_BLK_RDATA1_OFST),
1762                       drvdata->base + ECC_BLK_WDATA1_OFST);
1763                writel(readl(drvdata->base + ECC_BLK_RDATA2_OFST),
1764                       drvdata->base + ECC_BLK_WDATA2_OFST);
1765                writel(readl(drvdata->base + ECC_BLK_RDATA3_OFST),
1766                       drvdata->base + ECC_BLK_WDATA3_OFST);
1767
1768                /* Copy Read ECC to Write ECC */
1769                writel(readl(drvdata->base + ECC_BLK_RECC0_OFST),
1770                       drvdata->base + ECC_BLK_WECC0_OFST);
1771                writel(readl(drvdata->base + ECC_BLK_RECC1_OFST),
1772                       drvdata->base + ECC_BLK_WECC1_OFST);
1773                /* Setup accctrl to write & ecc override & data override */
1774                writel(ECC_WRITE_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1775                /* Kick it. */
1776                writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1777                /* Setup accctrl to read & ecc overwrite & data overwrite */
1778                writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1779                /* Kick it. */
1780                writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1781        }
1782
1783        /* Ensure the interrupt test bits are set */
1784        wmb();
1785        local_irq_restore(flags);
1786
1787        return count;
1788}
1789
1790static void altr_edac_a10_irq_handler(struct irq_desc *desc)
1791{
1792        int dberr, bit, sm_offset, irq_status;
1793        struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc);
1794        struct irq_chip *chip = irq_desc_get_chip(desc);
1795        int irq = irq_desc_get_irq(desc);
1796        unsigned long bits;
1797
1798        dberr = (irq == edac->db_irq) ? 1 : 0;
1799        sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST :
1800                            A10_SYSMGR_ECC_INTSTAT_SERR_OFST;
1801
1802        chained_irq_enter(chip, desc);
1803
1804        regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status);
1805
1806        bits = irq_status;
1807        for_each_set_bit(bit, &bits, 32) {
1808                irq = irq_linear_revmap(edac->domain, dberr * 32 + bit);
1809                if (irq)
1810                        generic_handle_irq(irq);
1811        }
1812
1813        chained_irq_exit(chip, desc);
1814}
1815
1816static int validate_parent_available(struct device_node *np)
1817{
1818        struct device_node *parent;
1819        int ret = 0;
1820
1821        /* SDRAM must be present for Linux (implied parent) */
1822        if (of_device_is_compatible(np, "altr,sdram-edac-s10"))
1823                return 0;
1824
1825        /* Ensure parent device is enabled if parent node exists */
1826        parent = of_parse_phandle(np, "altr,ecc-parent", 0);
1827        if (parent && !of_device_is_available(parent))
1828                ret = -ENODEV;
1829
1830        of_node_put(parent);
1831        return ret;
1832}
1833
1834static int get_s10_sdram_edac_resource(struct device_node *np,
1835                                       struct resource *res)
1836{
1837        struct device_node *parent;
1838        int ret;
1839
1840        parent = of_parse_phandle(np, "altr,sdr-syscon", 0);
1841        if (!parent)
1842                return -ENODEV;
1843
1844        ret = of_address_to_resource(parent, 0, res);
1845        of_node_put(parent);
1846
1847        return ret;
1848}
1849
1850static int altr_edac_a10_device_add(struct altr_arria10_edac *edac,
1851                                    struct device_node *np)
1852{
1853        struct edac_device_ctl_info *dci;
1854        struct altr_edac_device_dev *altdev;
1855        char *ecc_name = (char *)np->name;
1856        struct resource res;
1857        int edac_idx;
1858        int rc = 0;
1859        const struct edac_device_prv_data *prv;
1860        /* Get matching node and check for valid result */
1861        const struct of_device_id *pdev_id =
1862                of_match_node(altr_edac_a10_device_of_match, np);
1863        if (IS_ERR_OR_NULL(pdev_id))
1864                return -ENODEV;
1865
1866        /* Get driver specific data for this EDAC device */
1867        prv = pdev_id->data;
1868        if (IS_ERR_OR_NULL(prv))
1869                return -ENODEV;
1870
1871        if (validate_parent_available(np))
1872                return -ENODEV;
1873
1874        if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL))
1875                return -ENOMEM;
1876
1877        if (of_device_is_compatible(np, "altr,sdram-edac-s10"))
1878                rc = get_s10_sdram_edac_resource(np, &res);
1879        else
1880                rc = of_address_to_resource(np, 0, &res);
1881
1882        if (rc < 0) {
1883                edac_printk(KERN_ERR, EDAC_DEVICE,
1884                            "%s: no resource address\n", ecc_name);
1885                goto err_release_group;
1886        }
1887
1888        edac_idx = edac_device_alloc_index();
1889        dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name,
1890                                         1, ecc_name, 1, 0, NULL, 0,
1891                                         edac_idx);
1892
1893        if (!dci) {
1894                edac_printk(KERN_ERR, EDAC_DEVICE,
1895                            "%s: Unable to allocate EDAC device\n", ecc_name);
1896                rc = -ENOMEM;
1897                goto err_release_group;
1898        }
1899
1900        altdev = dci->pvt_info;
1901        dci->dev = edac->dev;
1902        altdev->edac_dev_name = ecc_name;
1903        altdev->edac_idx = edac_idx;
1904        altdev->edac = edac;
1905        altdev->edac_dev = dci;
1906        altdev->data = prv;
1907        altdev->ddev = *edac->dev;
1908        dci->dev = &altdev->ddev;
1909        dci->ctl_name = "Altera ECC Manager";
1910        dci->mod_name = ecc_name;
1911        dci->dev_name = ecc_name;
1912
1913        altdev->base = devm_ioremap_resource(edac->dev, &res);
1914        if (IS_ERR(altdev->base)) {
1915                rc = PTR_ERR(altdev->base);
1916                goto err_release_group1;
1917        }
1918
1919        /* Check specific dependencies for the module */
1920        if (altdev->data->setup) {
1921                rc = altdev->data->setup(altdev);
1922                if (rc)
1923                        goto err_release_group1;
1924        }
1925
1926        altdev->sb_irq = irq_of_parse_and_map(np, 0);
1927        if (!altdev->sb_irq) {
1928                edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating SBIRQ\n");
1929                rc = -ENODEV;
1930                goto err_release_group1;
1931        }
1932        rc = devm_request_irq(edac->dev, altdev->sb_irq, prv->ecc_irq_handler,
1933                              IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1934                              ecc_name, altdev);
1935        if (rc) {
1936                edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n");
1937                goto err_release_group1;
1938        }
1939
1940#ifdef CONFIG_64BIT
1941        /* Use IRQ to determine SError origin instead of assigning IRQ */
1942        rc = of_property_read_u32_index(np, "interrupts", 0, &altdev->db_irq);
1943        if (rc) {
1944                edac_printk(KERN_ERR, EDAC_DEVICE,
1945                            "Unable to parse DB IRQ index\n");
1946                goto err_release_group1;
1947        }
1948#else
1949        altdev->db_irq = irq_of_parse_and_map(np, 1);
1950        if (!altdev->db_irq) {
1951                edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n");
1952                rc = -ENODEV;
1953                goto err_release_group1;
1954        }
1955        rc = devm_request_irq(edac->dev, altdev->db_irq, prv->ecc_irq_handler,
1956                              IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1957                              ecc_name, altdev);
1958        if (rc) {
1959                edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n");
1960                goto err_release_group1;
1961        }
1962#endif
1963
1964        rc = edac_device_add_device(dci);
1965        if (rc) {
1966                dev_err(edac->dev, "edac_device_add_device failed\n");
1967                rc = -ENOMEM;
1968                goto err_release_group1;
1969        }
1970
1971        altr_create_edacdev_dbgfs(dci, prv);
1972
1973        list_add(&altdev->next, &edac->a10_ecc_devices);
1974
1975        devres_remove_group(edac->dev, altr_edac_a10_device_add);
1976
1977        return 0;
1978
1979err_release_group1:
1980        edac_device_free_ctl_info(dci);
1981err_release_group:
1982        devres_release_group(edac->dev, NULL);
1983        edac_printk(KERN_ERR, EDAC_DEVICE,
1984                    "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
1985
1986        return rc;
1987}
1988
1989static void a10_eccmgr_irq_mask(struct irq_data *d)
1990{
1991        struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
1992
1993        regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST,
1994                     BIT(d->hwirq));
1995}
1996
1997static void a10_eccmgr_irq_unmask(struct irq_data *d)
1998{
1999        struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
2000
2001        regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST,
2002                     BIT(d->hwirq));
2003}
2004
2005static int a10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq,
2006                                    irq_hw_number_t hwirq)
2007{
2008        struct altr_arria10_edac *edac = d->host_data;
2009
2010        irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq);
2011        irq_set_chip_data(irq, edac);
2012        irq_set_noprobe(irq);
2013
2014        return 0;
2015}
2016
2017static const struct irq_domain_ops a10_eccmgr_ic_ops = {
2018        .map = a10_eccmgr_irqdomain_map,
2019        .xlate = irq_domain_xlate_twocell,
2020};
2021
2022/************** Stratix 10 EDAC Double Bit Error Handler ************/
2023#define to_a10edac(p, m) container_of(p, struct altr_arria10_edac, m)
2024
2025#ifdef CONFIG_64BIT
2026/* panic routine issues reboot on non-zero panic_timeout */
2027extern int panic_timeout;
2028
2029/*
2030 * The double bit error is handled through SError which is fatal. This is
2031 * called as a panic notifier to printout ECC error info as part of the panic.
2032 */
2033static int s10_edac_dberr_handler(struct notifier_block *this,
2034                                  unsigned long event, void *ptr)
2035{
2036        struct altr_arria10_edac *edac = to_a10edac(this, panic_notifier);
2037        int err_addr, dberror;
2038
2039        regmap_read(edac->ecc_mgr_map, S10_SYSMGR_ECC_INTSTAT_DERR_OFST,
2040                    &dberror);
2041        regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, dberror);
2042        if (dberror & S10_DBE_IRQ_MASK) {
2043                struct list_head *position;
2044                struct altr_edac_device_dev *ed;
2045                struct arm_smccc_res result;
2046
2047                /* Find the matching DBE in the list of devices */
2048                list_for_each(position, &edac->a10_ecc_devices) {
2049                        ed = list_entry(position, struct altr_edac_device_dev,
2050                                        next);
2051                        if (!(BIT(ed->db_irq) & dberror))
2052                                continue;
2053
2054                        writel(ALTR_A10_ECC_DERRPENA,
2055                               ed->base + ALTR_A10_ECC_INTSTAT_OFST);
2056                        err_addr = readl(ed->base + ALTR_S10_DERR_ADDRA_OFST);
2057                        regmap_write(edac->ecc_mgr_map,
2058                                     S10_SYSMGR_UE_ADDR_OFST, err_addr);
2059                        edac_printk(KERN_ERR, EDAC_DEVICE,
2060                                    "EDAC: [Fatal DBE on %s @ 0x%08X]\n",
2061                                    ed->edac_dev_name, err_addr);
2062                        break;
2063                }
2064                /* Notify the System through SMC. Reboot delay = 1 second */
2065                panic_timeout = 1;
2066                arm_smccc_smc(INTEL_SIP_SMC_ECC_DBE, dberror, 0, 0, 0, 0,
2067                              0, 0, &result);
2068        }
2069
2070        return NOTIFY_DONE;
2071}
2072#endif
2073
2074/****************** Arria 10 EDAC Probe Function *********************/
2075static int altr_edac_a10_probe(struct platform_device *pdev)
2076{
2077        struct altr_arria10_edac *edac;
2078        struct device_node *child;
2079
2080        edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL);
2081        if (!edac)
2082                return -ENOMEM;
2083
2084        edac->dev = &pdev->dev;
2085        platform_set_drvdata(pdev, edac);
2086        INIT_LIST_HEAD(&edac->a10_ecc_devices);
2087
2088        edac->ecc_mgr_map =
2089                altr_sysmgr_regmap_lookup_by_phandle(pdev->dev.of_node,
2090                                                     "altr,sysmgr-syscon");
2091
2092        if (IS_ERR(edac->ecc_mgr_map)) {
2093                edac_printk(KERN_ERR, EDAC_DEVICE,
2094                            "Unable to get syscon altr,sysmgr-syscon\n");
2095                return PTR_ERR(edac->ecc_mgr_map);
2096        }
2097
2098        edac->irq_chip.name = pdev->dev.of_node->name;
2099        edac->irq_chip.irq_mask = a10_eccmgr_irq_mask;
2100        edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask;
2101        edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64,
2102                                             &a10_eccmgr_ic_ops, edac);
2103        if (!edac->domain) {
2104                dev_err(&pdev->dev, "Error adding IRQ domain\n");
2105                return -ENOMEM;
2106        }
2107
2108        edac->sb_irq = platform_get_irq(pdev, 0);
2109        if (edac->sb_irq < 0) {
2110                dev_err(&pdev->dev, "No SBERR IRQ resource\n");
2111                return edac->sb_irq;
2112        }
2113
2114        irq_set_chained_handler_and_data(edac->sb_irq,
2115                                         altr_edac_a10_irq_handler,
2116                                         edac);
2117
2118#ifdef CONFIG_64BIT
2119        {
2120                int dberror, err_addr;
2121
2122                edac->panic_notifier.notifier_call = s10_edac_dberr_handler;
2123                atomic_notifier_chain_register(&panic_notifier_list,
2124                                               &edac->panic_notifier);
2125
2126                /* Printout a message if uncorrectable error previously. */
2127                regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST,
2128                            &dberror);
2129                if (dberror) {
2130                        regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST,
2131                                    &err_addr);
2132                        edac_printk(KERN_ERR, EDAC_DEVICE,
2133                                    "Previous Boot UE detected[0x%X] @ 0x%X\n",
2134                                    dberror, err_addr);
2135                        /* Reset the sticky registers */
2136                        regmap_write(edac->ecc_mgr_map,
2137                                     S10_SYSMGR_UE_VAL_OFST, 0);
2138                        regmap_write(edac->ecc_mgr_map,
2139                                     S10_SYSMGR_UE_ADDR_OFST, 0);
2140                }
2141        }
2142#else
2143        edac->db_irq = platform_get_irq(pdev, 1);
2144        if (edac->db_irq < 0) {
2145                dev_err(&pdev->dev, "No DBERR IRQ resource\n");
2146                return edac->db_irq;
2147        }
2148        irq_set_chained_handler_and_data(edac->db_irq,
2149                                         altr_edac_a10_irq_handler, edac);
2150#endif
2151
2152        for_each_child_of_node(pdev->dev.of_node, child) {
2153                if (!of_device_is_available(child))
2154                        continue;
2155
2156                if (of_match_node(altr_edac_a10_device_of_match, child))
2157                        altr_edac_a10_device_add(edac, child);
2158
2159#ifdef CONFIG_EDAC_ALTERA_SDRAM
2160                else if (of_device_is_compatible(child, "altr,sdram-edac-a10"))
2161                        of_platform_populate(pdev->dev.of_node,
2162                                             altr_sdram_ctrl_of_match,
2163                                             NULL, &pdev->dev);
2164#endif
2165        }
2166
2167        return 0;
2168}
2169
2170static const struct of_device_id altr_edac_a10_of_match[] = {
2171        { .compatible = "altr,socfpga-a10-ecc-manager" },
2172        { .compatible = "altr,socfpga-s10-ecc-manager" },
2173        {},
2174};
2175MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match);
2176
2177static struct platform_driver altr_edac_a10_driver = {
2178        .probe =  altr_edac_a10_probe,
2179        .driver = {
2180                .name = "socfpga_a10_ecc_manager",
2181                .of_match_table = altr_edac_a10_of_match,
2182        },
2183};
2184module_platform_driver(altr_edac_a10_driver);
2185
2186MODULE_LICENSE("GPL v2");
2187MODULE_AUTHOR("Thor Thayer");
2188MODULE_DESCRIPTION("EDAC Driver for Altera Memories");
2189