linux/drivers/clk/zynq/clkc.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Zynq clock controller
   4 *
   5 *  Copyright (C) 2012 - 2013 Xilinx
   6 *
   7 *  S\xC3\xB6ren Brinkmann <soren.brinkmann@xilinx.com>
   8 */
   9
  10#include <linux/clk/zynq.h>
  11#include <linux/clk.h>
  12#include <linux/clk-provider.h>
  13#include <linux/of.h>
  14#include <linux/of_address.h>
  15#include <linux/slab.h>
  16#include <linux/string.h>
  17#include <linux/io.h>
  18
  19static void __iomem *zynq_clkc_base;
  20
  21#define SLCR_ARMPLL_CTRL                (zynq_clkc_base + 0x00)
  22#define SLCR_DDRPLL_CTRL                (zynq_clkc_base + 0x04)
  23#define SLCR_IOPLL_CTRL                 (zynq_clkc_base + 0x08)
  24#define SLCR_PLL_STATUS                 (zynq_clkc_base + 0x0c)
  25#define SLCR_ARM_CLK_CTRL               (zynq_clkc_base + 0x20)
  26#define SLCR_DDR_CLK_CTRL               (zynq_clkc_base + 0x24)
  27#define SLCR_DCI_CLK_CTRL               (zynq_clkc_base + 0x28)
  28#define SLCR_APER_CLK_CTRL              (zynq_clkc_base + 0x2c)
  29#define SLCR_GEM0_CLK_CTRL              (zynq_clkc_base + 0x40)
  30#define SLCR_GEM1_CLK_CTRL              (zynq_clkc_base + 0x44)
  31#define SLCR_SMC_CLK_CTRL               (zynq_clkc_base + 0x48)
  32#define SLCR_LQSPI_CLK_CTRL             (zynq_clkc_base + 0x4c)
  33#define SLCR_SDIO_CLK_CTRL              (zynq_clkc_base + 0x50)
  34#define SLCR_UART_CLK_CTRL              (zynq_clkc_base + 0x54)
  35#define SLCR_SPI_CLK_CTRL               (zynq_clkc_base + 0x58)
  36#define SLCR_CAN_CLK_CTRL               (zynq_clkc_base + 0x5c)
  37#define SLCR_CAN_MIOCLK_CTRL            (zynq_clkc_base + 0x60)
  38#define SLCR_DBG_CLK_CTRL               (zynq_clkc_base + 0x64)
  39#define SLCR_PCAP_CLK_CTRL              (zynq_clkc_base + 0x68)
  40#define SLCR_FPGA0_CLK_CTRL             (zynq_clkc_base + 0x70)
  41#define SLCR_621_TRUE                   (zynq_clkc_base + 0xc4)
  42#define SLCR_SWDT_CLK_SEL               (zynq_clkc_base + 0x204)
  43
  44#define NUM_MIO_PINS    54
  45
  46#define DBG_CLK_CTRL_CLKACT_TRC         BIT(0)
  47#define DBG_CLK_CTRL_CPU_1XCLKACT       BIT(1)
  48
  49enum zynq_clk {
  50        armpll, ddrpll, iopll,
  51        cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x,
  52        ddr2x, ddr3x, dci,
  53        lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1,
  54        sdio0, sdio1, uart0, uart1, spi0, spi1, dma,
  55        usb0_aper, usb1_aper, gem0_aper, gem1_aper,
  56        sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper,
  57        i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper,
  58        smc_aper, swdt, dbg_trc, dbg_apb, clk_max};
  59
  60static struct clk *ps_clk;
  61static struct clk *clks[clk_max];
  62static struct clk_onecell_data clk_data;
  63
  64static DEFINE_SPINLOCK(armpll_lock);
  65static DEFINE_SPINLOCK(ddrpll_lock);
  66static DEFINE_SPINLOCK(iopll_lock);
  67static DEFINE_SPINLOCK(armclk_lock);
  68static DEFINE_SPINLOCK(swdtclk_lock);
  69static DEFINE_SPINLOCK(ddrclk_lock);
  70static DEFINE_SPINLOCK(dciclk_lock);
  71static DEFINE_SPINLOCK(gem0clk_lock);
  72static DEFINE_SPINLOCK(gem1clk_lock);
  73static DEFINE_SPINLOCK(canclk_lock);
  74static DEFINE_SPINLOCK(canmioclk_lock);
  75static DEFINE_SPINLOCK(dbgclk_lock);
  76static DEFINE_SPINLOCK(aperclk_lock);
  77
  78static const char *const armpll_parents[] __initconst = {"armpll_int",
  79        "ps_clk"};
  80static const char *const ddrpll_parents[] __initconst = {"ddrpll_int",
  81        "ps_clk"};
  82static const char *const iopll_parents[] __initconst = {"iopll_int",
  83        "ps_clk"};
  84static const char *gem0_mux_parents[] __initdata = {"gem0_div1", "dummy_name"};
  85static const char *gem1_mux_parents[] __initdata = {"gem1_div1", "dummy_name"};
  86static const char *const can0_mio_mux2_parents[] __initconst = {"can0_gate",
  87        "can0_mio_mux"};
  88static const char *const can1_mio_mux2_parents[] __initconst = {"can1_gate",
  89        "can1_mio_mux"};
  90static const char *dbg_emio_mux_parents[] __initdata = {"dbg_div",
  91        "dummy_name"};
  92
  93static const char *const dbgtrc_emio_input_names[] __initconst = {
  94        "trace_emio_clk"};
  95static const char *const gem0_emio_input_names[] __initconst = {
  96        "gem0_emio_clk"};
  97static const char *const gem1_emio_input_names[] __initconst = {
  98        "gem1_emio_clk"};
  99static const char *const swdt_ext_clk_input_names[] __initconst = {
 100        "swdt_ext_clk"};
 101
 102static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
 103                const char *clk_name, void __iomem *fclk_ctrl_reg,
 104                const char **parents, int enable)
 105{
 106        u32 enable_reg;
 107        char *mux_name;
 108        char *div0_name;
 109        char *div1_name;
 110        spinlock_t *fclk_lock;
 111        spinlock_t *fclk_gate_lock;
 112        void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8;
 113
 114        fclk_lock = kmalloc(sizeof(*fclk_lock), GFP_KERNEL);
 115        if (!fclk_lock)
 116                goto err;
 117        fclk_gate_lock = kmalloc(sizeof(*fclk_gate_lock), GFP_KERNEL);
 118        if (!fclk_gate_lock)
 119                goto err_fclk_gate_lock;
 120        spin_lock_init(fclk_lock);
 121        spin_lock_init(fclk_gate_lock);
 122
 123        mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name);
 124        if (!mux_name)
 125                goto err_mux_name;
 126        div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name);
 127        if (!div0_name)
 128                goto err_div0_name;
 129        div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name);
 130        if (!div1_name)
 131                goto err_div1_name;
 132
 133        clk_register_mux(NULL, mux_name, parents, 4,
 134                        CLK_SET_RATE_NO_REPARENT, fclk_ctrl_reg, 4, 2, 0,
 135                        fclk_lock);
 136
 137        clk_register_divider(NULL, div0_name, mux_name,
 138                        0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED |
 139                        CLK_DIVIDER_ALLOW_ZERO, fclk_lock);
 140
 141        clk_register_divider(NULL, div1_name, div0_name,
 142                        CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6,
 143                        CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
 144                        fclk_lock);
 145
 146        clks[fclk] = clk_register_gate(NULL, clk_name,
 147                        div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg,
 148                        0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock);
 149        enable_reg = readl(fclk_gate_reg) & 1;
 150        if (enable && !enable_reg) {
 151                if (clk_prepare_enable(clks[fclk]))
 152                        pr_warn("%s: FCLK%u enable failed\n", __func__,
 153                                        fclk - fclk0);
 154        }
 155        kfree(mux_name);
 156        kfree(div0_name);
 157        kfree(div1_name);
 158
 159        return;
 160
 161err_div1_name:
 162        kfree(div0_name);
 163err_div0_name:
 164        kfree(mux_name);
 165err_mux_name:
 166        kfree(fclk_gate_lock);
 167err_fclk_gate_lock:
 168        kfree(fclk_lock);
 169err:
 170        clks[fclk] = ERR_PTR(-ENOMEM);
 171}
 172
 173static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0,
 174                enum zynq_clk clk1, const char *clk_name0,
 175                const char *clk_name1, void __iomem *clk_ctrl,
 176                const char **parents, unsigned int two_gates)
 177{
 178        char *mux_name;
 179        char *div_name;
 180        spinlock_t *lock;
 181
 182        lock = kmalloc(sizeof(*lock), GFP_KERNEL);
 183        if (!lock)
 184                goto err;
 185        spin_lock_init(lock);
 186
 187        mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0);
 188        div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0);
 189
 190        clk_register_mux(NULL, mux_name, parents, 4,
 191                        CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock);
 192
 193        clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
 194                        CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock);
 195
 196        clks[clk0] = clk_register_gate(NULL, clk_name0, div_name,
 197                        CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock);
 198        if (two_gates)
 199                clks[clk1] = clk_register_gate(NULL, clk_name1, div_name,
 200                                CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock);
 201
 202        kfree(mux_name);
 203        kfree(div_name);
 204
 205        return;
 206
 207err:
 208        clks[clk0] = ERR_PTR(-ENOMEM);
 209        if (two_gates)
 210                clks[clk1] = ERR_PTR(-ENOMEM);
 211}
 212
 213static void __init zynq_clk_setup(struct device_node *np)
 214{
 215        int i;
 216        u32 tmp;
 217        int ret;
 218        char *clk_name;
 219        unsigned int fclk_enable = 0;
 220        const char *clk_output_name[clk_max];
 221        const char *cpu_parents[4];
 222        const char *periph_parents[4];
 223        const char *swdt_ext_clk_mux_parents[2];
 224        const char *can_mio_mux_parents[NUM_MIO_PINS];
 225        const char *dummy_nm = "dummy_name";
 226
 227        pr_info("Zynq clock init\n");
 228
 229        /* get clock output names from DT */
 230        for (i = 0; i < clk_max; i++) {
 231                if (of_property_read_string_index(np, "clock-output-names",
 232                                  i, &clk_output_name[i])) {
 233                        pr_err("%s: clock output name not in DT\n", __func__);
 234                        BUG();
 235                }
 236        }
 237        cpu_parents[0] = clk_output_name[armpll];
 238        cpu_parents[1] = clk_output_name[armpll];
 239        cpu_parents[2] = clk_output_name[ddrpll];
 240        cpu_parents[3] = clk_output_name[iopll];
 241        periph_parents[0] = clk_output_name[iopll];
 242        periph_parents[1] = clk_output_name[iopll];
 243        periph_parents[2] = clk_output_name[armpll];
 244        periph_parents[3] = clk_output_name[ddrpll];
 245
 246        of_property_read_u32(np, "fclk-enable", &fclk_enable);
 247
 248        /* ps_clk */
 249        ret = of_property_read_u32(np, "ps-clk-frequency", &tmp);
 250        if (ret) {
 251                pr_warn("ps_clk frequency not specified, using 33 MHz.\n");
 252                tmp = 33333333;
 253        }
 254        ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, 0, tmp);
 255
 256        /* PLLs */
 257        clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL,
 258                        SLCR_PLL_STATUS, 0, &armpll_lock);
 259        clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll],
 260                        armpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
 261                        SLCR_ARMPLL_CTRL, 4, 1, 0, &armpll_lock);
 262
 263        clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL,
 264                        SLCR_PLL_STATUS, 1, &ddrpll_lock);
 265        clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll],
 266                        ddrpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
 267                        SLCR_DDRPLL_CTRL, 4, 1, 0, &ddrpll_lock);
 268
 269        clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL,
 270                        SLCR_PLL_STATUS, 2, &iopll_lock);
 271        clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll],
 272                        iopll_parents, 2, CLK_SET_RATE_NO_REPARENT,
 273                        SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock);
 274
 275        /* CPU clocks */
 276        tmp = readl(SLCR_621_TRUE) & 1;
 277        clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
 278                        CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0,
 279                        &armclk_lock);
 280        clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
 281                        SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
 282                        CLK_DIVIDER_ALLOW_ZERO, &armclk_lock);
 283
 284        clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x],
 285                        "cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
 286                        SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock);
 287
 288        clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0,
 289                        1, 2);
 290        clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x],
 291                        "cpu_3or2x_div", CLK_IGNORE_UNUSED,
 292                        SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock);
 293
 294        clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1,
 295                        2 + tmp);
 296        clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x],
 297                        "cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL,
 298                        26, 0, &armclk_lock);
 299        clk_prepare_enable(clks[cpu_2x]);
 300
 301        clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1,
 302                        4 + 2 * tmp);
 303        clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x],
 304                        "cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27,
 305                        0, &armclk_lock);
 306
 307        /* Timers */
 308        swdt_ext_clk_mux_parents[0] = clk_output_name[cpu_1x];
 309        for (i = 0; i < ARRAY_SIZE(swdt_ext_clk_input_names); i++) {
 310                int idx = of_property_match_string(np, "clock-names",
 311                                swdt_ext_clk_input_names[i]);
 312                if (idx >= 0)
 313                        swdt_ext_clk_mux_parents[i + 1] =
 314                                of_clk_get_parent_name(np, idx);
 315                else
 316                        swdt_ext_clk_mux_parents[i + 1] = dummy_nm;
 317        }
 318        clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt],
 319                        swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT |
 320                        CLK_SET_RATE_NO_REPARENT, SLCR_SWDT_CLK_SEL, 0, 1, 0,
 321                        &swdtclk_lock);
 322
 323        /* DDR clocks */
 324        clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
 325                        SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED |
 326                        CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
 327        clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x],
 328                        "ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock);
 329        clk_prepare_enable(clks[ddr2x]);
 330        clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,
 331                        SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED |
 332                        CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
 333        clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x],
 334                        "ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock);
 335        clk_prepare_enable(clks[ddr3x]);
 336
 337        clk_register_divider(NULL, "dci_div0", "ddrpll", 0,
 338                        SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
 339                        CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock);
 340        clk_register_divider(NULL, "dci_div1", "dci_div0",
 341                        CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6,
 342                        CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
 343                        &dciclk_lock);
 344        clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1",
 345                        CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0,
 346                        &dciclk_lock);
 347        clk_prepare_enable(clks[dci]);
 348
 349        /* Peripheral clocks */
 350        for (i = fclk0; i <= fclk3; i++) {
 351                int enable = !!(fclk_enable & BIT(i - fclk0));
 352                zynq_clk_register_fclk(i, clk_output_name[i],
 353                                SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0),
 354                                periph_parents, enable);
 355        }
 356
 357        zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL,
 358                        SLCR_LQSPI_CLK_CTRL, periph_parents, 0);
 359
 360        zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL,
 361                        SLCR_SMC_CLK_CTRL, periph_parents, 0);
 362
 363        zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL,
 364                        SLCR_PCAP_CLK_CTRL, periph_parents, 0);
 365
 366        zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0],
 367                        clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL,
 368                        periph_parents, 1);
 369
 370        zynq_clk_register_periph_clk(uart0, uart1, clk_output_name[uart0],
 371                        clk_output_name[uart1], SLCR_UART_CLK_CTRL,
 372                        periph_parents, 1);
 373
 374        zynq_clk_register_periph_clk(spi0, spi1, clk_output_name[spi0],
 375                        clk_output_name[spi1], SLCR_SPI_CLK_CTRL,
 376                        periph_parents, 1);
 377
 378        for (i = 0; i < ARRAY_SIZE(gem0_emio_input_names); i++) {
 379                int idx = of_property_match_string(np, "clock-names",
 380                                gem0_emio_input_names[i]);
 381                if (idx >= 0)
 382                        gem0_mux_parents[i + 1] = of_clk_get_parent_name(np,
 383                                        idx);
 384        }
 385        clk_register_mux(NULL, "gem0_mux", periph_parents, 4,
 386                        CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 4, 2, 0,
 387                        &gem0clk_lock);
 388        clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
 389                        SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
 390                        CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock);
 391        clk_register_divider(NULL, "gem0_div1", "gem0_div0",
 392                        CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6,
 393                        CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
 394                        &gem0clk_lock);
 395        clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
 396                        CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 397                        SLCR_GEM0_CLK_CTRL, 6, 1, 0,
 398                        &gem0clk_lock);
 399        clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0],
 400                        "gem0_emio_mux", CLK_SET_RATE_PARENT,
 401                        SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock);
 402
 403        for (i = 0; i < ARRAY_SIZE(gem1_emio_input_names); i++) {
 404                int idx = of_property_match_string(np, "clock-names",
 405                                gem1_emio_input_names[i]);
 406                if (idx >= 0)
 407                        gem1_mux_parents[i + 1] = of_clk_get_parent_name(np,
 408                                        idx);
 409        }
 410        clk_register_mux(NULL, "gem1_mux", periph_parents, 4,
 411                        CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 4, 2, 0,
 412                        &gem1clk_lock);
 413        clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
 414                        SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
 415                        CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock);
 416        clk_register_divider(NULL, "gem1_div1", "gem1_div0",
 417                        CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6,
 418                        CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
 419                        &gem1clk_lock);
 420        clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
 421                        CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 422                        SLCR_GEM1_CLK_CTRL, 6, 1, 0,
 423                        &gem1clk_lock);
 424        clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1],
 425                        "gem1_emio_mux", CLK_SET_RATE_PARENT,
 426                        SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock);
 427
 428        tmp = strlen("mio_clk_00x");
 429        clk_name = kmalloc(tmp, GFP_KERNEL);
 430        for (i = 0; i < NUM_MIO_PINS; i++) {
 431                int idx;
 432
 433                snprintf(clk_name, tmp, "mio_clk_%2.2d", i);
 434                idx = of_property_match_string(np, "clock-names", clk_name);
 435                if (idx >= 0)
 436                        can_mio_mux_parents[i] = of_clk_get_parent_name(np,
 437                                                idx);
 438                else
 439                        can_mio_mux_parents[i] = dummy_nm;
 440        }
 441        kfree(clk_name);
 442        clk_register_mux(NULL, "can_mux", periph_parents, 4,
 443                        CLK_SET_RATE_NO_REPARENT, SLCR_CAN_CLK_CTRL, 4, 2, 0,
 444                        &canclk_lock);
 445        clk_register_divider(NULL, "can_div0", "can_mux", 0,
 446                        SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
 447                        CLK_DIVIDER_ALLOW_ZERO, &canclk_lock);
 448        clk_register_divider(NULL, "can_div1", "can_div0",
 449                        CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6,
 450                        CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
 451                        &canclk_lock);
 452        clk_register_gate(NULL, "can0_gate", "can_div1",
 453                        CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0,
 454                        &canclk_lock);
 455        clk_register_gate(NULL, "can1_gate", "can_div1",
 456                        CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0,
 457                        &canclk_lock);
 458        clk_register_mux(NULL, "can0_mio_mux",
 459                        can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
 460                        CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 0, 6, 0,
 461                        &canmioclk_lock);
 462        clk_register_mux(NULL, "can1_mio_mux",
 463                        can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
 464                        CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 16, 6,
 465                        0, &canmioclk_lock);
 466        clks[can0] = clk_register_mux(NULL, clk_output_name[can0],
 467                        can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
 468                        CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 6, 1, 0,
 469                        &canmioclk_lock);
 470        clks[can1] = clk_register_mux(NULL, clk_output_name[can1],
 471                        can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
 472                        CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 22, 1,
 473                        0, &canmioclk_lock);
 474
 475        for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) {
 476                int idx = of_property_match_string(np, "clock-names",
 477                                dbgtrc_emio_input_names[i]);
 478                if (idx >= 0)
 479                        dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np,
 480                                        idx);
 481        }
 482        clk_register_mux(NULL, "dbg_mux", periph_parents, 4,
 483                        CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 4, 2, 0,
 484                        &dbgclk_lock);
 485        clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
 486                        SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
 487                        CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock);
 488        clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2,
 489                        CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 6, 1, 0,
 490                        &dbgclk_lock);
 491        clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc],
 492                        "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL,
 493                        0, 0, &dbgclk_lock);
 494        clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb],
 495                        clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0,
 496                        &dbgclk_lock);
 497
 498        /* leave debug clocks in the state the bootloader set them up to */
 499        tmp = readl(SLCR_DBG_CLK_CTRL);
 500        if (tmp & DBG_CLK_CTRL_CLKACT_TRC)
 501                if (clk_prepare_enable(clks[dbg_trc]))
 502                        pr_warn("%s: trace clk enable failed\n", __func__);
 503        if (tmp & DBG_CLK_CTRL_CPU_1XCLKACT)
 504                if (clk_prepare_enable(clks[dbg_apb]))
 505                        pr_warn("%s: debug APB clk enable failed\n", __func__);
 506
 507        /* One gated clock for all APER clocks. */
 508        clks[dma] = clk_register_gate(NULL, clk_output_name[dma],
 509                        clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0,
 510                        &aperclk_lock);
 511        clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper],
 512                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 2, 0,
 513                        &aperclk_lock);
 514        clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper],
 515                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 3, 0,
 516                        &aperclk_lock);
 517        clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper],
 518                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 6, 0,
 519                        &aperclk_lock);
 520        clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper],
 521                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 7, 0,
 522                        &aperclk_lock);
 523        clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper],
 524                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 10, 0,
 525                        &aperclk_lock);
 526        clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper],
 527                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 11, 0,
 528                        &aperclk_lock);
 529        clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper],
 530                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 14, 0,
 531                        &aperclk_lock);
 532        clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper],
 533                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 15, 0,
 534                        &aperclk_lock);
 535        clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper],
 536                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 16, 0,
 537                        &aperclk_lock);
 538        clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper],
 539                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 17, 0,
 540                        &aperclk_lock);
 541        clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper],
 542                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 18, 0,
 543                        &aperclk_lock);
 544        clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper],
 545                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 19, 0,
 546                        &aperclk_lock);
 547        clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper],
 548                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 20, 0,
 549                        &aperclk_lock);
 550        clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper],
 551                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 21, 0,
 552                        &aperclk_lock);
 553        clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper],
 554                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 22, 0,
 555                        &aperclk_lock);
 556        clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper],
 557                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 23, 0,
 558                        &aperclk_lock);
 559        clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper],
 560                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 24, 0,
 561                        &aperclk_lock);
 562
 563        for (i = 0; i < ARRAY_SIZE(clks); i++) {
 564                if (IS_ERR(clks[i])) {
 565                        pr_err("Zynq clk %d: register failed with %ld\n",
 566                               i, PTR_ERR(clks[i]));
 567                        BUG();
 568                }
 569        }
 570
 571        clk_data.clks = clks;
 572        clk_data.clk_num = ARRAY_SIZE(clks);
 573        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 574}
 575
 576CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup);
 577
 578void __init zynq_clock_init(void)
 579{
 580        struct device_node *np;
 581        struct device_node *slcr;
 582        struct resource res;
 583
 584        np = of_find_compatible_node(NULL, NULL, "xlnx,ps7-clkc");
 585        if (!np) {
 586                pr_err("%s: clkc node not found\n", __func__);
 587                goto np_err;
 588        }
 589
 590        if (of_address_to_resource(np, 0, &res)) {
 591                pr_err("%pOFn: failed to get resource\n", np);
 592                goto np_err;
 593        }
 594
 595        slcr = of_get_parent(np);
 596
 597        if (slcr->data) {
 598                zynq_clkc_base = (__force void __iomem *)slcr->data + res.start;
 599        } else {
 600                pr_err("%pOFn: Unable to get I/O memory\n", np);
 601                of_node_put(slcr);
 602                goto np_err;
 603        }
 604
 605        pr_info("%s: clkc starts at %p\n", __func__, zynq_clkc_base);
 606
 607        of_node_put(slcr);
 608        of_node_put(np);
 609
 610        return;
 611
 612np_err:
 613        of_node_put(np);
 614        BUG();
 615}
 616