linux/drivers/clk/samsung/clk-exynos3250.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   4 *
   5 * Common Clock Framework support for Exynos3250 SoC.
   6 */
   7
   8#include <linux/clk-provider.h>
   9#include <linux/io.h>
  10#include <linux/of.h>
  11#include <linux/of_address.h>
  12#include <linux/platform_device.h>
  13
  14#include <dt-bindings/clock/exynos3250.h>
  15
  16#include "clk.h"
  17#include "clk-cpu.h"
  18#include "clk-pll.h"
  19
  20#define SRC_LEFTBUS             0x4200
  21#define DIV_LEFTBUS             0x4500
  22#define GATE_IP_LEFTBUS         0x4800
  23#define SRC_RIGHTBUS            0x8200
  24#define DIV_RIGHTBUS            0x8500
  25#define GATE_IP_RIGHTBUS        0x8800
  26#define GATE_IP_PERIR           0x8960
  27#define MPLL_LOCK               0xc010
  28#define MPLL_CON0               0xc110
  29#define VPLL_LOCK               0xc020
  30#define VPLL_CON0               0xc120
  31#define UPLL_LOCK               0xc030
  32#define UPLL_CON0               0xc130
  33#define SRC_TOP0                0xc210
  34#define SRC_TOP1                0xc214
  35#define SRC_CAM                 0xc220
  36#define SRC_MFC                 0xc228
  37#define SRC_G3D                 0xc22c
  38#define SRC_LCD                 0xc234
  39#define SRC_ISP                 0xc238
  40#define SRC_FSYS                0xc240
  41#define SRC_PERIL0              0xc250
  42#define SRC_PERIL1              0xc254
  43#define SRC_MASK_TOP            0xc310
  44#define SRC_MASK_CAM            0xc320
  45#define SRC_MASK_LCD            0xc334
  46#define SRC_MASK_ISP            0xc338
  47#define SRC_MASK_FSYS           0xc340
  48#define SRC_MASK_PERIL0         0xc350
  49#define SRC_MASK_PERIL1         0xc354
  50#define DIV_TOP                 0xc510
  51#define DIV_CAM                 0xc520
  52#define DIV_MFC                 0xc528
  53#define DIV_G3D                 0xc52c
  54#define DIV_LCD                 0xc534
  55#define DIV_ISP                 0xc538
  56#define DIV_FSYS0               0xc540
  57#define DIV_FSYS1               0xc544
  58#define DIV_FSYS2               0xc548
  59#define DIV_PERIL0              0xc550
  60#define DIV_PERIL1              0xc554
  61#define DIV_PERIL3              0xc55c
  62#define DIV_PERIL4              0xc560
  63#define DIV_PERIL5              0xc564
  64#define DIV_CAM1                0xc568
  65#define CLKDIV2_RATIO           0xc580
  66#define GATE_SCLK_CAM           0xc820
  67#define GATE_SCLK_MFC           0xc828
  68#define GATE_SCLK_G3D           0xc82c
  69#define GATE_SCLK_LCD           0xc834
  70#define GATE_SCLK_ISP_TOP       0xc838
  71#define GATE_SCLK_FSYS          0xc840
  72#define GATE_SCLK_PERIL         0xc850
  73#define GATE_IP_CAM             0xc920
  74#define GATE_IP_MFC             0xc928
  75#define GATE_IP_G3D             0xc92c
  76#define GATE_IP_LCD             0xc934
  77#define GATE_IP_ISP             0xc938
  78#define GATE_IP_FSYS            0xc940
  79#define GATE_IP_PERIL           0xc950
  80#define GATE_BLOCK              0xc970
  81#define APLL_LOCK               0x14000
  82#define APLL_CON0               0x14100
  83#define SRC_CPU                 0x14200
  84#define DIV_CPU0                0x14500
  85#define DIV_CPU1                0x14504
  86#define PWR_CTRL1               0x15020
  87#define PWR_CTRL2               0x15024
  88
  89/* Below definitions are used for PWR_CTRL settings */
  90#define PWR_CTRL1_CORE2_DOWN_RATIO(x)           (((x) & 0x7) << 28)
  91#define PWR_CTRL1_CORE1_DOWN_RATIO(x)           (((x) & 0x7) << 16)
  92#define PWR_CTRL1_DIV2_DOWN_EN                  (1 << 9)
  93#define PWR_CTRL1_DIV1_DOWN_EN                  (1 << 8)
  94#define PWR_CTRL1_USE_CORE3_WFE                 (1 << 7)
  95#define PWR_CTRL1_USE_CORE2_WFE                 (1 << 6)
  96#define PWR_CTRL1_USE_CORE1_WFE                 (1 << 5)
  97#define PWR_CTRL1_USE_CORE0_WFE                 (1 << 4)
  98#define PWR_CTRL1_USE_CORE3_WFI                 (1 << 3)
  99#define PWR_CTRL1_USE_CORE2_WFI                 (1 << 2)
 100#define PWR_CTRL1_USE_CORE1_WFI                 (1 << 1)
 101#define PWR_CTRL1_USE_CORE0_WFI                 (1 << 0)
 102
 103static const unsigned long exynos3250_cmu_clk_regs[] __initconst = {
 104        SRC_LEFTBUS,
 105        DIV_LEFTBUS,
 106        GATE_IP_LEFTBUS,
 107        SRC_RIGHTBUS,
 108        DIV_RIGHTBUS,
 109        GATE_IP_RIGHTBUS,
 110        GATE_IP_PERIR,
 111        MPLL_LOCK,
 112        MPLL_CON0,
 113        VPLL_LOCK,
 114        VPLL_CON0,
 115        UPLL_LOCK,
 116        UPLL_CON0,
 117        SRC_TOP0,
 118        SRC_TOP1,
 119        SRC_CAM,
 120        SRC_MFC,
 121        SRC_G3D,
 122        SRC_LCD,
 123        SRC_ISP,
 124        SRC_FSYS,
 125        SRC_PERIL0,
 126        SRC_PERIL1,
 127        SRC_MASK_TOP,
 128        SRC_MASK_CAM,
 129        SRC_MASK_LCD,
 130        SRC_MASK_ISP,
 131        SRC_MASK_FSYS,
 132        SRC_MASK_PERIL0,
 133        SRC_MASK_PERIL1,
 134        DIV_TOP,
 135        DIV_CAM,
 136        DIV_MFC,
 137        DIV_G3D,
 138        DIV_LCD,
 139        DIV_ISP,
 140        DIV_FSYS0,
 141        DIV_FSYS1,
 142        DIV_FSYS2,
 143        DIV_PERIL0,
 144        DIV_PERIL1,
 145        DIV_PERIL3,
 146        DIV_PERIL4,
 147        DIV_PERIL5,
 148        DIV_CAM1,
 149        CLKDIV2_RATIO,
 150        GATE_SCLK_CAM,
 151        GATE_SCLK_MFC,
 152        GATE_SCLK_G3D,
 153        GATE_SCLK_LCD,
 154        GATE_SCLK_ISP_TOP,
 155        GATE_SCLK_FSYS,
 156        GATE_SCLK_PERIL,
 157        GATE_IP_CAM,
 158        GATE_IP_MFC,
 159        GATE_IP_G3D,
 160        GATE_IP_LCD,
 161        GATE_IP_ISP,
 162        GATE_IP_FSYS,
 163        GATE_IP_PERIL,
 164        GATE_BLOCK,
 165        APLL_LOCK,
 166        SRC_CPU,
 167        DIV_CPU0,
 168        DIV_CPU1,
 169        PWR_CTRL1,
 170        PWR_CTRL2,
 171};
 172
 173/* list of all parent clock list */
 174PNAME(mout_vpllsrc_p)           = { "fin_pll", };
 175
 176PNAME(mout_apll_p)              = { "fin_pll", "fout_apll", };
 177PNAME(mout_mpll_p)              = { "fin_pll", "fout_mpll", };
 178PNAME(mout_vpll_p)              = { "fin_pll", "fout_vpll", };
 179PNAME(mout_upll_p)              = { "fin_pll", "fout_upll", };
 180
 181PNAME(mout_mpll_user_p)         = { "fin_pll", "div_mpll_pre", };
 182PNAME(mout_epll_user_p)         = { "fin_pll", "mout_epll", };
 183PNAME(mout_core_p)              = { "mout_apll", "mout_mpll_user_c", };
 184PNAME(mout_hpm_p)               = { "mout_apll", "mout_mpll_user_c", };
 185
 186PNAME(mout_ebi_p)               = { "div_aclk_200", "div_aclk_160", };
 187PNAME(mout_ebi_1_p)             = { "mout_ebi", "mout_vpll", };
 188
 189PNAME(mout_gdl_p)               = { "mout_mpll_user_l", };
 190PNAME(mout_gdr_p)               = { "mout_mpll_user_r", };
 191
 192PNAME(mout_aclk_400_mcuisp_sub_p)
 193                                = { "fin_pll", "div_aclk_400_mcuisp", };
 194PNAME(mout_aclk_266_0_p)        = { "div_mpll_pre", "mout_vpll", };
 195PNAME(mout_aclk_266_1_p)        = { "mout_epll_user", };
 196PNAME(mout_aclk_266_p)          = { "mout_aclk_266_0", "mout_aclk_266_1", };
 197PNAME(mout_aclk_266_sub_p)      = { "fin_pll", "div_aclk_266", };
 198
 199PNAME(group_div_mpll_pre_p)     = { "div_mpll_pre", };
 200PNAME(group_epll_vpll_p)        = { "mout_epll_user", "mout_vpll" };
 201PNAME(group_sclk_p)             = { "xxti", "xusbxti",
 202                                    "none", "none",
 203                                    "none", "none", "div_mpll_pre",
 204                                    "mout_epll_user", "mout_vpll", };
 205PNAME(group_sclk_audio_p)       = { "audiocdclk", "none",
 206                                    "none", "none",
 207                                    "xxti", "xusbxti",
 208                                    "div_mpll_pre", "mout_epll_user",
 209                                    "mout_vpll", };
 210PNAME(group_sclk_cam_blk_p)     = { "xxti", "xusbxti",
 211                                    "none", "none", "none",
 212                                    "none", "div_mpll_pre",
 213                                    "mout_epll_user", "mout_vpll",
 214                                    "none", "none", "none",
 215                                    "div_cam_blk_320", };
 216PNAME(group_sclk_fimd0_p)       = { "xxti", "xusbxti",
 217                                    "m_bitclkhsdiv4_2l", "none",
 218                                    "none", "none", "div_mpll_pre",
 219                                    "mout_epll_user", "mout_vpll",
 220                                    "none", "none", "none",
 221                                    "div_lcd_blk_145", };
 222
 223PNAME(mout_mfc_p)               = { "mout_mfc_0", "mout_mfc_1" };
 224PNAME(mout_g3d_p)               = { "mout_g3d_0", "mout_g3d_1" };
 225
 226static const struct samsung_fixed_factor_clock fixed_factor_clks[] __initconst = {
 227        FFACTOR(0, "sclk_mpll_1600", "mout_mpll", 1, 1, 0),
 228        FFACTOR(0, "sclk_mpll_mif", "mout_mpll", 1, 2, 0),
 229        FFACTOR(0, "sclk_bpll", "fout_bpll", 1, 2, 0),
 230        FFACTOR(0, "div_cam_blk_320", "sclk_mpll_1600", 1, 5, 0),
 231        FFACTOR(0, "div_lcd_blk_145", "sclk_mpll_1600", 1, 11, 0),
 232
 233        /* HACK: fin_pll hardcoded to xusbxti until detection is implemented. */
 234        FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
 235};
 236
 237static const struct samsung_mux_clock mux_clks[] __initconst = {
 238        /*
 239         * NOTE: Following table is sorted by register address in ascending
 240         * order and then bitfield shift in descending order, as it is done
 241         * in the User's Manual. When adding new entries, please make sure
 242         * that the order is preserved, to avoid merge conflicts and make
 243         * further work with defined data easier.
 244         */
 245
 246        /* SRC_LEFTBUS */
 247        MUX(CLK_MOUT_MPLL_USER_L, "mout_mpll_user_l", mout_mpll_user_p,
 248            SRC_LEFTBUS, 4, 1),
 249        MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1),
 250
 251        /* SRC_RIGHTBUS */
 252        MUX(CLK_MOUT_MPLL_USER_R, "mout_mpll_user_r", mout_mpll_user_p,
 253            SRC_RIGHTBUS, 4, 1),
 254        MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1),
 255
 256        /* SRC_TOP0 */
 257        MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),
 258        MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p,SRC_TOP0, 24, 1),
 259        MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_div_mpll_pre_p, SRC_TOP0, 20, 1),
 260        MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_div_mpll_pre_p, SRC_TOP0, 16, 1),
 261        MUX(CLK_MOUT_ACLK_266_1, "mout_aclk_266_1", mout_aclk_266_1_p, SRC_TOP0, 14, 1),
 262        MUX(CLK_MOUT_ACLK_266_0, "mout_aclk_266_0", mout_aclk_266_0_p, SRC_TOP0, 13, 1),
 263        MUX(CLK_MOUT_ACLK_266, "mout_aclk_266", mout_aclk_266_p, SRC_TOP0, 12, 1),
 264        MUX(CLK_MOUT_VPLL, "mout_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
 265        MUX(CLK_MOUT_EPLL_USER, "mout_epll_user", mout_epll_user_p, SRC_TOP0, 4, 1),
 266        MUX(CLK_MOUT_EBI_1, "mout_ebi_1", mout_ebi_1_p, SRC_TOP0, 0, 1),
 267
 268        /* SRC_TOP1 */
 269        MUX(CLK_MOUT_UPLL, "mout_upll", mout_upll_p, SRC_TOP1, 28, 1),
 270        MUX(CLK_MOUT_ACLK_400_MCUISP_SUB, "mout_aclk_400_mcuisp_sub", mout_aclk_400_mcuisp_sub_p,
 271                SRC_TOP1, 24, 1),
 272        MUX(CLK_MOUT_ACLK_266_SUB, "mout_aclk_266_sub", mout_aclk_266_sub_p, SRC_TOP1, 20, 1),
 273        MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_TOP1, 12, 1),
 274        MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp", group_div_mpll_pre_p, SRC_TOP1, 8, 1),
 275        MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
 276
 277        /* SRC_CAM */
 278        MUX(CLK_MOUT_CAM1, "mout_cam1", group_sclk_p, SRC_CAM, 20, 4),
 279        MUX(CLK_MOUT_CAM_BLK, "mout_cam_blk", group_sclk_cam_blk_p, SRC_CAM, 0, 4),
 280
 281        /* SRC_MFC */
 282        MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
 283        MUX(CLK_MOUT_MFC_1, "mout_mfc_1", group_epll_vpll_p, SRC_MFC, 4, 1),
 284        MUX(CLK_MOUT_MFC_0, "mout_mfc_0", group_div_mpll_pre_p, SRC_MFC, 0, 1),
 285
 286        /* SRC_G3D */
 287        MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
 288        MUX(CLK_MOUT_G3D_1, "mout_g3d_1", group_epll_vpll_p, SRC_G3D, 4, 1),
 289        MUX(CLK_MOUT_G3D_0, "mout_g3d_0", group_div_mpll_pre_p, SRC_G3D, 0, 1),
 290
 291        /* SRC_LCD */
 292        MUX(CLK_MOUT_MIPI0, "mout_mipi0", group_sclk_p, SRC_LCD, 12, 4),
 293        MUX(CLK_MOUT_FIMD0, "mout_fimd0", group_sclk_fimd0_p, SRC_LCD, 0, 4),
 294
 295        /* SRC_ISP */
 296        MUX(CLK_MOUT_UART_ISP, "mout_uart_isp", group_sclk_p, SRC_ISP, 12, 4),
 297        MUX(CLK_MOUT_SPI1_ISP, "mout_spi1_isp", group_sclk_p, SRC_ISP, 8, 4),
 298        MUX(CLK_MOUT_SPI0_ISP, "mout_spi0_isp", group_sclk_p, SRC_ISP, 4, 4),
 299
 300        /* SRC_FSYS */
 301        MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
 302        MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),
 303        MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),
 304        MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
 305
 306        /* SRC_PERIL0 */
 307        MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
 308        MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
 309        MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
 310
 311        /* SRC_PERIL1 */
 312        MUX(CLK_MOUT_SPI1, "mout_spi1", group_sclk_p, SRC_PERIL1, 20, 4),
 313        MUX(CLK_MOUT_SPI0, "mout_spi0", group_sclk_p, SRC_PERIL1, 16, 4),
 314        MUX(CLK_MOUT_AUDIO, "mout_audio", group_sclk_audio_p, SRC_PERIL1, 4, 4),
 315
 316        /* SRC_CPU */
 317        MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,
 318            SRC_CPU, 24, 1),
 319        MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),
 320        MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1,
 321                        CLK_SET_RATE_PARENT, 0),
 322        MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
 323                        CLK_SET_RATE_PARENT, 0),
 324};
 325
 326static const struct samsung_div_clock div_clks[] __initconst = {
 327        /*
 328         * NOTE: Following table is sorted by register address in ascending
 329         * order and then bitfield shift in descending order, as it is done
 330         * in the User's Manual. When adding new entries, please make sure
 331         * that the order is preserved, to avoid merge conflicts and make
 332         * further work with defined data easier.
 333         */
 334
 335        /* DIV_LEFTBUS */
 336        DIV(CLK_DIV_GPL, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
 337        DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 4),
 338
 339        /* DIV_RIGHTBUS */
 340        DIV(CLK_DIV_GPR, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
 341        DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 4),
 342
 343        /* DIV_TOP */
 344        DIV(CLK_DIV_MPLL_PRE, "div_mpll_pre", "sclk_mpll_mif", DIV_TOP, 28, 2),
 345        DIV(CLK_DIV_ACLK_400_MCUISP, "div_aclk_400_mcuisp",
 346            "mout_aclk_400_mcuisp", DIV_TOP, 24, 3),
 347        DIV(CLK_DIV_EBI, "div_ebi", "mout_ebi_1", DIV_TOP, 16, 3),
 348        DIV(CLK_DIV_ACLK_200, "div_aclk_200", "mout_aclk_200", DIV_TOP, 12, 3),
 349        DIV(CLK_DIV_ACLK_160, "div_aclk_160", "mout_aclk_160", DIV_TOP, 8, 3),
 350        DIV(CLK_DIV_ACLK_100, "div_aclk_100", "mout_aclk_100", DIV_TOP, 4, 4),
 351        DIV(CLK_DIV_ACLK_266, "div_aclk_266", "mout_aclk_266", DIV_TOP, 0, 3),
 352
 353        /* DIV_CAM */
 354        DIV(CLK_DIV_CAM1, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
 355        DIV(CLK_DIV_CAM_BLK, "div_cam_blk", "mout_cam_blk", DIV_CAM, 0, 4),
 356
 357        /* DIV_MFC */
 358        DIV(CLK_DIV_MFC, "div_mfc", "mout_mfc", DIV_MFC, 0, 4),
 359
 360        /* DIV_G3D */
 361        DIV(CLK_DIV_G3D, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),
 362
 363        /* DIV_LCD */
 364        DIV_F(CLK_DIV_MIPI0_PRE, "div_mipi0_pre", "div_mipi0", DIV_LCD, 20, 4,
 365                CLK_SET_RATE_PARENT, 0),
 366        DIV(CLK_DIV_MIPI0, "div_mipi0", "mout_mipi0", DIV_LCD, 16, 4),
 367        DIV(CLK_DIV_FIMD0, "div_fimd0", "mout_fimd0", DIV_LCD, 0, 4),
 368
 369        /* DIV_ISP */
 370        DIV(CLK_DIV_UART_ISP, "div_uart_isp", "mout_uart_isp", DIV_ISP, 28, 4),
 371        DIV_F(CLK_DIV_SPI1_ISP_PRE, "div_spi1_isp_pre", "div_spi1_isp",
 372                DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
 373        DIV(CLK_DIV_SPI1_ISP, "div_spi1_isp", "mout_spi1_isp", DIV_ISP, 16, 4),
 374        DIV_F(CLK_DIV_SPI0_ISP_PRE, "div_spi0_isp_pre", "div_spi0_isp",
 375                DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
 376        DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 4, 4),
 377
 378        /* DIV_FSYS0 */
 379        DIV_F(CLK_DIV_TSADC_PRE, "div_tsadc_pre", "div_tsadc", DIV_FSYS0, 8, 8,
 380                CLK_SET_RATE_PARENT, 0),
 381        DIV(CLK_DIV_TSADC, "div_tsadc", "mout_tsadc", DIV_FSYS0, 0, 4),
 382
 383        /* DIV_FSYS1 */
 384        DIV_F(CLK_DIV_MMC1_PRE, "div_mmc1_pre", "div_mmc1", DIV_FSYS1, 24, 8,
 385                CLK_SET_RATE_PARENT, 0),
 386        DIV(CLK_DIV_MMC1, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
 387        DIV_F(CLK_DIV_MMC0_PRE, "div_mmc0_pre", "div_mmc0", DIV_FSYS1, 8, 8,
 388                CLK_SET_RATE_PARENT, 0),
 389        DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
 390
 391        /* DIV_FSYS2 */
 392        DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8,
 393                CLK_SET_RATE_PARENT, 0),
 394        DIV(CLK_DIV_MMC2, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
 395
 396        /* DIV_PERIL0 */
 397        DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
 398        DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
 399        DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
 400
 401        /* DIV_PERIL1 */
 402        DIV_F(CLK_DIV_SPI1_PRE, "div_spi1_pre", "div_spi1", DIV_PERIL1, 24, 8,
 403                CLK_SET_RATE_PARENT, 0),
 404        DIV(CLK_DIV_SPI1, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
 405        DIV_F(CLK_DIV_SPI0_PRE, "div_spi0_pre", "div_spi0", DIV_PERIL1, 8, 8,
 406                CLK_SET_RATE_PARENT, 0),
 407        DIV(CLK_DIV_SPI0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
 408
 409        /* DIV_PERIL4 */
 410        DIV(CLK_DIV_PCM, "div_pcm", "div_audio", DIV_PERIL4, 20, 8),
 411        DIV(CLK_DIV_AUDIO, "div_audio", "mout_audio", DIV_PERIL4, 16, 4),
 412
 413        /* DIV_PERIL5 */
 414        DIV(CLK_DIV_I2S, "div_i2s", "div_audio", DIV_PERIL5, 8, 6),
 415
 416        /* DIV_CPU0 */
 417        DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
 418        DIV(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
 419        DIV(CLK_DIV_PCLK_DBG, "div_pclk_dbg", "div_core2", DIV_CPU0, 20, 3),
 420        DIV(CLK_DIV_ATB, "div_atb", "div_core2", DIV_CPU0, 16, 3),
 421        DIV(CLK_DIV_COREM, "div_corem", "div_core2", DIV_CPU0, 4, 3),
 422        DIV(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3),
 423
 424        /* DIV_CPU1 */
 425        DIV(CLK_DIV_HPM, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
 426        DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
 427};
 428
 429static const struct samsung_gate_clock gate_clks[] __initconst = {
 430        /*
 431         * NOTE: Following table is sorted by register address in ascending
 432         * order and then bitfield shift in descending order, as it is done
 433         * in the User's Manual. When adding new entries, please make sure
 434         * that the order is preserved, to avoid merge conflicts and make
 435         * further work with defined data easier.
 436         */
 437
 438        /* GATE_IP_LEFTBUS */
 439        GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6,
 440                CLK_IGNORE_UNUSED, 0),
 441        GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4,
 442                CLK_IGNORE_UNUSED, 0),
 443        GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
 444                CLK_IGNORE_UNUSED, 0),
 445        GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0,
 446                CLK_IGNORE_UNUSED, 0),
 447
 448        /* GATE_IP_RIGHTBUS */
 449        GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100",
 450                GATE_IP_RIGHTBUS, 9, CLK_IGNORE_UNUSED, 0),
 451        GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100",
 452                GATE_IP_RIGHTBUS, 5, CLK_IGNORE_UNUSED, 0),
 453        GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100",
 454                GATE_IP_RIGHTBUS, 3, CLK_IGNORE_UNUSED, 0),
 455        GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100", GATE_IP_RIGHTBUS, 2,
 456                CLK_IGNORE_UNUSED, 0),
 457        GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100", GATE_IP_RIGHTBUS, 1,
 458                CLK_IGNORE_UNUSED, 0),
 459        GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100", GATE_IP_RIGHTBUS, 0,
 460                CLK_IGNORE_UNUSED, 0),
 461
 462        /* GATE_IP_PERIR */
 463        GATE(CLK_MONOCNT, "monocnt", "div_aclk_100", GATE_IP_PERIR, 22,
 464                CLK_IGNORE_UNUSED, 0),
 465        GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21,
 466                CLK_IGNORE_UNUSED, 0),
 467        GATE(CLK_PROVISIONKEY1, "provisionkey1", "div_aclk_100",
 468                GATE_IP_PERIR, 20, CLK_IGNORE_UNUSED, 0),
 469        GATE(CLK_PROVISIONKEY0, "provisionkey0", "div_aclk_100",
 470                GATE_IP_PERIR, 19, CLK_IGNORE_UNUSED, 0),
 471        GATE(CLK_CMU_ISPPART, "cmu_isppart", "div_aclk_100", GATE_IP_PERIR, 18,
 472                CLK_IGNORE_UNUSED, 0),
 473        GATE(CLK_TMU_APBIF, "tmu_apbif", "div_aclk_100",
 474                GATE_IP_PERIR, 17, 0, 0),
 475        GATE(CLK_KEYIF, "keyif", "div_aclk_100", GATE_IP_PERIR, 16, 0, 0),
 476        GATE(CLK_RTC, "rtc", "div_aclk_100", GATE_IP_PERIR, 15, 0, 0),
 477        GATE(CLK_WDT, "wdt", "div_aclk_100", GATE_IP_PERIR, 14, 0, 0),
 478        GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0),
 479        GATE(CLK_SECKEY, "seckey", "div_aclk_100", GATE_IP_PERIR, 12,
 480                CLK_IGNORE_UNUSED, 0),
 481        GATE(CLK_TZPC5, "tzpc5", "div_aclk_100", GATE_IP_PERIR, 10,
 482                CLK_IGNORE_UNUSED, 0),
 483        GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9,
 484                CLK_IGNORE_UNUSED, 0),
 485        GATE(CLK_TZPC3, "tzpc3", "div_aclk_100", GATE_IP_PERIR, 8,
 486                CLK_IGNORE_UNUSED, 0),
 487        GATE(CLK_TZPC2, "tzpc2", "div_aclk_100", GATE_IP_PERIR, 7,
 488                CLK_IGNORE_UNUSED, 0),
 489        GATE(CLK_TZPC1, "tzpc1", "div_aclk_100", GATE_IP_PERIR, 6,
 490                CLK_IGNORE_UNUSED, 0),
 491        GATE(CLK_TZPC0, "tzpc0", "div_aclk_100", GATE_IP_PERIR, 5,
 492                CLK_IGNORE_UNUSED, 0),
 493        GATE(CLK_CMU_COREPART, "cmu_corepart", "div_aclk_100", GATE_IP_PERIR, 4,
 494                CLK_IGNORE_UNUSED, 0),
 495        GATE(CLK_CMU_TOPPART, "cmu_toppart", "div_aclk_100", GATE_IP_PERIR, 3,
 496                CLK_IGNORE_UNUSED, 0),
 497        GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2,
 498                CLK_IGNORE_UNUSED, 0),
 499        GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1,
 500                CLK_IGNORE_UNUSED, 0),
 501        GATE(CLK_CHIP_ID, "chip_id", "div_aclk_100", GATE_IP_PERIR, 0,
 502                CLK_IGNORE_UNUSED, 0),
 503
 504        /* GATE_SCLK_CAM */
 505        GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_cam_blk",
 506                GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0),
 507        GATE(CLK_SCLK_M2MSCALER, "sclk_m2mscaler", "div_cam_blk",
 508                GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
 509        GATE(CLK_SCLK_GSCALER1, "sclk_gscaler1", "div_cam_blk",
 510                GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0),
 511        GATE(CLK_SCLK_GSCALER0, "sclk_gscaler0", "div_cam_blk",
 512                GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0),
 513
 514        /* GATE_SCLK_MFC */
 515        GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc",
 516                GATE_SCLK_MFC, 0, CLK_SET_RATE_PARENT, 0),
 517
 518        /* GATE_SCLK_G3D */
 519        GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d",
 520                GATE_SCLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
 521
 522        /* GATE_SCLK_LCD */
 523        GATE(CLK_SCLK_MIPIDPHY2L, "sclk_mipidphy2l", "div_mipi0",
 524                GATE_SCLK_LCD, 4, CLK_SET_RATE_PARENT, 0),
 525        GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi0_pre",
 526                GATE_SCLK_LCD, 3, CLK_SET_RATE_PARENT, 0),
 527        GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0",
 528                GATE_SCLK_LCD, 0, CLK_SET_RATE_PARENT, 0),
 529
 530        /* GATE_SCLK_ISP_TOP */
 531        GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
 532                GATE_SCLK_ISP_TOP, 4, CLK_SET_RATE_PARENT, 0),
 533        GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp",
 534                GATE_SCLK_ISP_TOP, 3, CLK_SET_RATE_PARENT, 0),
 535        GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp",
 536                GATE_SCLK_ISP_TOP, 2, CLK_SET_RATE_PARENT, 0),
 537        GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp",
 538                GATE_SCLK_ISP_TOP, 1, CLK_SET_RATE_PARENT, 0),
 539
 540        /* GATE_SCLK_FSYS */
 541        GATE(CLK_SCLK_UPLL, "sclk_upll", "mout_upll", GATE_SCLK_FSYS, 10, 0, 0),
 542        GATE(CLK_SCLK_TSADC, "sclk_tsadc", "div_tsadc_pre",
 543                GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
 544        GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
 545                GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
 546        GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre",
 547                GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
 548        GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
 549                GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
 550        GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
 551                GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
 552
 553        /* GATE_SCLK_PERIL */
 554        GATE(CLK_SCLK_I2S, "sclk_i2s", "div_i2s",
 555                GATE_SCLK_PERIL, 18, CLK_SET_RATE_PARENT, 0),
 556        GATE(CLK_SCLK_PCM, "sclk_pcm", "div_pcm",
 557                GATE_SCLK_PERIL, 16, CLK_SET_RATE_PARENT, 0),
 558        GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi1_pre",
 559                GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
 560        GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
 561                GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
 562
 563        GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
 564                GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
 565        GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
 566                GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
 567        GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
 568                GATE_SCLK_PERIL, 0, CLK_SET_RATE_PARENT, 0),
 569
 570        /* GATE_IP_CAM */
 571        GATE(CLK_QEJPEG, "qejpeg", "div_cam_blk_320", GATE_IP_CAM, 19,
 572                CLK_IGNORE_UNUSED, 0),
 573        GATE(CLK_PIXELASYNCM1, "pixelasyncm1", "div_cam_blk_320",
 574                GATE_IP_CAM, 18, CLK_IGNORE_UNUSED, 0),
 575        GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_cam_blk_320",
 576                GATE_IP_CAM, 17, CLK_IGNORE_UNUSED, 0),
 577        GATE(CLK_PPMUCAMIF, "ppmucamif", "div_cam_blk_320",
 578                GATE_IP_CAM, 16, CLK_IGNORE_UNUSED, 0),
 579        GATE(CLK_QEM2MSCALER, "qem2mscaler", "div_cam_blk_320",
 580                GATE_IP_CAM, 14, CLK_IGNORE_UNUSED, 0),
 581        GATE(CLK_QEGSCALER1, "qegscaler1", "div_cam_blk_320",
 582                GATE_IP_CAM, 13, CLK_IGNORE_UNUSED, 0),
 583        GATE(CLK_QEGSCALER0, "qegscaler0", "div_cam_blk_320",
 584                GATE_IP_CAM, 12, CLK_IGNORE_UNUSED, 0),
 585        GATE(CLK_SMMUJPEG, "smmujpeg", "div_cam_blk_320",
 586                GATE_IP_CAM, 11, 0, 0),
 587        GATE(CLK_SMMUM2M2SCALER, "smmum2m2scaler", "div_cam_blk_320",
 588                GATE_IP_CAM, 9, 0, 0),
 589        GATE(CLK_SMMUGSCALER1, "smmugscaler1", "div_cam_blk_320",
 590                GATE_IP_CAM, 8, 0, 0),
 591        GATE(CLK_SMMUGSCALER0, "smmugscaler0", "div_cam_blk_320",
 592                GATE_IP_CAM, 7, 0, 0),
 593        GATE(CLK_JPEG, "jpeg", "div_cam_blk_320", GATE_IP_CAM, 6, 0, 0),
 594        GATE(CLK_M2MSCALER, "m2mscaler", "div_cam_blk_320",
 595                GATE_IP_CAM, 2, 0, 0),
 596        GATE(CLK_GSCALER1, "gscaler1", "div_cam_blk_320", GATE_IP_CAM, 1, 0, 0),
 597        GATE(CLK_GSCALER0, "gscaler0", "div_cam_blk_320", GATE_IP_CAM, 0, 0, 0),
 598
 599        /* GATE_IP_MFC */
 600        GATE(CLK_QEMFC, "qemfc", "div_aclk_200", GATE_IP_MFC, 5,
 601                CLK_IGNORE_UNUSED, 0),
 602        GATE(CLK_PPMUMFC_L, "ppmumfc_l", "div_aclk_200", GATE_IP_MFC, 3,
 603                CLK_IGNORE_UNUSED, 0),
 604        GATE(CLK_SMMUMFC_L, "smmumfc_l", "div_aclk_200", GATE_IP_MFC, 1, 0, 0),
 605        GATE(CLK_MFC, "mfc", "div_aclk_200", GATE_IP_MFC, 0, 0, 0),
 606
 607        /* GATE_IP_G3D */
 608        GATE(CLK_SMMUG3D, "smmug3d", "div_aclk_200", GATE_IP_G3D, 3, 0, 0),
 609        GATE(CLK_QEG3D, "qeg3d", "div_aclk_200", GATE_IP_G3D, 2,
 610                CLK_IGNORE_UNUSED, 0),
 611        GATE(CLK_PPMUG3D, "ppmug3d", "div_aclk_200", GATE_IP_G3D, 1,
 612                CLK_IGNORE_UNUSED, 0),
 613        GATE(CLK_G3D, "g3d", "div_aclk_200", GATE_IP_G3D, 0, 0, 0),
 614
 615        /* GATE_IP_LCD */
 616        GATE(CLK_QE_CH1_LCD, "qe_ch1_lcd", "div_aclk_160", GATE_IP_LCD, 7,
 617                CLK_IGNORE_UNUSED, 0),
 618        GATE(CLK_QE_CH0_LCD, "qe_ch0_lcd", "div_aclk_160", GATE_IP_LCD, 6,
 619                CLK_IGNORE_UNUSED, 0),
 620        GATE(CLK_PPMULCD0, "ppmulcd0", "div_aclk_160", GATE_IP_LCD, 5,
 621                CLK_IGNORE_UNUSED, 0),
 622        GATE(CLK_SMMUFIMD0, "smmufimd0", "div_aclk_160", GATE_IP_LCD, 4, 0, 0),
 623        GATE(CLK_DSIM0, "dsim0", "div_aclk_160", GATE_IP_LCD, 3, 0, 0),
 624        GATE(CLK_SMIES, "smies", "div_aclk_160", GATE_IP_LCD, 2, 0, 0),
 625        GATE(CLK_FIMD0, "fimd0", "div_aclk_160", GATE_IP_LCD, 0, 0, 0),
 626
 627        /* GATE_IP_ISP */
 628        GATE(CLK_CAM1, "cam1", "mout_aclk_266_sub", GATE_IP_ISP, 5, 0, 0),
 629        GATE(CLK_UART_ISP_TOP, "uart_isp_top", "mout_aclk_266_sub",
 630                GATE_IP_ISP, 3, 0, 0),
 631        GATE(CLK_SPI1_ISP_TOP, "spi1_isp_top", "mout_aclk_266_sub",
 632                GATE_IP_ISP, 2, 0, 0),
 633        GATE(CLK_SPI0_ISP_TOP, "spi0_isp_top", "mout_aclk_266_sub",
 634                GATE_IP_ISP, 1, 0, 0),
 635
 636        /* GATE_IP_FSYS */
 637        GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0),
 638        GATE(CLK_PPMUFILE, "ppmufile", "div_aclk_200", GATE_IP_FSYS, 17,
 639                CLK_IGNORE_UNUSED, 0),
 640        GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
 641        GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
 642        GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
 643        GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
 644        GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
 645        GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
 646        GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
 647        GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0),
 648
 649        /* GATE_IP_PERIL */
 650        GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0),
 651        GATE(CLK_PCM, "pcm", "div_aclk_100", GATE_IP_PERIL, 23, 0, 0),
 652        GATE(CLK_I2S, "i2s", "div_aclk_100", GATE_IP_PERIL, 21, 0, 0),
 653        GATE(CLK_SPI1, "spi1", "div_aclk_100", GATE_IP_PERIL, 17, 0, 0),
 654        GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0),
 655        GATE(CLK_I2C7, "i2c7", "div_aclk_100", GATE_IP_PERIL, 13, 0, 0),
 656        GATE(CLK_I2C6, "i2c6", "div_aclk_100", GATE_IP_PERIL, 12, 0, 0),
 657        GATE(CLK_I2C5, "i2c5", "div_aclk_100", GATE_IP_PERIL, 11, 0, 0),
 658        GATE(CLK_I2C4, "i2c4", "div_aclk_100", GATE_IP_PERIL, 10, 0, 0),
 659        GATE(CLK_I2C3, "i2c3", "div_aclk_100", GATE_IP_PERIL, 9, 0, 0),
 660        GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
 661        GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
 662        GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
 663        GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
 664        GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
 665        GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
 666};
 667
 668/* APLL & MPLL & BPLL & UPLL */
 669static const struct samsung_pll_rate_table exynos3250_pll_rates[] __initconst = {
 670        PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
 671        PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
 672        PLL_35XX_RATE(24 * MHZ, 1066000000, 533, 6, 1),
 673        PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
 674        PLL_35XX_RATE(24 * MHZ,  960000000, 320, 4, 1),
 675        PLL_35XX_RATE(24 * MHZ,  900000000, 300, 4, 1),
 676        PLL_35XX_RATE(24 * MHZ,  850000000, 425, 6, 1),
 677        PLL_35XX_RATE(24 * MHZ,  800000000, 200, 3, 1),
 678        PLL_35XX_RATE(24 * MHZ,  700000000, 175, 3, 1),
 679        PLL_35XX_RATE(24 * MHZ,  667000000, 667, 12, 1),
 680        PLL_35XX_RATE(24 * MHZ,  600000000, 400, 4, 2),
 681        PLL_35XX_RATE(24 * MHZ,  533000000, 533, 6, 2),
 682        PLL_35XX_RATE(24 * MHZ,  520000000, 260, 3, 2),
 683        PLL_35XX_RATE(24 * MHZ,  500000000, 250, 3, 2),
 684        PLL_35XX_RATE(24 * MHZ,  400000000, 200, 3, 2),
 685        PLL_35XX_RATE(24 * MHZ,  200000000, 200, 3, 3),
 686        PLL_35XX_RATE(24 * MHZ,  100000000, 200, 3, 4),
 687        { /* sentinel */ }
 688};
 689
 690/* EPLL */
 691static const struct samsung_pll_rate_table exynos3250_epll_rates[] __initconst = {
 692        PLL_36XX_RATE(24 * MHZ, 800000000, 200, 3, 1,     0),
 693        PLL_36XX_RATE(24 * MHZ, 288000000,  96, 2, 2,     0),
 694        PLL_36XX_RATE(24 * MHZ, 192000000, 128, 2, 3,     0),
 695        PLL_36XX_RATE(24 * MHZ, 144000000,  96, 2, 3,     0),
 696        PLL_36XX_RATE(24 * MHZ,  96000000, 128, 2, 4,     0),
 697        PLL_36XX_RATE(24 * MHZ,  84000000, 112, 2, 4,     0),
 698        PLL_36XX_RATE(24 * MHZ,  80000003, 106, 2, 4, 43691),
 699        PLL_36XX_RATE(24 * MHZ,  73728000,  98, 2, 4, 19923),
 700        PLL_36XX_RATE(24 * MHZ,  67737598, 270, 3, 5, 62285),
 701        PLL_36XX_RATE(24 * MHZ,  65535999, 174, 2, 5, 49982),
 702        PLL_36XX_RATE(24 * MHZ,  50000000, 200, 3, 5,     0),
 703        PLL_36XX_RATE(24 * MHZ,  49152002, 131, 2, 5,  4719),
 704        PLL_36XX_RATE(24 * MHZ,  48000000, 128, 2, 5,     0),
 705        PLL_36XX_RATE(24 * MHZ,  45158401, 180, 3, 5, 41524),
 706        { /* sentinel */ }
 707};
 708
 709/* VPLL */
 710static const struct samsung_pll_rate_table exynos3250_vpll_rates[] __initconst = {
 711        PLL_36XX_RATE(24 * MHZ, 600000000, 100, 2, 1,     0),
 712        PLL_36XX_RATE(24 * MHZ, 533000000, 266, 3, 2, 32768),
 713        PLL_36XX_RATE(24 * MHZ, 519230987, 173, 2, 2,  5046),
 714        PLL_36XX_RATE(24 * MHZ, 500000000, 250, 3, 2,     0),
 715        PLL_36XX_RATE(24 * MHZ, 445500000, 148, 2, 2, 32768),
 716        PLL_36XX_RATE(24 * MHZ, 445055007, 148, 2, 2, 23047),
 717        PLL_36XX_RATE(24 * MHZ, 400000000, 200, 3, 2,     0),
 718        PLL_36XX_RATE(24 * MHZ, 371250000, 123, 2, 2, 49152),
 719        PLL_36XX_RATE(24 * MHZ, 370878997, 185, 3, 2, 28803),
 720        PLL_36XX_RATE(24 * MHZ, 340000000, 170, 3, 2,     0),
 721        PLL_36XX_RATE(24 * MHZ, 335000015, 111, 2, 2, 43691),
 722        PLL_36XX_RATE(24 * MHZ, 333000000, 111, 2, 2,     0),
 723        PLL_36XX_RATE(24 * MHZ, 330000000, 110, 2, 2,     0),
 724        PLL_36XX_RATE(24 * MHZ, 320000015, 106, 2, 2, 43691),
 725        PLL_36XX_RATE(24 * MHZ, 300000000, 100, 2, 2,     0),
 726        PLL_36XX_RATE(24 * MHZ, 275000000, 275, 3, 3,     0),
 727        PLL_36XX_RATE(24 * MHZ, 222750000, 148, 2, 3, 32768),
 728        PLL_36XX_RATE(24 * MHZ, 222528007, 148, 2, 3, 23069),
 729        PLL_36XX_RATE(24 * MHZ, 160000000, 160, 3, 3,     0),
 730        PLL_36XX_RATE(24 * MHZ, 148500000,  99, 2, 3,     0),
 731        PLL_36XX_RATE(24 * MHZ, 148352005,  98, 2, 3, 59070),
 732        PLL_36XX_RATE(24 * MHZ, 108000000, 144, 2, 4,     0),
 733        PLL_36XX_RATE(24 * MHZ,  74250000,  99, 2, 4,     0),
 734        PLL_36XX_RATE(24 * MHZ,  74176002,  98, 2, 4, 59070),
 735        PLL_36XX_RATE(24 * MHZ,  54054000, 216, 3, 5, 14156),
 736        PLL_36XX_RATE(24 * MHZ,  54000000, 144, 2, 5,     0),
 737        { /* sentinel */ }
 738};
 739
 740static const struct samsung_pll_clock exynos3250_plls[] __initconst = {
 741        PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
 742                APLL_LOCK, APLL_CON0, exynos3250_pll_rates),
 743        PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
 744                        MPLL_LOCK, MPLL_CON0, exynos3250_pll_rates),
 745        PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
 746                        VPLL_LOCK, VPLL_CON0, exynos3250_vpll_rates),
 747        PLL(pll_35xx, CLK_FOUT_UPLL, "fout_upll", "fin_pll",
 748                        UPLL_LOCK, UPLL_CON0, exynos3250_pll_rates),
 749};
 750
 751static void __init exynos3_core_down_clock(void __iomem *reg_base)
 752{
 753        unsigned int tmp;
 754
 755        /*
 756         * Enable arm clock down (in idle) and set arm divider
 757         * ratios in WFI/WFE state.
 758         */
 759        tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) |
 760                PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
 761                PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
 762                PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
 763        __raw_writel(tmp, reg_base + PWR_CTRL1);
 764
 765        /*
 766         * Disable the clock up feature on Exynos4x12, in case it was
 767         * enabled by bootloader.
 768         */
 769        __raw_writel(0x0, reg_base + PWR_CTRL2);
 770}
 771
 772static const struct samsung_cmu_info cmu_info __initconst = {
 773        .pll_clks               = exynos3250_plls,
 774        .nr_pll_clks            = ARRAY_SIZE(exynos3250_plls),
 775        .mux_clks               = mux_clks,
 776        .nr_mux_clks            = ARRAY_SIZE(mux_clks),
 777        .div_clks               = div_clks,
 778        .nr_div_clks            = ARRAY_SIZE(div_clks),
 779        .gate_clks              = gate_clks,
 780        .nr_gate_clks           = ARRAY_SIZE(gate_clks),
 781        .fixed_factor_clks      = fixed_factor_clks,
 782        .nr_fixed_factor_clks   = ARRAY_SIZE(fixed_factor_clks),
 783        .nr_clk_ids             = CLK_NR_CLKS,
 784        .clk_regs               = exynos3250_cmu_clk_regs,
 785        .nr_clk_regs            = ARRAY_SIZE(exynos3250_cmu_clk_regs),
 786};
 787
 788#define E3250_CPU_DIV0(apll, pclk_dbg, atb, corem)                      \
 789                (((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) |  \
 790                ((corem) << 4))
 791#define E3250_CPU_DIV1(hpm, copy)                                       \
 792                (((hpm) << 4) | ((copy) << 0))
 793
 794static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = {
 795        { 1000000, E3250_CPU_DIV0(1, 7, 4, 1), E3250_CPU_DIV1(7, 7), },
 796        {  900000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
 797        {  800000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
 798        {  700000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
 799        {  600000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
 800        {  500000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
 801        {  400000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
 802        {  300000, E3250_CPU_DIV0(1, 5, 3, 1), E3250_CPU_DIV1(7, 7), },
 803        {  200000, E3250_CPU_DIV0(1, 3, 3, 1), E3250_CPU_DIV1(7, 7), },
 804        {  100000, E3250_CPU_DIV0(1, 1, 1, 1), E3250_CPU_DIV1(7, 7), },
 805        {  0 },
 806};
 807
 808static void __init exynos3250_cmu_init(struct device_node *np)
 809{
 810        struct samsung_clk_provider *ctx;
 811        struct clk_hw **hws;
 812
 813        ctx = samsung_cmu_register_one(np, &cmu_info);
 814        if (!ctx)
 815                return;
 816
 817        hws = ctx->clk_data.hws;
 818        exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
 819                        hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL_USER_C],
 820                        0x14200, e3250_armclk_d, ARRAY_SIZE(e3250_armclk_d),
 821                        CLK_CPU_HAS_DIV1);
 822
 823        exynos3_core_down_clock(ctx->reg_base);
 824}
 825CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
 826
 827/*
 828 * CMU DMC
 829 */
 830
 831#define BPLL_LOCK               0x0118
 832#define BPLL_CON0               0x0218
 833#define BPLL_CON1               0x021c
 834#define BPLL_CON2               0x0220
 835#define SRC_DMC                 0x0300
 836#define DIV_DMC1                0x0504
 837#define GATE_BUS_DMC0           0x0700
 838#define GATE_BUS_DMC1           0x0704
 839#define GATE_BUS_DMC2           0x0708
 840#define GATE_BUS_DMC3           0x070c
 841#define GATE_SCLK_DMC           0x0800
 842#define GATE_IP_DMC0            0x0900
 843#define GATE_IP_DMC1            0x0904
 844#define EPLL_LOCK               0x1110
 845#define EPLL_CON0               0x1114
 846#define EPLL_CON1               0x1118
 847#define EPLL_CON2               0x111c
 848#define SRC_EPLL                0x1120
 849
 850static const unsigned long exynos3250_cmu_dmc_clk_regs[] __initconst = {
 851        BPLL_LOCK,
 852        BPLL_CON0,
 853        BPLL_CON1,
 854        BPLL_CON2,
 855        SRC_DMC,
 856        DIV_DMC1,
 857        GATE_BUS_DMC0,
 858        GATE_BUS_DMC1,
 859        GATE_BUS_DMC2,
 860        GATE_BUS_DMC3,
 861        GATE_SCLK_DMC,
 862        GATE_IP_DMC0,
 863        GATE_IP_DMC1,
 864        EPLL_LOCK,
 865        EPLL_CON0,
 866        EPLL_CON1,
 867        EPLL_CON2,
 868        SRC_EPLL,
 869};
 870
 871PNAME(mout_epll_p)      = { "fin_pll", "fout_epll", };
 872PNAME(mout_bpll_p)      = { "fin_pll", "fout_bpll", };
 873PNAME(mout_mpll_mif_p)  = { "fin_pll", "sclk_mpll_mif", };
 874PNAME(mout_dphy_p)      = { "mout_mpll_mif", "mout_bpll", };
 875
 876static const struct samsung_mux_clock dmc_mux_clks[] __initconst = {
 877        /*
 878         * NOTE: Following table is sorted by register address in ascending
 879         * order and then bitfield shift in descending order, as it is done
 880         * in the User's Manual. When adding new entries, please make sure
 881         * that the order is preserved, to avoid merge conflicts and make
 882         * further work with defined data easier.
 883         */
 884
 885        /* SRC_DMC */
 886        MUX(CLK_MOUT_MPLL_MIF, "mout_mpll_mif", mout_mpll_mif_p, SRC_DMC, 12, 1),
 887        MUX(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_DMC, 10, 1),
 888        MUX(CLK_MOUT_DPHY, "mout_dphy", mout_dphy_p, SRC_DMC, 8, 1),
 889        MUX(CLK_MOUT_DMC_BUS, "mout_dmc_bus", mout_dphy_p, SRC_DMC,  4, 1),
 890
 891        /* SRC_EPLL */
 892        MUX(CLK_MOUT_EPLL, "mout_epll", mout_epll_p, SRC_EPLL, 4, 1),
 893};
 894
 895static const struct samsung_div_clock dmc_div_clks[] __initconst = {
 896        /*
 897         * NOTE: Following table is sorted by register address in ascending
 898         * order and then bitfield shift in descending order, as it is done
 899         * in the User's Manual. When adding new entries, please make sure
 900         * that the order is preserved, to avoid merge conflicts and make
 901         * further work with defined data easier.
 902         */
 903
 904        /* DIV_DMC1 */
 905        DIV(CLK_DIV_DMC, "div_dmc", "div_dmc_pre", DIV_DMC1, 27, 3),
 906        DIV(CLK_DIV_DPHY, "div_dphy", "mout_dphy", DIV_DMC1, 23, 3),
 907        DIV(CLK_DIV_DMC_PRE, "div_dmc_pre", "mout_dmc_bus", DIV_DMC1, 19, 2),
 908        DIV(CLK_DIV_DMCP, "div_dmcp", "div_dmcd", DIV_DMC1, 15, 3),
 909        DIV(CLK_DIV_DMCD, "div_dmcd", "div_dmc", DIV_DMC1, 11, 3),
 910};
 911
 912static const struct samsung_pll_clock exynos3250_dmc_plls[] __initconst = {
 913        PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll",
 914                BPLL_LOCK, BPLL_CON0, exynos3250_pll_rates),
 915        PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
 916                EPLL_LOCK, EPLL_CON0, exynos3250_epll_rates),
 917};
 918
 919static const struct samsung_cmu_info dmc_cmu_info __initconst = {
 920        .pll_clks               = exynos3250_dmc_plls,
 921        .nr_pll_clks            = ARRAY_SIZE(exynos3250_dmc_plls),
 922        .mux_clks               = dmc_mux_clks,
 923        .nr_mux_clks            = ARRAY_SIZE(dmc_mux_clks),
 924        .div_clks               = dmc_div_clks,
 925        .nr_div_clks            = ARRAY_SIZE(dmc_div_clks),
 926        .nr_clk_ids             = NR_CLKS_DMC,
 927        .clk_regs               = exynos3250_cmu_dmc_clk_regs,
 928        .nr_clk_regs            = ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs),
 929};
 930
 931static void __init exynos3250_cmu_dmc_init(struct device_node *np)
 932{
 933        samsung_cmu_register_one(np, &dmc_cmu_info);
 934}
 935CLK_OF_DECLARE(exynos3250_cmu_dmc, "samsung,exynos3250-cmu-dmc",
 936                exynos3250_cmu_dmc_init);
 937
 938
 939/*
 940 * CMU ISP
 941 */
 942
 943#define DIV_ISP0                0x300
 944#define DIV_ISP1                0x304
 945#define GATE_IP_ISP0            0x800
 946#define GATE_IP_ISP1            0x804
 947#define GATE_SCLK_ISP           0x900
 948
 949static const struct samsung_div_clock isp_div_clks[] __initconst = {
 950        /*
 951         * NOTE: Following table is sorted by register address in ascending
 952         * order and then bitfield shift in descending order, as it is done
 953         * in the User's Manual. When adding new entries, please make sure
 954         * that the order is preserved, to avoid merge conflicts and make
 955         * further work with defined data easier.
 956         */
 957        /* DIV_ISP0 */
 958        DIV(CLK_DIV_ISP1, "div_isp1", "mout_aclk_266_sub", DIV_ISP0, 4, 3),
 959        DIV(CLK_DIV_ISP0, "div_isp0", "mout_aclk_266_sub", DIV_ISP0, 0, 3),
 960
 961        /* DIV_ISP1 */
 962        DIV(CLK_DIV_MCUISP1, "div_mcuisp1", "mout_aclk_400_mcuisp_sub",
 963                DIV_ISP1, 8, 3),
 964        DIV(CLK_DIV_MCUISP0, "div_mcuisp0", "mout_aclk_400_mcuisp_sub",
 965                DIV_ISP1, 4, 3),
 966        DIV(CLK_DIV_MPWM, "div_mpwm", "div_isp1", DIV_ISP1, 0, 3),
 967};
 968
 969static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
 970        /*
 971         * NOTE: Following table is sorted by register address in ascending
 972         * order and then bitfield shift in descending order, as it is done
 973         * in the User's Manual. When adding new entries, please make sure
 974         * that the order is preserved, to avoid merge conflicts and make
 975         * further work with defined data easier.
 976         */
 977
 978        /* GATE_IP_ISP0 */
 979        GATE(CLK_UART_ISP, "uart_isp", "uart_isp_top",
 980                GATE_IP_ISP0, 31, CLK_IGNORE_UNUSED, 0),
 981        GATE(CLK_WDT_ISP, "wdt_isp", "mout_aclk_266_sub",
 982                GATE_IP_ISP0, 30, CLK_IGNORE_UNUSED, 0),
 983        GATE(CLK_PWM_ISP, "pwm_isp", "mout_aclk_266_sub",
 984                GATE_IP_ISP0, 28, CLK_IGNORE_UNUSED, 0),
 985        GATE(CLK_I2C1_ISP, "i2c1_isp", "mout_aclk_266_sub",
 986                GATE_IP_ISP0, 26, CLK_IGNORE_UNUSED, 0),
 987        GATE(CLK_I2C0_ISP, "i2c0_isp", "mout_aclk_266_sub",
 988                GATE_IP_ISP0, 25, CLK_IGNORE_UNUSED, 0),
 989        GATE(CLK_MPWM_ISP, "mpwm_isp", "mout_aclk_266_sub",
 990                GATE_IP_ISP0, 24, CLK_IGNORE_UNUSED, 0),
 991        GATE(CLK_MCUCTL_ISP, "mcuctl_isp", "mout_aclk_266_sub",
 992                GATE_IP_ISP0, 23, CLK_IGNORE_UNUSED, 0),
 993        GATE(CLK_PPMUISPX, "ppmuispx", "mout_aclk_266_sub",
 994                GATE_IP_ISP0, 21, CLK_IGNORE_UNUSED, 0),
 995        GATE(CLK_PPMUISPMX, "ppmuispmx", "mout_aclk_266_sub",
 996                GATE_IP_ISP0, 20, CLK_IGNORE_UNUSED, 0),
 997        GATE(CLK_QE_LITE1, "qe_lite1", "mout_aclk_266_sub",
 998                GATE_IP_ISP0, 18, CLK_IGNORE_UNUSED, 0),
 999        GATE(CLK_QE_LITE0, "qe_lite0", "mout_aclk_266_sub",
1000                GATE_IP_ISP0, 17, CLK_IGNORE_UNUSED, 0),
1001        GATE(CLK_QE_FD, "qe_fd", "mout_aclk_266_sub",
1002                GATE_IP_ISP0, 16, CLK_IGNORE_UNUSED, 0),
1003        GATE(CLK_QE_DRC, "qe_drc", "mout_aclk_266_sub",
1004                GATE_IP_ISP0, 15, CLK_IGNORE_UNUSED, 0),
1005        GATE(CLK_QE_ISP, "qe_isp", "mout_aclk_266_sub",
1006                GATE_IP_ISP0, 14, CLK_IGNORE_UNUSED, 0),
1007        GATE(CLK_CSIS1, "csis1", "mout_aclk_266_sub",
1008                GATE_IP_ISP0, 13, CLK_IGNORE_UNUSED, 0),
1009        GATE(CLK_SMMU_LITE1, "smmu_lite1", "mout_aclk_266_sub",
1010                GATE_IP_ISP0, 12, CLK_IGNORE_UNUSED, 0),
1011        GATE(CLK_SMMU_LITE0, "smmu_lite0", "mout_aclk_266_sub",
1012                GATE_IP_ISP0, 11, CLK_IGNORE_UNUSED, 0),
1013        GATE(CLK_SMMU_FD, "smmu_fd", "mout_aclk_266_sub",
1014                GATE_IP_ISP0, 10, CLK_IGNORE_UNUSED, 0),
1015        GATE(CLK_SMMU_DRC, "smmu_drc", "mout_aclk_266_sub",
1016                GATE_IP_ISP0, 9, CLK_IGNORE_UNUSED, 0),
1017        GATE(CLK_SMMU_ISP, "smmu_isp", "mout_aclk_266_sub",
1018                GATE_IP_ISP0, 8, CLK_IGNORE_UNUSED, 0),
1019        GATE(CLK_GICISP, "gicisp", "mout_aclk_266_sub",
1020                GATE_IP_ISP0, 7, CLK_IGNORE_UNUSED, 0),
1021        GATE(CLK_CSIS0, "csis0", "mout_aclk_266_sub",
1022                GATE_IP_ISP0, 6, CLK_IGNORE_UNUSED, 0),
1023        GATE(CLK_MCUISP, "mcuisp", "mout_aclk_266_sub",
1024                GATE_IP_ISP0, 5, CLK_IGNORE_UNUSED, 0),
1025        GATE(CLK_LITE1, "lite1", "mout_aclk_266_sub",
1026                GATE_IP_ISP0, 4, CLK_IGNORE_UNUSED, 0),
1027        GATE(CLK_LITE0, "lite0", "mout_aclk_266_sub",
1028                GATE_IP_ISP0, 3, CLK_IGNORE_UNUSED, 0),
1029        GATE(CLK_FD, "fd", "mout_aclk_266_sub",
1030                GATE_IP_ISP0, 2, CLK_IGNORE_UNUSED, 0),
1031        GATE(CLK_DRC, "drc", "mout_aclk_266_sub",
1032                GATE_IP_ISP0, 1, CLK_IGNORE_UNUSED, 0),
1033        GATE(CLK_ISP, "isp", "mout_aclk_266_sub",
1034                GATE_IP_ISP0, 0, CLK_IGNORE_UNUSED, 0),
1035
1036        /* GATE_IP_ISP1 */
1037        GATE(CLK_QE_ISPCX, "qe_ispcx", "uart_isp_top",
1038                GATE_IP_ISP0, 21, CLK_IGNORE_UNUSED, 0),
1039        GATE(CLK_QE_SCALERP, "qe_scalerp", "uart_isp_top",
1040                GATE_IP_ISP0, 20, CLK_IGNORE_UNUSED, 0),
1041        GATE(CLK_QE_SCALERC, "qe_scalerc", "uart_isp_top",
1042                GATE_IP_ISP0, 19, CLK_IGNORE_UNUSED, 0),
1043        GATE(CLK_SMMU_SCALERP, "smmu_scalerp", "uart_isp_top",
1044                GATE_IP_ISP0, 18, CLK_IGNORE_UNUSED, 0),
1045        GATE(CLK_SMMU_SCALERC, "smmu_scalerc", "uart_isp_top",
1046                GATE_IP_ISP0, 17, CLK_IGNORE_UNUSED, 0),
1047        GATE(CLK_SCALERP, "scalerp", "uart_isp_top",
1048                GATE_IP_ISP0, 16, CLK_IGNORE_UNUSED, 0),
1049        GATE(CLK_SCALERC, "scalerc", "uart_isp_top",
1050                GATE_IP_ISP0, 15, CLK_IGNORE_UNUSED, 0),
1051        GATE(CLK_SPI1_ISP, "spi1_isp", "uart_isp_top",
1052                GATE_IP_ISP0, 13, CLK_IGNORE_UNUSED, 0),
1053        GATE(CLK_SPI0_ISP, "spi0_isp", "uart_isp_top",
1054                GATE_IP_ISP0, 12, CLK_IGNORE_UNUSED, 0),
1055        GATE(CLK_SMMU_ISPCX, "smmu_ispcx", "uart_isp_top",
1056                GATE_IP_ISP0, 4, CLK_IGNORE_UNUSED, 0),
1057        GATE(CLK_ASYNCAXIM, "asyncaxim", "uart_isp_top",
1058                GATE_IP_ISP0, 0, CLK_IGNORE_UNUSED, 0),
1059
1060        /* GATE_SCLK_ISP */
1061        GATE(CLK_SCLK_MPWM_ISP, "sclk_mpwm_isp", "div_mpwm",
1062                GATE_SCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
1063};
1064
1065static const struct samsung_cmu_info isp_cmu_info __initconst = {
1066        .div_clks       = isp_div_clks,
1067        .nr_div_clks    = ARRAY_SIZE(isp_div_clks),
1068        .gate_clks      = isp_gate_clks,
1069        .nr_gate_clks   = ARRAY_SIZE(isp_gate_clks),
1070        .nr_clk_ids     = NR_CLKS_ISP,
1071};
1072
1073static int __init exynos3250_cmu_isp_probe(struct platform_device *pdev)
1074{
1075        struct device_node *np = pdev->dev.of_node;
1076
1077        samsung_cmu_register_one(np, &isp_cmu_info);
1078        return 0;
1079}
1080
1081static const struct of_device_id exynos3250_cmu_isp_of_match[] __initconst = {
1082        { .compatible = "samsung,exynos3250-cmu-isp", },
1083        { /* sentinel */ }
1084};
1085
1086static struct platform_driver exynos3250_cmu_isp_driver __initdata = {
1087        .driver = {
1088                .name = "exynos3250-cmu-isp",
1089                .suppress_bind_attrs = true,
1090                .of_match_table = exynos3250_cmu_isp_of_match,
1091        },
1092};
1093
1094static int __init exynos3250_cmu_platform_init(void)
1095{
1096        return platform_driver_probe(&exynos3250_cmu_isp_driver,
1097                                        exynos3250_cmu_isp_probe);
1098}
1099subsys_initcall(exynos3250_cmu_platform_init);
1100
1101