linux/drivers/clk/ralink/clk-mt7621.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Mediatek MT7621 Clock Driver
   4 * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
   5 */
   6
   7#include <linux/bitfield.h>
   8#include <linux/bitops.h>
   9#include <linux/clk-provider.h>
  10#include <linux/clk.h>
  11#include <linux/mfd/syscon.h>
  12#include <linux/platform_device.h>
  13#include <linux/regmap.h>
  14#include <linux/slab.h>
  15#include <dt-bindings/clock/mt7621-clk.h>
  16
  17/* Configuration registers */
  18#define SYSC_REG_SYSTEM_CONFIG0         0x10
  19#define SYSC_REG_SYSTEM_CONFIG1         0x14
  20#define SYSC_REG_CLKCFG0                0x2c
  21#define SYSC_REG_CLKCFG1                0x30
  22#define SYSC_REG_CUR_CLK_STS            0x44
  23#define MEMC_REG_CPU_PLL                0x648
  24
  25#define XTAL_MODE_SEL_MASK              GENMASK(8, 6)
  26#define CPU_CLK_SEL_MASK                GENMASK(31, 30)
  27#define CUR_CPU_FDIV_MASK               GENMASK(12, 8)
  28#define CUR_CPU_FFRAC_MASK              GENMASK(4, 0)
  29#define CPU_PLL_PREDIV_MASK             GENMASK(13, 12)
  30#define CPU_PLL_FBDIV_MASK              GENMASK(10, 4)
  31
  32struct mt7621_clk_priv {
  33        struct regmap *sysc;
  34        struct regmap *memc;
  35};
  36
  37struct mt7621_clk {
  38        struct clk_hw hw;
  39        struct mt7621_clk_priv *priv;
  40};
  41
  42struct mt7621_fixed_clk {
  43        u8 idx;
  44        const char *name;
  45        const char *parent_name;
  46        unsigned long rate;
  47        struct clk_hw *hw;
  48};
  49
  50struct mt7621_gate {
  51        u8 idx;
  52        const char *name;
  53        const char *parent_name;
  54        struct mt7621_clk_priv *priv;
  55        u32 bit_idx;
  56        struct clk_hw hw;
  57};
  58
  59#define GATE(_id, _name, _pname, _shift)        \
  60        {                                       \
  61                .idx            = _id,          \
  62                .name           = _name,        \
  63                .parent_name    = _pname,       \
  64                .bit_idx        = _shift        \
  65        }
  66
  67static struct mt7621_gate mt7621_gates[] = {
  68        GATE(MT7621_CLK_HSDMA, "hsdma", "150m", BIT(5)),
  69        GATE(MT7621_CLK_FE, "fe", "250m", BIT(6)),
  70        GATE(MT7621_CLK_SP_DIVTX, "sp_divtx", "270m", BIT(7)),
  71        GATE(MT7621_CLK_TIMER, "timer", "50m", BIT(8)),
  72        GATE(MT7621_CLK_PCM, "pcm", "270m", BIT(11)),
  73        GATE(MT7621_CLK_PIO, "pio", "50m", BIT(13)),
  74        GATE(MT7621_CLK_GDMA, "gdma", "bus", BIT(14)),
  75        GATE(MT7621_CLK_NAND, "nand", "125m", BIT(15)),
  76        GATE(MT7621_CLK_I2C, "i2c", "50m", BIT(16)),
  77        GATE(MT7621_CLK_I2S, "i2s", "270m", BIT(17)),
  78        GATE(MT7621_CLK_SPI, "spi", "bus", BIT(18)),
  79        GATE(MT7621_CLK_UART1, "uart1", "50m", BIT(19)),
  80        GATE(MT7621_CLK_UART2, "uart2", "50m", BIT(20)),
  81        GATE(MT7621_CLK_UART3, "uart3", "50m", BIT(21)),
  82        GATE(MT7621_CLK_ETH, "eth", "50m", BIT(23)),
  83        GATE(MT7621_CLK_PCIE0, "pcie0", "125m", BIT(24)),
  84        GATE(MT7621_CLK_PCIE1, "pcie1", "125m", BIT(25)),
  85        GATE(MT7621_CLK_PCIE2, "pcie2", "125m", BIT(26)),
  86        GATE(MT7621_CLK_CRYPTO, "crypto", "250m", BIT(29)),
  87        GATE(MT7621_CLK_SHXC, "shxc", "50m", BIT(30))
  88};
  89
  90static inline struct mt7621_gate *to_mt7621_gate(struct clk_hw *hw)
  91{
  92        return container_of(hw, struct mt7621_gate, hw);
  93}
  94
  95static int mt7621_gate_enable(struct clk_hw *hw)
  96{
  97        struct mt7621_gate *clk_gate = to_mt7621_gate(hw);
  98        struct regmap *sysc = clk_gate->priv->sysc;
  99
 100        return regmap_update_bits(sysc, SYSC_REG_CLKCFG1,
 101                                  clk_gate->bit_idx, clk_gate->bit_idx);
 102}
 103
 104static void mt7621_gate_disable(struct clk_hw *hw)
 105{
 106        struct mt7621_gate *clk_gate = to_mt7621_gate(hw);
 107        struct regmap *sysc = clk_gate->priv->sysc;
 108
 109        regmap_update_bits(sysc, SYSC_REG_CLKCFG1, clk_gate->bit_idx, 0);
 110}
 111
 112static int mt7621_gate_is_enabled(struct clk_hw *hw)
 113{
 114        struct mt7621_gate *clk_gate = to_mt7621_gate(hw);
 115        struct regmap *sysc = clk_gate->priv->sysc;
 116        u32 val;
 117
 118        if (regmap_read(sysc, SYSC_REG_CLKCFG1, &val))
 119                return 0;
 120
 121        return val & BIT(clk_gate->bit_idx);
 122}
 123
 124static const struct clk_ops mt7621_gate_ops = {
 125        .enable = mt7621_gate_enable,
 126        .disable = mt7621_gate_disable,
 127        .is_enabled = mt7621_gate_is_enabled,
 128};
 129
 130static int mt7621_gate_ops_init(struct device *dev,
 131                                struct mt7621_gate *sclk)
 132{
 133        struct clk_init_data init = {
 134                /*
 135                 * Until now no clock driver existed so
 136                 * these SoC drivers are not prepared
 137                 * yet for the clock. We don't want kernel to
 138                 * disable anything so we add CLK_IS_CRITICAL
 139                 * flag here.
 140                 */
 141                .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
 142                .num_parents = 1,
 143                .parent_names = &sclk->parent_name,
 144                .ops = &mt7621_gate_ops,
 145                .name = sclk->name,
 146        };
 147
 148        sclk->hw.init = &init;
 149        return devm_clk_hw_register(dev, &sclk->hw);
 150}
 151
 152static int mt7621_register_gates(struct device *dev,
 153                                 struct clk_hw_onecell_data *clk_data,
 154                                 struct mt7621_clk_priv *priv)
 155{
 156        struct clk_hw **hws = clk_data->hws;
 157        struct mt7621_gate *sclk;
 158        int ret, i;
 159
 160        for (i = 0; i < ARRAY_SIZE(mt7621_gates); i++) {
 161                sclk = &mt7621_gates[i];
 162                sclk->priv = priv;
 163                ret = mt7621_gate_ops_init(dev, sclk);
 164                if (ret) {
 165                        dev_err(dev, "Couldn't register clock %s\n", sclk->name);
 166                        goto err_clk_unreg;
 167                }
 168
 169                hws[sclk->idx] = &sclk->hw;
 170        }
 171
 172        return 0;
 173
 174err_clk_unreg:
 175        while (--i >= 0) {
 176                sclk = &mt7621_gates[i];
 177                clk_hw_unregister(&sclk->hw);
 178        }
 179        return ret;
 180}
 181
 182#define FIXED(_id, _name, _rate)                \
 183        {                                       \
 184                .idx            = _id,          \
 185                .name           = _name,        \
 186                .parent_name    = "xtal",       \
 187                .rate           = _rate         \
 188        }
 189
 190static struct mt7621_fixed_clk mt7621_fixed_clks[] = {
 191        FIXED(MT7621_CLK_50M, "50m", 50000000),
 192        FIXED(MT7621_CLK_125M, "125m", 125000000),
 193        FIXED(MT7621_CLK_150M, "150m", 150000000),
 194        FIXED(MT7621_CLK_250M, "250m", 250000000),
 195        FIXED(MT7621_CLK_270M, "270m", 270000000),
 196};
 197
 198static int mt7621_register_fixed_clocks(struct device *dev,
 199                                        struct clk_hw_onecell_data *clk_data)
 200{
 201        struct clk_hw **hws = clk_data->hws;
 202        struct mt7621_fixed_clk *sclk;
 203        int ret, i;
 204
 205        for (i = 0; i < ARRAY_SIZE(mt7621_fixed_clks); i++) {
 206                sclk = &mt7621_fixed_clks[i];
 207                sclk->hw = clk_hw_register_fixed_rate(dev, sclk->name,
 208                                                      sclk->parent_name, 0,
 209                                                      sclk->rate);
 210                if (IS_ERR(sclk->hw)) {
 211                        dev_err(dev, "Couldn't register clock %s\n", sclk->name);
 212                        ret = PTR_ERR(sclk->hw);
 213                        goto err_clk_unreg;
 214                }
 215
 216                hws[sclk->idx] = sclk->hw;
 217        }
 218
 219        return 0;
 220
 221err_clk_unreg:
 222        while (--i >= 0) {
 223                sclk = &mt7621_fixed_clks[i];
 224                clk_hw_unregister_fixed_rate(sclk->hw);
 225        }
 226        return ret;
 227}
 228
 229static inline struct mt7621_clk *to_mt7621_clk(struct clk_hw *hw)
 230{
 231        return container_of(hw, struct mt7621_clk, hw);
 232}
 233
 234static unsigned long mt7621_xtal_recalc_rate(struct clk_hw *hw,
 235                                             unsigned long parent_rate)
 236{
 237        struct mt7621_clk *clk = to_mt7621_clk(hw);
 238        struct regmap *sysc = clk->priv->sysc;
 239        u32 val;
 240
 241        regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG0, &val);
 242        val = FIELD_GET(XTAL_MODE_SEL_MASK, val);
 243
 244        if (val <= 2)
 245                return 20000000;
 246        if (val <= 5)
 247                return 40000000;
 248
 249        return 25000000;
 250}
 251
 252static unsigned long mt7621_cpu_recalc_rate(struct clk_hw *hw,
 253                                            unsigned long xtal_clk)
 254{
 255        static const u32 prediv_tbl[] = { 0, 1, 2, 2 };
 256        struct mt7621_clk *clk = to_mt7621_clk(hw);
 257        struct regmap *sysc = clk->priv->sysc;
 258        struct regmap *memc = clk->priv->memc;
 259        u32 clkcfg, clk_sel, curclk, ffiv, ffrac;
 260        u32 pll, prediv, fbdiv;
 261        unsigned long cpu_clk;
 262
 263        regmap_read(sysc, SYSC_REG_CLKCFG0, &clkcfg);
 264        clk_sel = FIELD_GET(CPU_CLK_SEL_MASK, clkcfg);
 265
 266        regmap_read(sysc, SYSC_REG_CUR_CLK_STS, &curclk);
 267        ffiv = FIELD_GET(CUR_CPU_FDIV_MASK, curclk);
 268        ffrac = FIELD_GET(CUR_CPU_FFRAC_MASK, curclk);
 269
 270        switch (clk_sel) {
 271        case 0:
 272                cpu_clk = 500000000;
 273                break;
 274        case 1:
 275                regmap_read(memc, MEMC_REG_CPU_PLL, &pll);
 276                fbdiv = FIELD_GET(CPU_PLL_FBDIV_MASK, pll);
 277                prediv = FIELD_GET(CPU_PLL_PREDIV_MASK, pll);
 278                cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv];
 279                break;
 280        default:
 281                cpu_clk = xtal_clk;
 282        }
 283
 284        return cpu_clk / ffiv * ffrac;
 285}
 286
 287static unsigned long mt7621_bus_recalc_rate(struct clk_hw *hw,
 288                                            unsigned long parent_rate)
 289{
 290        return parent_rate / 4;
 291}
 292
 293#define CLK_BASE(_name, _parent, _recalc) {                             \
 294        .init = &(struct clk_init_data) {                               \
 295                .name = _name,                                          \
 296                .ops = &(const struct clk_ops) {                        \
 297                        .recalc_rate = _recalc,                         \
 298                },                                                      \
 299                .parent_data = &(const struct clk_parent_data) {        \
 300                        .name = _parent,                                \
 301                        .fw_name = _parent                              \
 302                },                                                      \
 303                .num_parents = _parent ? 1 : 0                          \
 304        },                                                              \
 305}
 306
 307static struct mt7621_clk mt7621_clks_base[] = {
 308        { CLK_BASE("xtal", NULL, mt7621_xtal_recalc_rate) },
 309        { CLK_BASE("cpu", "xtal", mt7621_cpu_recalc_rate) },
 310        { CLK_BASE("bus", "cpu", mt7621_bus_recalc_rate) },
 311};
 312
 313static struct clk_hw *mt7621_clk_early[MT7621_CLK_MAX];
 314
 315static int mt7621_register_early_clocks(struct device_node *np,
 316                                        struct clk_hw_onecell_data *clk_data,
 317                                        struct mt7621_clk_priv *priv)
 318{
 319        struct clk_hw **hws = clk_data->hws;
 320        struct mt7621_clk *sclk;
 321        int ret, i, j;
 322
 323        for (i = 0; i < ARRAY_SIZE(mt7621_clks_base); i++) {
 324                sclk = &mt7621_clks_base[i];
 325                sclk->priv = priv;
 326                ret = of_clk_hw_register(np, &sclk->hw);
 327                if (ret) {
 328                        pr_err("Couldn't register top clock %i\n", i);
 329                        goto err_clk_unreg;
 330                }
 331
 332                hws[i] = &sclk->hw;
 333                mt7621_clk_early[i] = &sclk->hw;
 334        }
 335
 336        for (j = i; j < MT7621_CLK_MAX; j++)
 337                mt7621_clk_early[j] = ERR_PTR(-EPROBE_DEFER);
 338
 339        return 0;
 340
 341err_clk_unreg:
 342        while (--i >= 0) {
 343                sclk = &mt7621_clks_base[i];
 344                clk_hw_unregister(&sclk->hw);
 345        }
 346        return ret;
 347}
 348
 349static void __init mt7621_clk_init(struct device_node *node)
 350{
 351        struct mt7621_clk_priv *priv;
 352        struct clk_hw_onecell_data *clk_data;
 353        int ret, i, count;
 354
 355        priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 356        if (!priv)
 357                return;
 358
 359        priv->sysc = syscon_node_to_regmap(node);
 360        if (IS_ERR(priv->sysc)) {
 361                pr_err("Could not get sysc syscon regmap\n");
 362                goto free_clk_priv;
 363        }
 364
 365        priv->memc = syscon_regmap_lookup_by_phandle(node, "ralink,memctl");
 366        if (IS_ERR(priv->memc)) {
 367                pr_err("Could not get memc syscon regmap\n");
 368                goto free_clk_priv;
 369        }
 370
 371        count = ARRAY_SIZE(mt7621_clks_base) +
 372                ARRAY_SIZE(mt7621_fixed_clks) + ARRAY_SIZE(mt7621_gates);
 373        clk_data = kzalloc(struct_size(clk_data, hws, count), GFP_KERNEL);
 374        if (!clk_data)
 375                goto free_clk_priv;
 376
 377        ret = mt7621_register_early_clocks(node, clk_data, priv);
 378        if (ret) {
 379                pr_err("Couldn't register top clocks\n");
 380                goto free_clk_data;
 381        }
 382
 383        clk_data->num = count;
 384
 385        ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 386        if (ret) {
 387                pr_err("Couldn't add clk hw provider\n");
 388                goto unreg_clk_top;
 389        }
 390
 391        return;
 392
 393unreg_clk_top:
 394        for (i = 0; i < ARRAY_SIZE(mt7621_clks_base); i++) {
 395                struct mt7621_clk *sclk = &mt7621_clks_base[i];
 396
 397                clk_hw_unregister(&sclk->hw);
 398        }
 399
 400free_clk_data:
 401        kfree(clk_data);
 402
 403free_clk_priv:
 404        kfree(priv);
 405}
 406CLK_OF_DECLARE_DRIVER(mt7621_clk, "mediatek,mt7621-sysc", mt7621_clk_init);
 407
 408static int mt7621_clk_probe(struct platform_device *pdev)
 409{
 410        struct device_node *np = pdev->dev.of_node;
 411        struct clk_hw_onecell_data *clk_data;
 412        struct device *dev = &pdev->dev;
 413        struct mt7621_clk_priv *priv;
 414        int ret, i, count;
 415
 416        priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 417        if (!priv)
 418                return -ENOMEM;
 419
 420        priv->sysc = syscon_node_to_regmap(np);
 421        if (IS_ERR(priv->sysc)) {
 422                ret = PTR_ERR(priv->sysc);
 423                dev_err(dev, "Could not get sysc syscon regmap\n");
 424                return ret;
 425        }
 426
 427        priv->memc = syscon_regmap_lookup_by_phandle(np, "ralink,memctl");
 428        if (IS_ERR(priv->memc)) {
 429                ret = PTR_ERR(priv->memc);
 430                dev_err(dev, "Could not get memc syscon regmap\n");
 431                return ret;
 432        }
 433
 434        count = ARRAY_SIZE(mt7621_clks_base) +
 435                ARRAY_SIZE(mt7621_fixed_clks) + ARRAY_SIZE(mt7621_gates);
 436        clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count),
 437                                GFP_KERNEL);
 438        if (!clk_data)
 439                return -ENOMEM;
 440
 441        for (i = 0; i < ARRAY_SIZE(mt7621_clks_base); i++)
 442                clk_data->hws[i] = mt7621_clk_early[i];
 443
 444        ret = mt7621_register_fixed_clocks(dev, clk_data);
 445        if (ret) {
 446                dev_err(dev, "Couldn't register fixed clocks\n");
 447                return ret;
 448        }
 449
 450        ret = mt7621_register_gates(dev, clk_data, priv);
 451        if (ret) {
 452                dev_err(dev, "Couldn't register fixed clock gates\n");
 453                goto unreg_clk_fixed;
 454        }
 455
 456        clk_data->num = count;
 457
 458        ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
 459        if (ret) {
 460                dev_err(dev, "Couldn't add clk hw provider\n");
 461                goto unreg_clk_gates;
 462        }
 463
 464        return 0;
 465
 466unreg_clk_gates:
 467        for (i = 0; i < ARRAY_SIZE(mt7621_gates); i++) {
 468                struct mt7621_gate *sclk = &mt7621_gates[i];
 469
 470                clk_hw_unregister(&sclk->hw);
 471        }
 472
 473unreg_clk_fixed:
 474        for (i = 0; i < ARRAY_SIZE(mt7621_fixed_clks); i++) {
 475                struct mt7621_fixed_clk *sclk = &mt7621_fixed_clks[i];
 476
 477                clk_hw_unregister_fixed_rate(sclk->hw);
 478        }
 479
 480        return ret;
 481}
 482
 483static const struct of_device_id mt7621_clk_of_match[] = {
 484        { .compatible = "mediatek,mt7621-sysc" },
 485        {}
 486};
 487
 488static struct platform_driver mt7621_clk_driver = {
 489        .probe = mt7621_clk_probe,
 490        .driver = {
 491                .name = "mt7621-clk",
 492                .of_match_table = mt7621_clk_of_match,
 493        },
 494};
 495builtin_platform_driver(mt7621_clk_driver);
 496