linux/drivers/clk/meson/gxbb-aoclk.c
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   1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
   2/*
   3 * Copyright (c) 2016 BayLibre, SAS.
   4 * Author: Neil Armstrong <narmstrong@baylibre.com>
   5 */
   6#include <linux/platform_device.h>
   7#include <linux/mfd/syscon.h>
   8#include <linux/module.h>
   9#include "meson-aoclk.h"
  10#include "gxbb-aoclk.h"
  11
  12#include "clk-regmap.h"
  13#include "clk-dualdiv.h"
  14
  15/* AO Configuration Clock registers offsets */
  16#define AO_RTI_PWR_CNTL_REG1    0x0c
  17#define AO_RTI_PWR_CNTL_REG0    0x10
  18#define AO_RTI_GEN_CNTL_REG0    0x40
  19#define AO_OSCIN_CNTL           0x58
  20#define AO_CRT_CLK_CNTL1        0x68
  21#define AO_RTC_ALT_CLK_CNTL0    0x94
  22#define AO_RTC_ALT_CLK_CNTL1    0x98
  23
  24#define GXBB_AO_GATE(_name, _bit)                                       \
  25static struct clk_regmap _name##_ao = {                                 \
  26        .data = &(struct clk_regmap_gate_data) {                        \
  27                .offset = AO_RTI_GEN_CNTL_REG0,                         \
  28                .bit_idx = (_bit),                                      \
  29        },                                                              \
  30        .hw.init = &(struct clk_init_data) {                            \
  31                .name = #_name "_ao",                                   \
  32                .ops = &clk_regmap_gate_ops,                            \
  33                .parent_data = &(const struct clk_parent_data) {        \
  34                        .fw_name = "mpeg-clk",                          \
  35                },                                                      \
  36                .num_parents = 1,                                       \
  37                .flags = CLK_IGNORE_UNUSED,                             \
  38        },                                                              \
  39}
  40
  41GXBB_AO_GATE(remote, 0);
  42GXBB_AO_GATE(i2c_master, 1);
  43GXBB_AO_GATE(i2c_slave, 2);
  44GXBB_AO_GATE(uart1, 3);
  45GXBB_AO_GATE(uart2, 5);
  46GXBB_AO_GATE(ir_blaster, 6);
  47
  48static struct clk_regmap ao_cts_oscin = {
  49        .data = &(struct clk_regmap_gate_data){
  50                .offset = AO_RTI_PWR_CNTL_REG0,
  51                .bit_idx = 6,
  52        },
  53        .hw.init = &(struct clk_init_data){
  54                .name = "ao_cts_oscin",
  55                .ops = &clk_regmap_gate_ro_ops,
  56                .parent_data = &(const struct clk_parent_data) {
  57                        .fw_name = "xtal",
  58                },
  59                .num_parents = 1,
  60        },
  61};
  62
  63static struct clk_regmap ao_32k_pre = {
  64        .data = &(struct clk_regmap_gate_data){
  65                .offset = AO_RTC_ALT_CLK_CNTL0,
  66                .bit_idx = 31,
  67        },
  68        .hw.init = &(struct clk_init_data){
  69                .name = "ao_32k_pre",
  70                .ops = &clk_regmap_gate_ops,
  71                .parent_hws = (const struct clk_hw *[]) { &ao_cts_oscin.hw },
  72                .num_parents = 1,
  73        },
  74};
  75
  76static const struct meson_clk_dualdiv_param gxbb_32k_div_table[] = {
  77        {
  78                .dual   = 1,
  79                .n1     = 733,
  80                .m1     = 8,
  81                .n2     = 732,
  82                .m2     = 11,
  83        }, {}
  84};
  85
  86static struct clk_regmap ao_32k_div = {
  87        .data = &(struct meson_clk_dualdiv_data){
  88                .n1 = {
  89                        .reg_off = AO_RTC_ALT_CLK_CNTL0,
  90                        .shift   = 0,
  91                        .width   = 12,
  92                },
  93                .n2 = {
  94                        .reg_off = AO_RTC_ALT_CLK_CNTL0,
  95                        .shift   = 12,
  96                        .width   = 12,
  97                },
  98                .m1 = {
  99                        .reg_off = AO_RTC_ALT_CLK_CNTL1,
 100                        .shift   = 0,
 101                        .width   = 12,
 102                },
 103                .m2 = {
 104                        .reg_off = AO_RTC_ALT_CLK_CNTL1,
 105                        .shift   = 12,
 106                        .width   = 12,
 107                },
 108                .dual = {
 109                        .reg_off = AO_RTC_ALT_CLK_CNTL0,
 110                        .shift   = 28,
 111                        .width   = 1,
 112                },
 113                .table = gxbb_32k_div_table,
 114        },
 115        .hw.init = &(struct clk_init_data){
 116                .name = "ao_32k_div",
 117                .ops = &meson_clk_dualdiv_ops,
 118                .parent_hws = (const struct clk_hw *[]) { &ao_32k_pre.hw },
 119                .num_parents = 1,
 120        },
 121};
 122
 123static struct clk_regmap ao_32k_sel = {
 124        .data = &(struct clk_regmap_mux_data) {
 125                .offset = AO_RTC_ALT_CLK_CNTL1,
 126                .mask = 0x1,
 127                .shift = 24,
 128                .flags = CLK_MUX_ROUND_CLOSEST,
 129        },
 130        .hw.init = &(struct clk_init_data){
 131                .name = "ao_32k_sel",
 132                .ops = &clk_regmap_mux_ops,
 133                .parent_hws = (const struct clk_hw *[]) {
 134                        &ao_32k_div.hw,
 135                        &ao_32k_pre.hw
 136                },
 137                .num_parents = 2,
 138                .flags = CLK_SET_RATE_PARENT,
 139        },
 140};
 141
 142static struct clk_regmap ao_32k = {
 143        .data = &(struct clk_regmap_gate_data){
 144                .offset = AO_RTC_ALT_CLK_CNTL0,
 145                .bit_idx = 30,
 146        },
 147        .hw.init = &(struct clk_init_data){
 148                .name = "ao_32k",
 149                .ops = &clk_regmap_gate_ops,
 150                .parent_hws = (const struct clk_hw *[]) { &ao_32k_sel.hw },
 151                .num_parents = 1,
 152                .flags = CLK_SET_RATE_PARENT,
 153        },
 154};
 155
 156static struct clk_regmap ao_cts_rtc_oscin = {
 157        .data = &(struct clk_regmap_mux_data) {
 158                .offset = AO_RTI_PWR_CNTL_REG0,
 159                .mask = 0x7,
 160                .shift = 10,
 161                .table = (u32[]){ 1, 2, 3, 4 },
 162                .flags = CLK_MUX_ROUND_CLOSEST,
 163        },
 164        .hw.init = &(struct clk_init_data){
 165                .name = "ao_cts_rtc_oscin",
 166                .ops = &clk_regmap_mux_ops,
 167                .parent_data = (const struct clk_parent_data []) {
 168                        { .fw_name = "ext-32k-0", },
 169                        { .fw_name = "ext-32k-1", },
 170                        { .fw_name = "ext-32k-2", },
 171                        { .hw = &ao_32k.hw },
 172                },
 173                .num_parents = 4,
 174                .flags = CLK_SET_RATE_PARENT,
 175        },
 176};
 177
 178static struct clk_regmap ao_clk81 = {
 179        .data = &(struct clk_regmap_mux_data) {
 180                .offset = AO_RTI_PWR_CNTL_REG0,
 181                .mask = 0x1,
 182                .shift = 0,
 183                .flags = CLK_MUX_ROUND_CLOSEST,
 184        },
 185        .hw.init = &(struct clk_init_data){
 186                .name = "ao_clk81",
 187                .ops = &clk_regmap_mux_ro_ops,
 188                .parent_data = (const struct clk_parent_data []) {
 189                        { .fw_name = "mpeg-clk", },
 190                        { .hw = &ao_cts_rtc_oscin.hw },
 191                },
 192                .num_parents = 2,
 193                .flags = CLK_SET_RATE_PARENT,
 194        },
 195};
 196
 197static struct clk_regmap ao_cts_cec = {
 198        .data = &(struct clk_regmap_mux_data) {
 199                .offset = AO_CRT_CLK_CNTL1,
 200                .mask = 0x1,
 201                .shift = 27,
 202                .flags = CLK_MUX_ROUND_CLOSEST,
 203        },
 204        .hw.init = &(struct clk_init_data){
 205                .name = "ao_cts_cec",
 206                .ops = &clk_regmap_mux_ops,
 207                /*
 208                 * FIXME: The 'fixme' parent obviously does not exist.
 209                 *
 210                 * ATM, CCF won't call get_parent() if num_parents is 1. It
 211                 * does not allow NULL as a parent name either.
 212                 *
 213                 * On this particular mux, we only know the input #1 parent
 214                 * but, on boot, unknown input #0 is set, so it is critical
 215                 * to call .get_parent() on it
 216                 *
 217                 * Until CCF gets fixed, adding this fake parent that won't
 218                 * ever be registered should work around the problem
 219                 */
 220                .parent_data = (const struct clk_parent_data []) {
 221                        { .name = "fixme", .index = -1, },
 222                        { .hw = &ao_cts_rtc_oscin.hw },
 223                },
 224                .num_parents = 2,
 225                .flags = CLK_SET_RATE_PARENT,
 226        },
 227};
 228
 229static const unsigned int gxbb_aoclk_reset[] = {
 230        [RESET_AO_REMOTE] = 16,
 231        [RESET_AO_I2C_MASTER] = 18,
 232        [RESET_AO_I2C_SLAVE] = 19,
 233        [RESET_AO_UART1] = 17,
 234        [RESET_AO_UART2] = 22,
 235        [RESET_AO_IR_BLASTER] = 23,
 236};
 237
 238static struct clk_regmap *gxbb_aoclk[] = {
 239        &remote_ao,
 240        &i2c_master_ao,
 241        &i2c_slave_ao,
 242        &uart1_ao,
 243        &uart2_ao,
 244        &ir_blaster_ao,
 245        &ao_cts_oscin,
 246        &ao_32k_pre,
 247        &ao_32k_div,
 248        &ao_32k_sel,
 249        &ao_32k,
 250        &ao_cts_rtc_oscin,
 251        &ao_clk81,
 252        &ao_cts_cec,
 253};
 254
 255static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
 256        .hws = {
 257                [CLKID_AO_REMOTE] = &remote_ao.hw,
 258                [CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
 259                [CLKID_AO_I2C_SLAVE] = &i2c_slave_ao.hw,
 260                [CLKID_AO_UART1] = &uart1_ao.hw,
 261                [CLKID_AO_UART2] = &uart2_ao.hw,
 262                [CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw,
 263                [CLKID_AO_CEC_32K] = &ao_cts_cec.hw,
 264                [CLKID_AO_CTS_OSCIN] = &ao_cts_oscin.hw,
 265                [CLKID_AO_32K_PRE] = &ao_32k_pre.hw,
 266                [CLKID_AO_32K_DIV] = &ao_32k_div.hw,
 267                [CLKID_AO_32K_SEL] = &ao_32k_sel.hw,
 268                [CLKID_AO_32K] = &ao_32k.hw,
 269                [CLKID_AO_CTS_RTC_OSCIN] = &ao_cts_rtc_oscin.hw,
 270                [CLKID_AO_CLK81] = &ao_clk81.hw,
 271        },
 272        .num = NR_CLKS,
 273};
 274
 275static const struct meson_aoclk_data gxbb_aoclkc_data = {
 276        .reset_reg      = AO_RTI_GEN_CNTL_REG0,
 277        .num_reset      = ARRAY_SIZE(gxbb_aoclk_reset),
 278        .reset          = gxbb_aoclk_reset,
 279        .num_clks       = ARRAY_SIZE(gxbb_aoclk),
 280        .clks           = gxbb_aoclk,
 281        .hw_data        = &gxbb_aoclk_onecell_data,
 282};
 283
 284static const struct of_device_id gxbb_aoclkc_match_table[] = {
 285        {
 286                .compatible     = "amlogic,meson-gx-aoclkc",
 287                .data           = &gxbb_aoclkc_data,
 288        },
 289        { }
 290};
 291MODULE_DEVICE_TABLE(of, gxbb_aoclkc_match_table);
 292
 293static struct platform_driver gxbb_aoclkc_driver = {
 294        .probe          = meson_aoclkc_probe,
 295        .driver         = {
 296                .name   = "gxbb-aoclkc",
 297                .of_match_table = gxbb_aoclkc_match_table,
 298        },
 299};
 300module_platform_driver(gxbb_aoclkc_driver);
 301MODULE_LICENSE("GPL v2");
 302