linux/drivers/clk/clk-stm32mp1.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
   4 * Author: Olivier Bideau <olivier.bideau@st.com> for STMicroelectronics.
   5 * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
   6 */
   7
   8#include <linux/clk.h>
   9#include <linux/clk-provider.h>
  10#include <linux/delay.h>
  11#include <linux/err.h>
  12#include <linux/io.h>
  13#include <linux/module.h>
  14#include <linux/of.h>
  15#include <linux/of_address.h>
  16#include <linux/platform_device.h>
  17#include <linux/reset-controller.h>
  18#include <linux/slab.h>
  19#include <linux/spinlock.h>
  20
  21#include <dt-bindings/clock/stm32mp1-clks.h>
  22
  23static DEFINE_SPINLOCK(rlock);
  24
  25#define RCC_OCENSETR            0x0C
  26#define RCC_HSICFGR             0x18
  27#define RCC_RDLSICR             0x144
  28#define RCC_PLL1CR              0x80
  29#define RCC_PLL1CFGR1           0x84
  30#define RCC_PLL1CFGR2           0x88
  31#define RCC_PLL2CR              0x94
  32#define RCC_PLL2CFGR1           0x98
  33#define RCC_PLL2CFGR2           0x9C
  34#define RCC_PLL3CR              0x880
  35#define RCC_PLL3CFGR1           0x884
  36#define RCC_PLL3CFGR2           0x888
  37#define RCC_PLL4CR              0x894
  38#define RCC_PLL4CFGR1           0x898
  39#define RCC_PLL4CFGR2           0x89C
  40#define RCC_APB1ENSETR          0xA00
  41#define RCC_APB2ENSETR          0xA08
  42#define RCC_APB3ENSETR          0xA10
  43#define RCC_APB4ENSETR          0x200
  44#define RCC_APB5ENSETR          0x208
  45#define RCC_AHB2ENSETR          0xA18
  46#define RCC_AHB3ENSETR          0xA20
  47#define RCC_AHB4ENSETR          0xA28
  48#define RCC_AHB5ENSETR          0x210
  49#define RCC_AHB6ENSETR          0x218
  50#define RCC_AHB6LPENSETR        0x318
  51#define RCC_RCK12SELR           0x28
  52#define RCC_RCK3SELR            0x820
  53#define RCC_RCK4SELR            0x824
  54#define RCC_MPCKSELR            0x20
  55#define RCC_ASSCKSELR           0x24
  56#define RCC_MSSCKSELR           0x48
  57#define RCC_SPI6CKSELR          0xC4
  58#define RCC_SDMMC12CKSELR       0x8F4
  59#define RCC_SDMMC3CKSELR        0x8F8
  60#define RCC_FMCCKSELR           0x904
  61#define RCC_I2C46CKSELR         0xC0
  62#define RCC_I2C12CKSELR         0x8C0
  63#define RCC_I2C35CKSELR         0x8C4
  64#define RCC_UART1CKSELR         0xC8
  65#define RCC_QSPICKSELR          0x900
  66#define RCC_ETHCKSELR           0x8FC
  67#define RCC_RNG1CKSELR          0xCC
  68#define RCC_RNG2CKSELR          0x920
  69#define RCC_GPUCKSELR           0x938
  70#define RCC_USBCKSELR           0x91C
  71#define RCC_STGENCKSELR         0xD4
  72#define RCC_SPDIFCKSELR         0x914
  73#define RCC_SPI2S1CKSELR        0x8D8
  74#define RCC_SPI2S23CKSELR       0x8DC
  75#define RCC_SPI2S45CKSELR       0x8E0
  76#define RCC_CECCKSELR           0x918
  77#define RCC_LPTIM1CKSELR        0x934
  78#define RCC_LPTIM23CKSELR       0x930
  79#define RCC_LPTIM45CKSELR       0x92C
  80#define RCC_UART24CKSELR        0x8E8
  81#define RCC_UART35CKSELR        0x8EC
  82#define RCC_UART6CKSELR         0x8E4
  83#define RCC_UART78CKSELR        0x8F0
  84#define RCC_FDCANCKSELR         0x90C
  85#define RCC_SAI1CKSELR          0x8C8
  86#define RCC_SAI2CKSELR          0x8CC
  87#define RCC_SAI3CKSELR          0x8D0
  88#define RCC_SAI4CKSELR          0x8D4
  89#define RCC_ADCCKSELR           0x928
  90#define RCC_MPCKDIVR            0x2C
  91#define RCC_DSICKSELR           0x924
  92#define RCC_CPERCKSELR          0xD0
  93#define RCC_MCO1CFGR            0x800
  94#define RCC_MCO2CFGR            0x804
  95#define RCC_BDCR                0x140
  96#define RCC_AXIDIVR             0x30
  97#define RCC_MCUDIVR             0x830
  98#define RCC_APB1DIVR            0x834
  99#define RCC_APB2DIVR            0x838
 100#define RCC_APB3DIVR            0x83C
 101#define RCC_APB4DIVR            0x3C
 102#define RCC_APB5DIVR            0x40
 103#define RCC_TIMG1PRER           0x828
 104#define RCC_TIMG2PRER           0x82C
 105#define RCC_RTCDIVR             0x44
 106#define RCC_DBGCFGR             0x80C
 107
 108#define RCC_CLR 0x4
 109
 110static const char * const ref12_parents[] = {
 111        "ck_hsi", "ck_hse"
 112};
 113
 114static const char * const ref3_parents[] = {
 115        "ck_hsi", "ck_hse", "ck_csi"
 116};
 117
 118static const char * const ref4_parents[] = {
 119        "ck_hsi", "ck_hse", "ck_csi"
 120};
 121
 122static const char * const cpu_src[] = {
 123        "ck_hsi", "ck_hse", "pll1_p"
 124};
 125
 126static const char * const axi_src[] = {
 127        "ck_hsi", "ck_hse", "pll2_p"
 128};
 129
 130static const char * const per_src[] = {
 131        "ck_hsi", "ck_csi", "ck_hse"
 132};
 133
 134static const char * const mcu_src[] = {
 135        "ck_hsi", "ck_hse", "ck_csi", "pll3_p"
 136};
 137
 138static const char * const sdmmc12_src[] = {
 139        "ck_axi", "pll3_r", "pll4_p", "ck_hsi"
 140};
 141
 142static const char * const sdmmc3_src[] = {
 143        "ck_mcu", "pll3_r", "pll4_p", "ck_hsi"
 144};
 145
 146static const char * const fmc_src[] = {
 147        "ck_axi", "pll3_r", "pll4_p", "ck_per"
 148};
 149
 150static const char * const qspi_src[] = {
 151        "ck_axi", "pll3_r", "pll4_p", "ck_per"
 152};
 153
 154static const char * const eth_src[] = {
 155        "pll4_p", "pll3_q"
 156};
 157
 158static const char * const rng_src[] = {
 159        "ck_csi", "pll4_r", "ck_lse", "ck_lsi"
 160};
 161
 162static const char * const usbphy_src[] = {
 163        "ck_hse", "pll4_r", "clk-hse-div2"
 164};
 165
 166static const char * const usbo_src[] = {
 167        "pll4_r", "ck_usbo_48m"
 168};
 169
 170static const char * const stgen_src[] = {
 171        "ck_hsi", "ck_hse"
 172};
 173
 174static const char * const spdif_src[] = {
 175        "pll4_p", "pll3_q", "ck_hsi"
 176};
 177
 178static const char * const spi123_src[] = {
 179        "pll4_p", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
 180};
 181
 182static const char * const spi45_src[] = {
 183        "pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
 184};
 185
 186static const char * const spi6_src[] = {
 187        "pclk5", "pll4_q", "ck_hsi", "ck_csi", "ck_hse", "pll3_q"
 188};
 189
 190static const char * const cec_src[] = {
 191        "ck_lse", "ck_lsi", "ck_csi"
 192};
 193
 194static const char * const i2c12_src[] = {
 195        "pclk1", "pll4_r", "ck_hsi", "ck_csi"
 196};
 197
 198static const char * const i2c35_src[] = {
 199        "pclk1", "pll4_r", "ck_hsi", "ck_csi"
 200};
 201
 202static const char * const i2c46_src[] = {
 203        "pclk5", "pll3_q", "ck_hsi", "ck_csi"
 204};
 205
 206static const char * const lptim1_src[] = {
 207        "pclk1", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per"
 208};
 209
 210static const char * const lptim23_src[] = {
 211        "pclk3", "pll4_q", "ck_per", "ck_lse", "ck_lsi"
 212};
 213
 214static const char * const lptim45_src[] = {
 215        "pclk3", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per"
 216};
 217
 218static const char * const usart1_src[] = {
 219        "pclk5", "pll3_q", "ck_hsi", "ck_csi", "pll4_q", "ck_hse"
 220};
 221
 222static const char * const usart234578_src[] = {
 223        "pclk1", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
 224};
 225
 226static const char * const usart6_src[] = {
 227        "pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
 228};
 229
 230static const char * const fdcan_src[] = {
 231        "ck_hse", "pll3_q", "pll4_q", "pll4_r"
 232};
 233
 234static const char * const sai_src[] = {
 235        "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
 236};
 237
 238static const char * const sai2_src[] = {
 239        "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "spdif_ck_symb", "pll3_r"
 240};
 241
 242static const char * const adc12_src[] = {
 243        "pll4_r", "ck_per", "pll3_q"
 244};
 245
 246static const char * const dsi_src[] = {
 247        "ck_dsi_phy", "pll4_p"
 248};
 249
 250static const char * const rtc_src[] = {
 251        "off", "ck_lse", "ck_lsi", "ck_hse"
 252};
 253
 254static const char * const mco1_src[] = {
 255        "ck_hsi", "ck_hse", "ck_csi", "ck_lsi", "ck_lse"
 256};
 257
 258static const char * const mco2_src[] = {
 259        "ck_mpu", "ck_axi", "ck_mcu", "pll4_p", "ck_hse", "ck_hsi"
 260};
 261
 262static const char * const ck_trace_src[] = {
 263        "ck_axi"
 264};
 265
 266static const struct clk_div_table axi_div_table[] = {
 267        { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
 268        { 4, 4 }, { 5, 4 }, { 6, 4 }, { 7, 4 },
 269        { 0 },
 270};
 271
 272static const struct clk_div_table mcu_div_table[] = {
 273        { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
 274        { 4, 16 }, { 5, 32 }, { 6, 64 }, { 7, 128 },
 275        { 8, 256 }, { 9, 512 }, { 10, 512}, { 11, 512 },
 276        { 12, 512 }, { 13, 512 }, { 14, 512}, { 15, 512 },
 277        { 0 },
 278};
 279
 280static const struct clk_div_table apb_div_table[] = {
 281        { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
 282        { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 },
 283        { 0 },
 284};
 285
 286static const struct clk_div_table ck_trace_div_table[] = {
 287        { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
 288        { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 },
 289        { 0 },
 290};
 291
 292#define MAX_MUX_CLK 2
 293
 294struct stm32_mmux {
 295        u8 nbr_clk;
 296        struct clk_hw *hws[MAX_MUX_CLK];
 297};
 298
 299struct stm32_clk_mmux {
 300        struct clk_mux mux;
 301        struct stm32_mmux *mmux;
 302};
 303
 304struct stm32_mgate {
 305        u8 nbr_clk;
 306        u32 flag;
 307};
 308
 309struct stm32_clk_mgate {
 310        struct clk_gate gate;
 311        struct stm32_mgate *mgate;
 312        u32 mask;
 313};
 314
 315struct clock_config {
 316        u32 id;
 317        const char *name;
 318        const char *parent_name;
 319        const char * const *parent_names;
 320        int num_parents;
 321        unsigned long flags;
 322        void *cfg;
 323        struct clk_hw * (*func)(struct device *dev,
 324                                struct clk_hw_onecell_data *clk_data,
 325                                void __iomem *base, spinlock_t *lock,
 326                                const struct clock_config *cfg);
 327};
 328
 329#define NO_ID ~0
 330
 331struct gate_cfg {
 332        u32 reg_off;
 333        u8 bit_idx;
 334        u8 gate_flags;
 335};
 336
 337struct fixed_factor_cfg {
 338        unsigned int mult;
 339        unsigned int div;
 340};
 341
 342struct div_cfg {
 343        u32 reg_off;
 344        u8 shift;
 345        u8 width;
 346        u8 div_flags;
 347        const struct clk_div_table *table;
 348};
 349
 350struct mux_cfg {
 351        u32 reg_off;
 352        u8 shift;
 353        u8 width;
 354        u8 mux_flags;
 355        u32 *table;
 356};
 357
 358struct stm32_gate_cfg {
 359        struct gate_cfg         *gate;
 360        struct stm32_mgate      *mgate;
 361        const struct clk_ops    *ops;
 362};
 363
 364struct stm32_div_cfg {
 365        struct div_cfg          *div;
 366        const struct clk_ops    *ops;
 367};
 368
 369struct stm32_mux_cfg {
 370        struct mux_cfg          *mux;
 371        struct stm32_mmux       *mmux;
 372        const struct clk_ops    *ops;
 373};
 374
 375/* STM32 Composite clock */
 376struct stm32_composite_cfg {
 377        const struct stm32_gate_cfg     *gate;
 378        const struct stm32_div_cfg      *div;
 379        const struct stm32_mux_cfg      *mux;
 380};
 381
 382static struct clk_hw *
 383_clk_hw_register_gate(struct device *dev,
 384                      struct clk_hw_onecell_data *clk_data,
 385                      void __iomem *base, spinlock_t *lock,
 386                      const struct clock_config *cfg)
 387{
 388        struct gate_cfg *gate_cfg = cfg->cfg;
 389
 390        return clk_hw_register_gate(dev,
 391                                    cfg->name,
 392                                    cfg->parent_name,
 393                                    cfg->flags,
 394                                    gate_cfg->reg_off + base,
 395                                    gate_cfg->bit_idx,
 396                                    gate_cfg->gate_flags,
 397                                    lock);
 398}
 399
 400static struct clk_hw *
 401_clk_hw_register_fixed_factor(struct device *dev,
 402                              struct clk_hw_onecell_data *clk_data,
 403                              void __iomem *base, spinlock_t *lock,
 404                              const struct clock_config *cfg)
 405{
 406        struct fixed_factor_cfg *ff_cfg = cfg->cfg;
 407
 408        return clk_hw_register_fixed_factor(dev, cfg->name, cfg->parent_name,
 409                                            cfg->flags, ff_cfg->mult,
 410                                            ff_cfg->div);
 411}
 412
 413static struct clk_hw *
 414_clk_hw_register_divider_table(struct device *dev,
 415                               struct clk_hw_onecell_data *clk_data,
 416                               void __iomem *base, spinlock_t *lock,
 417                               const struct clock_config *cfg)
 418{
 419        struct div_cfg *div_cfg = cfg->cfg;
 420
 421        return clk_hw_register_divider_table(dev,
 422                                             cfg->name,
 423                                             cfg->parent_name,
 424                                             cfg->flags,
 425                                             div_cfg->reg_off + base,
 426                                             div_cfg->shift,
 427                                             div_cfg->width,
 428                                             div_cfg->div_flags,
 429                                             div_cfg->table,
 430                                             lock);
 431}
 432
 433static struct clk_hw *
 434_clk_hw_register_mux(struct device *dev,
 435                     struct clk_hw_onecell_data *clk_data,
 436                     void __iomem *base, spinlock_t *lock,
 437                     const struct clock_config *cfg)
 438{
 439        struct mux_cfg *mux_cfg = cfg->cfg;
 440
 441        return clk_hw_register_mux(dev, cfg->name, cfg->parent_names,
 442                                   cfg->num_parents, cfg->flags,
 443                                   mux_cfg->reg_off + base, mux_cfg->shift,
 444                                   mux_cfg->width, mux_cfg->mux_flags, lock);
 445}
 446
 447/* MP1 Gate clock with set & clear registers */
 448
 449static int mp1_gate_clk_enable(struct clk_hw *hw)
 450{
 451        if (!clk_gate_ops.is_enabled(hw))
 452                clk_gate_ops.enable(hw);
 453
 454        return 0;
 455}
 456
 457static void mp1_gate_clk_disable(struct clk_hw *hw)
 458{
 459        struct clk_gate *gate = to_clk_gate(hw);
 460        unsigned long flags = 0;
 461
 462        if (clk_gate_ops.is_enabled(hw)) {
 463                spin_lock_irqsave(gate->lock, flags);
 464                writel_relaxed(BIT(gate->bit_idx), gate->reg + RCC_CLR);
 465                spin_unlock_irqrestore(gate->lock, flags);
 466        }
 467}
 468
 469static const struct clk_ops mp1_gate_clk_ops = {
 470        .enable         = mp1_gate_clk_enable,
 471        .disable        = mp1_gate_clk_disable,
 472        .is_enabled     = clk_gate_is_enabled,
 473};
 474
 475static struct clk_hw *_get_stm32_mux(struct device *dev, void __iomem *base,
 476                                     const struct stm32_mux_cfg *cfg,
 477                                     spinlock_t *lock)
 478{
 479        struct stm32_clk_mmux *mmux;
 480        struct clk_mux *mux;
 481        struct clk_hw *mux_hw;
 482
 483        if (cfg->mmux) {
 484                mmux = devm_kzalloc(dev, sizeof(*mmux), GFP_KERNEL);
 485                if (!mmux)
 486                        return ERR_PTR(-ENOMEM);
 487
 488                mmux->mux.reg = cfg->mux->reg_off + base;
 489                mmux->mux.shift = cfg->mux->shift;
 490                mmux->mux.mask = (1 << cfg->mux->width) - 1;
 491                mmux->mux.flags = cfg->mux->mux_flags;
 492                mmux->mux.table = cfg->mux->table;
 493                mmux->mux.lock = lock;
 494                mmux->mmux = cfg->mmux;
 495                mux_hw = &mmux->mux.hw;
 496                cfg->mmux->hws[cfg->mmux->nbr_clk++] = mux_hw;
 497
 498        } else {
 499                mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
 500                if (!mux)
 501                        return ERR_PTR(-ENOMEM);
 502
 503                mux->reg = cfg->mux->reg_off + base;
 504                mux->shift = cfg->mux->shift;
 505                mux->mask = (1 << cfg->mux->width) - 1;
 506                mux->flags = cfg->mux->mux_flags;
 507                mux->table = cfg->mux->table;
 508                mux->lock = lock;
 509                mux_hw = &mux->hw;
 510        }
 511
 512        return mux_hw;
 513}
 514
 515static struct clk_hw *_get_stm32_div(struct device *dev, void __iomem *base,
 516                                     const struct stm32_div_cfg *cfg,
 517                                     spinlock_t *lock)
 518{
 519        struct clk_divider *div;
 520
 521        div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
 522
 523        if (!div)
 524                return ERR_PTR(-ENOMEM);
 525
 526        div->reg = cfg->div->reg_off + base;
 527        div->shift = cfg->div->shift;
 528        div->width = cfg->div->width;
 529        div->flags = cfg->div->div_flags;
 530        div->table = cfg->div->table;
 531        div->lock = lock;
 532
 533        return &div->hw;
 534}
 535
 536static struct clk_hw *_get_stm32_gate(struct device *dev, void __iomem *base,
 537                                      const struct stm32_gate_cfg *cfg,
 538                                      spinlock_t *lock)
 539{
 540        struct stm32_clk_mgate *mgate;
 541        struct clk_gate *gate;
 542        struct clk_hw *gate_hw;
 543
 544        if (cfg->mgate) {
 545                mgate = devm_kzalloc(dev, sizeof(*mgate), GFP_KERNEL);
 546                if (!mgate)
 547                        return ERR_PTR(-ENOMEM);
 548
 549                mgate->gate.reg = cfg->gate->reg_off + base;
 550                mgate->gate.bit_idx = cfg->gate->bit_idx;
 551                mgate->gate.flags = cfg->gate->gate_flags;
 552                mgate->gate.lock = lock;
 553                mgate->mask = BIT(cfg->mgate->nbr_clk++);
 554
 555                mgate->mgate = cfg->mgate;
 556
 557                gate_hw = &mgate->gate.hw;
 558
 559        } else {
 560                gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
 561                if (!gate)
 562                        return ERR_PTR(-ENOMEM);
 563
 564                gate->reg = cfg->gate->reg_off + base;
 565                gate->bit_idx = cfg->gate->bit_idx;
 566                gate->flags = cfg->gate->gate_flags;
 567                gate->lock = lock;
 568
 569                gate_hw = &gate->hw;
 570        }
 571
 572        return gate_hw;
 573}
 574
 575static struct clk_hw *
 576clk_stm32_register_gate_ops(struct device *dev,
 577                            const char *name,
 578                            const char *parent_name,
 579                            unsigned long flags,
 580                            void __iomem *base,
 581                            const struct stm32_gate_cfg *cfg,
 582                            spinlock_t *lock)
 583{
 584        struct clk_init_data init = { NULL };
 585        struct clk_hw *hw;
 586        int ret;
 587
 588        init.name = name;
 589        init.parent_names = &parent_name;
 590        init.num_parents = 1;
 591        init.flags = flags;
 592
 593        init.ops = &clk_gate_ops;
 594
 595        if (cfg->ops)
 596                init.ops = cfg->ops;
 597
 598        hw = _get_stm32_gate(dev, base, cfg, lock);
 599        if (IS_ERR(hw))
 600                return ERR_PTR(-ENOMEM);
 601
 602        hw->init = &init;
 603
 604        ret = clk_hw_register(dev, hw);
 605        if (ret)
 606                hw = ERR_PTR(ret);
 607
 608        return hw;
 609}
 610
 611static struct clk_hw *
 612clk_stm32_register_composite(struct device *dev,
 613                             const char *name, const char * const *parent_names,
 614                             int num_parents, void __iomem *base,
 615                             const struct stm32_composite_cfg *cfg,
 616                             unsigned long flags, spinlock_t *lock)
 617{
 618        const struct clk_ops *mux_ops, *div_ops, *gate_ops;
 619        struct clk_hw *mux_hw, *div_hw, *gate_hw;
 620
 621        mux_hw = NULL;
 622        div_hw = NULL;
 623        gate_hw = NULL;
 624        mux_ops = NULL;
 625        div_ops = NULL;
 626        gate_ops = NULL;
 627
 628        if (cfg->mux) {
 629                mux_hw = _get_stm32_mux(dev, base, cfg->mux, lock);
 630
 631                if (!IS_ERR(mux_hw)) {
 632                        mux_ops = &clk_mux_ops;
 633
 634                        if (cfg->mux->ops)
 635                                mux_ops = cfg->mux->ops;
 636                }
 637        }
 638
 639        if (cfg->div) {
 640                div_hw = _get_stm32_div(dev, base, cfg->div, lock);
 641
 642                if (!IS_ERR(div_hw)) {
 643                        div_ops = &clk_divider_ops;
 644
 645                        if (cfg->div->ops)
 646                                div_ops = cfg->div->ops;
 647                }
 648        }
 649
 650        if (cfg->gate) {
 651                gate_hw = _get_stm32_gate(dev, base, cfg->gate, lock);
 652
 653                if (!IS_ERR(gate_hw)) {
 654                        gate_ops = &clk_gate_ops;
 655
 656                        if (cfg->gate->ops)
 657                                gate_ops = cfg->gate->ops;
 658                }
 659        }
 660
 661        return clk_hw_register_composite(dev, name, parent_names, num_parents,
 662                                       mux_hw, mux_ops, div_hw, div_ops,
 663                                       gate_hw, gate_ops, flags);
 664}
 665
 666#define to_clk_mgate(_gate) container_of(_gate, struct stm32_clk_mgate, gate)
 667
 668static int mp1_mgate_clk_enable(struct clk_hw *hw)
 669{
 670        struct clk_gate *gate = to_clk_gate(hw);
 671        struct stm32_clk_mgate *clk_mgate = to_clk_mgate(gate);
 672
 673        clk_mgate->mgate->flag |= clk_mgate->mask;
 674
 675        mp1_gate_clk_enable(hw);
 676
 677        return  0;
 678}
 679
 680static void mp1_mgate_clk_disable(struct clk_hw *hw)
 681{
 682        struct clk_gate *gate = to_clk_gate(hw);
 683        struct stm32_clk_mgate *clk_mgate = to_clk_mgate(gate);
 684
 685        clk_mgate->mgate->flag &= ~clk_mgate->mask;
 686
 687        if (clk_mgate->mgate->flag == 0)
 688                mp1_gate_clk_disable(hw);
 689}
 690
 691static const struct clk_ops mp1_mgate_clk_ops = {
 692        .enable         = mp1_mgate_clk_enable,
 693        .disable        = mp1_mgate_clk_disable,
 694        .is_enabled     = clk_gate_is_enabled,
 695
 696};
 697
 698#define to_clk_mmux(_mux) container_of(_mux, struct stm32_clk_mmux, mux)
 699
 700static u8 clk_mmux_get_parent(struct clk_hw *hw)
 701{
 702        return clk_mux_ops.get_parent(hw);
 703}
 704
 705static int clk_mmux_set_parent(struct clk_hw *hw, u8 index)
 706{
 707        struct clk_mux *mux = to_clk_mux(hw);
 708        struct stm32_clk_mmux *clk_mmux = to_clk_mmux(mux);
 709        struct clk_hw *hwp;
 710        int ret, n;
 711
 712        ret = clk_mux_ops.set_parent(hw, index);
 713        if (ret)
 714                return ret;
 715
 716        hwp = clk_hw_get_parent(hw);
 717
 718        for (n = 0; n < clk_mmux->mmux->nbr_clk; n++)
 719                if (clk_mmux->mmux->hws[n] != hw)
 720                        clk_hw_reparent(clk_mmux->mmux->hws[n], hwp);
 721
 722        return 0;
 723}
 724
 725static const struct clk_ops clk_mmux_ops = {
 726        .get_parent     = clk_mmux_get_parent,
 727        .set_parent     = clk_mmux_set_parent,
 728        .determine_rate = __clk_mux_determine_rate,
 729};
 730
 731/* STM32 PLL */
 732struct stm32_pll_obj {
 733        /* lock pll enable/disable registers */
 734        spinlock_t *lock;
 735        void __iomem *reg;
 736        struct clk_hw hw;
 737        struct clk_mux mux;
 738};
 739
 740#define to_pll(_hw) container_of(_hw, struct stm32_pll_obj, hw)
 741
 742#define PLL_ON          BIT(0)
 743#define PLL_RDY         BIT(1)
 744#define DIVN_MASK       0x1FF
 745#define DIVM_MASK       0x3F
 746#define DIVM_SHIFT      16
 747#define DIVN_SHIFT      0
 748#define FRAC_OFFSET     0xC
 749#define FRAC_MASK       0x1FFF
 750#define FRAC_SHIFT      3
 751#define FRACLE          BIT(16)
 752#define PLL_MUX_SHIFT   0
 753#define PLL_MUX_MASK    3
 754
 755static int __pll_is_enabled(struct clk_hw *hw)
 756{
 757        struct stm32_pll_obj *clk_elem = to_pll(hw);
 758
 759        return readl_relaxed(clk_elem->reg) & PLL_ON;
 760}
 761
 762#define TIMEOUT 5
 763
 764static int pll_enable(struct clk_hw *hw)
 765{
 766        struct stm32_pll_obj *clk_elem = to_pll(hw);
 767        u32 reg;
 768        unsigned long flags = 0;
 769        unsigned int timeout = TIMEOUT;
 770        int bit_status = 0;
 771
 772        spin_lock_irqsave(clk_elem->lock, flags);
 773
 774        if (__pll_is_enabled(hw))
 775                goto unlock;
 776
 777        reg = readl_relaxed(clk_elem->reg);
 778        reg |= PLL_ON;
 779        writel_relaxed(reg, clk_elem->reg);
 780
 781        /* We can't use readl_poll_timeout() because we can be blocked if
 782         * someone enables this clock before clocksource changes.
 783         * Only jiffies counter is available. Jiffies are incremented by
 784         * interruptions and enable op does not allow to be interrupted.
 785         */
 786        do {
 787                bit_status = !(readl_relaxed(clk_elem->reg) & PLL_RDY);
 788
 789                if (bit_status)
 790                        udelay(120);
 791
 792        } while (bit_status && --timeout);
 793
 794unlock:
 795        spin_unlock_irqrestore(clk_elem->lock, flags);
 796
 797        return bit_status;
 798}
 799
 800static void pll_disable(struct clk_hw *hw)
 801{
 802        struct stm32_pll_obj *clk_elem = to_pll(hw);
 803        u32 reg;
 804        unsigned long flags = 0;
 805
 806        spin_lock_irqsave(clk_elem->lock, flags);
 807
 808        reg = readl_relaxed(clk_elem->reg);
 809        reg &= ~PLL_ON;
 810        writel_relaxed(reg, clk_elem->reg);
 811
 812        spin_unlock_irqrestore(clk_elem->lock, flags);
 813}
 814
 815static u32 pll_frac_val(struct clk_hw *hw)
 816{
 817        struct stm32_pll_obj *clk_elem = to_pll(hw);
 818        u32 reg, frac = 0;
 819
 820        reg = readl_relaxed(clk_elem->reg + FRAC_OFFSET);
 821        if (reg & FRACLE)
 822                frac = (reg >> FRAC_SHIFT) & FRAC_MASK;
 823
 824        return frac;
 825}
 826
 827static unsigned long pll_recalc_rate(struct clk_hw *hw,
 828                                     unsigned long parent_rate)
 829{
 830        struct stm32_pll_obj *clk_elem = to_pll(hw);
 831        u32 reg;
 832        u32 frac, divm, divn;
 833        u64 rate, rate_frac = 0;
 834
 835        reg = readl_relaxed(clk_elem->reg + 4);
 836
 837        divm = ((reg >> DIVM_SHIFT) & DIVM_MASK) + 1;
 838        divn = ((reg >> DIVN_SHIFT) & DIVN_MASK) + 1;
 839        rate = (u64)parent_rate * divn;
 840
 841        do_div(rate, divm);
 842
 843        frac = pll_frac_val(hw);
 844        if (frac) {
 845                rate_frac = (u64)parent_rate * (u64)frac;
 846                do_div(rate_frac, (divm * 8192));
 847        }
 848
 849        return rate + rate_frac;
 850}
 851
 852static int pll_is_enabled(struct clk_hw *hw)
 853{
 854        struct stm32_pll_obj *clk_elem = to_pll(hw);
 855        unsigned long flags = 0;
 856        int ret;
 857
 858        spin_lock_irqsave(clk_elem->lock, flags);
 859        ret = __pll_is_enabled(hw);
 860        spin_unlock_irqrestore(clk_elem->lock, flags);
 861
 862        return ret;
 863}
 864
 865static u8 pll_get_parent(struct clk_hw *hw)
 866{
 867        struct stm32_pll_obj *clk_elem = to_pll(hw);
 868        struct clk_hw *mux_hw = &clk_elem->mux.hw;
 869
 870        __clk_hw_set_clk(mux_hw, hw);
 871
 872        return clk_mux_ops.get_parent(mux_hw);
 873}
 874
 875static const struct clk_ops pll_ops = {
 876        .enable         = pll_enable,
 877        .disable        = pll_disable,
 878        .recalc_rate    = pll_recalc_rate,
 879        .is_enabled     = pll_is_enabled,
 880        .get_parent     = pll_get_parent,
 881};
 882
 883static struct clk_hw *clk_register_pll(struct device *dev, const char *name,
 884                                       const char * const *parent_names,
 885                                       int num_parents,
 886                                       void __iomem *reg,
 887                                       void __iomem *mux_reg,
 888                                       unsigned long flags,
 889                                       spinlock_t *lock)
 890{
 891        struct stm32_pll_obj *element;
 892        struct clk_init_data init;
 893        struct clk_hw *hw;
 894        int err;
 895
 896        element = devm_kzalloc(dev, sizeof(*element), GFP_KERNEL);
 897        if (!element)
 898                return ERR_PTR(-ENOMEM);
 899
 900        init.name = name;
 901        init.ops = &pll_ops;
 902        init.flags = flags;
 903        init.parent_names = parent_names;
 904        init.num_parents = num_parents;
 905
 906        element->mux.lock = lock;
 907        element->mux.reg =  mux_reg;
 908        element->mux.shift = PLL_MUX_SHIFT;
 909        element->mux.mask =  PLL_MUX_MASK;
 910        element->mux.flags =  CLK_MUX_READ_ONLY;
 911        element->mux.reg =  mux_reg;
 912
 913        element->hw.init = &init;
 914        element->reg = reg;
 915        element->lock = lock;
 916
 917        hw = &element->hw;
 918        err = clk_hw_register(dev, hw);
 919
 920        if (err)
 921                return ERR_PTR(err);
 922
 923        return hw;
 924}
 925
 926/* Kernel Timer */
 927struct timer_cker {
 928        /* lock the kernel output divider register */
 929        spinlock_t *lock;
 930        void __iomem *apbdiv;
 931        void __iomem *timpre;
 932        struct clk_hw hw;
 933};
 934
 935#define to_timer_cker(_hw) container_of(_hw, struct timer_cker, hw)
 936
 937#define APB_DIV_MASK 0x07
 938#define TIM_PRE_MASK 0x01
 939
 940static unsigned long __bestmult(struct clk_hw *hw, unsigned long rate,
 941                                unsigned long parent_rate)
 942{
 943        struct timer_cker *tim_ker = to_timer_cker(hw);
 944        u32 prescaler;
 945        unsigned int mult = 0;
 946
 947        prescaler = readl_relaxed(tim_ker->apbdiv) & APB_DIV_MASK;
 948        if (prescaler < 2)
 949                return 1;
 950
 951        mult = 2;
 952
 953        if (rate / parent_rate >= 4)
 954                mult = 4;
 955
 956        return mult;
 957}
 958
 959static long timer_ker_round_rate(struct clk_hw *hw, unsigned long rate,
 960                                 unsigned long *parent_rate)
 961{
 962        unsigned long factor = __bestmult(hw, rate, *parent_rate);
 963
 964        return *parent_rate * factor;
 965}
 966
 967static int timer_ker_set_rate(struct clk_hw *hw, unsigned long rate,
 968                              unsigned long parent_rate)
 969{
 970        struct timer_cker *tim_ker = to_timer_cker(hw);
 971        unsigned long flags = 0;
 972        unsigned long factor = __bestmult(hw, rate, parent_rate);
 973        int ret = 0;
 974
 975        spin_lock_irqsave(tim_ker->lock, flags);
 976
 977        switch (factor) {
 978        case 1:
 979                break;
 980        case 2:
 981                writel_relaxed(0, tim_ker->timpre);
 982                break;
 983        case 4:
 984                writel_relaxed(1, tim_ker->timpre);
 985                break;
 986        default:
 987                ret = -EINVAL;
 988        }
 989        spin_unlock_irqrestore(tim_ker->lock, flags);
 990
 991        return ret;
 992}
 993
 994static unsigned long timer_ker_recalc_rate(struct clk_hw *hw,
 995                                           unsigned long parent_rate)
 996{
 997        struct timer_cker *tim_ker = to_timer_cker(hw);
 998        u32 prescaler, timpre;
 999        u32 mul;
1000
1001        prescaler = readl_relaxed(tim_ker->apbdiv) & APB_DIV_MASK;
1002
1003        timpre = readl_relaxed(tim_ker->timpre) & TIM_PRE_MASK;
1004
1005        if (!prescaler)
1006                return parent_rate;
1007
1008        mul = (timpre + 1) * 2;
1009
1010        return parent_rate * mul;
1011}
1012
1013static const struct clk_ops timer_ker_ops = {
1014        .recalc_rate    = timer_ker_recalc_rate,
1015        .round_rate     = timer_ker_round_rate,
1016        .set_rate       = timer_ker_set_rate,
1017
1018};
1019
1020static struct clk_hw *clk_register_cktim(struct device *dev, const char *name,
1021                                         const char *parent_name,
1022                                         unsigned long flags,
1023                                         void __iomem *apbdiv,
1024                                         void __iomem *timpre,
1025                                         spinlock_t *lock)
1026{
1027        struct timer_cker *tim_ker;
1028        struct clk_init_data init;
1029        struct clk_hw *hw;
1030        int err;
1031
1032        tim_ker = devm_kzalloc(dev, sizeof(*tim_ker), GFP_KERNEL);
1033        if (!tim_ker)
1034                return ERR_PTR(-ENOMEM);
1035
1036        init.name = name;
1037        init.ops = &timer_ker_ops;
1038        init.flags = flags;
1039        init.parent_names = &parent_name;
1040        init.num_parents = 1;
1041
1042        tim_ker->hw.init = &init;
1043        tim_ker->lock = lock;
1044        tim_ker->apbdiv = apbdiv;
1045        tim_ker->timpre = timpre;
1046
1047        hw = &tim_ker->hw;
1048        err = clk_hw_register(dev, hw);
1049
1050        if (err)
1051                return ERR_PTR(err);
1052
1053        return hw;
1054}
1055
1056/* The divider of RTC clock concerns only ck_hse clock */
1057#define HSE_RTC 3
1058
1059static unsigned long clk_divider_rtc_recalc_rate(struct clk_hw *hw,
1060                                                 unsigned long parent_rate)
1061{
1062        if (clk_hw_get_parent(hw) == clk_hw_get_parent_by_index(hw, HSE_RTC))
1063                return clk_divider_ops.recalc_rate(hw, parent_rate);
1064
1065        return parent_rate;
1066}
1067
1068static int clk_divider_rtc_set_rate(struct clk_hw *hw, unsigned long rate,
1069                                    unsigned long parent_rate)
1070{
1071        if (clk_hw_get_parent(hw) == clk_hw_get_parent_by_index(hw, HSE_RTC))
1072                return clk_divider_ops.set_rate(hw, rate, parent_rate);
1073
1074        return parent_rate;
1075}
1076
1077static int clk_divider_rtc_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
1078{
1079        unsigned long best_parent_rate = req->best_parent_rate;
1080
1081        if (req->best_parent_hw == clk_hw_get_parent_by_index(hw, HSE_RTC)) {
1082                req->rate = clk_divider_ops.round_rate(hw, req->rate, &best_parent_rate);
1083                req->best_parent_rate = best_parent_rate;
1084        } else {
1085                req->rate = best_parent_rate;
1086        }
1087
1088        return 0;
1089}
1090
1091static const struct clk_ops rtc_div_clk_ops = {
1092        .recalc_rate    = clk_divider_rtc_recalc_rate,
1093        .set_rate       = clk_divider_rtc_set_rate,
1094        .determine_rate = clk_divider_rtc_determine_rate
1095};
1096
1097struct stm32_pll_cfg {
1098        u32 offset;
1099        u32 muxoff;
1100};
1101
1102static struct clk_hw *_clk_register_pll(struct device *dev,
1103                                        struct clk_hw_onecell_data *clk_data,
1104                                        void __iomem *base, spinlock_t *lock,
1105                                        const struct clock_config *cfg)
1106{
1107        struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg;
1108
1109        return clk_register_pll(dev, cfg->name, cfg->parent_names,
1110                                cfg->num_parents,
1111                                base + stm_pll_cfg->offset,
1112                                base + stm_pll_cfg->muxoff,
1113                                cfg->flags, lock);
1114}
1115
1116struct stm32_cktim_cfg {
1117        u32 offset_apbdiv;
1118        u32 offset_timpre;
1119};
1120
1121static struct clk_hw *_clk_register_cktim(struct device *dev,
1122                                          struct clk_hw_onecell_data *clk_data,
1123                                          void __iomem *base, spinlock_t *lock,
1124                                          const struct clock_config *cfg)
1125{
1126        struct stm32_cktim_cfg *cktim_cfg = cfg->cfg;
1127
1128        return clk_register_cktim(dev, cfg->name, cfg->parent_name, cfg->flags,
1129                                  cktim_cfg->offset_apbdiv + base,
1130                                  cktim_cfg->offset_timpre + base, lock);
1131}
1132
1133static struct clk_hw *
1134_clk_stm32_register_gate(struct device *dev,
1135                         struct clk_hw_onecell_data *clk_data,
1136                         void __iomem *base, spinlock_t *lock,
1137                         const struct clock_config *cfg)
1138{
1139        return clk_stm32_register_gate_ops(dev,
1140                                    cfg->name,
1141                                    cfg->parent_name,
1142                                    cfg->flags,
1143                                    base,
1144                                    cfg->cfg,
1145                                    lock);
1146}
1147
1148static struct clk_hw *
1149_clk_stm32_register_composite(struct device *dev,
1150                              struct clk_hw_onecell_data *clk_data,
1151                              void __iomem *base, spinlock_t *lock,
1152                              const struct clock_config *cfg)
1153{
1154        return clk_stm32_register_composite(dev, cfg->name, cfg->parent_names,
1155                                            cfg->num_parents, base, cfg->cfg,
1156                                            cfg->flags, lock);
1157}
1158
1159#define GATE(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\
1160{\
1161        .id             = _id,\
1162        .name           = _name,\
1163        .parent_name    = _parent,\
1164        .flags          = _flags,\
1165        .cfg            =  &(struct gate_cfg) {\
1166                .reg_off        = _offset,\
1167                .bit_idx        = _bit_idx,\
1168                .gate_flags     = _gate_flags,\
1169        },\
1170        .func           = _clk_hw_register_gate,\
1171}
1172
1173#define FIXED_FACTOR(_id, _name, _parent, _flags, _mult, _div)\
1174{\
1175        .id             = _id,\
1176        .name           = _name,\
1177        .parent_name    = _parent,\
1178        .flags          = _flags,\
1179        .cfg            =  &(struct fixed_factor_cfg) {\
1180                .mult = _mult,\
1181                .div = _div,\
1182        },\
1183        .func           = _clk_hw_register_fixed_factor,\
1184}
1185
1186#define DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\
1187                  _div_flags, _div_table)\
1188{\
1189        .id             = _id,\
1190        .name           = _name,\
1191        .parent_name    = _parent,\
1192        .flags          = _flags,\
1193        .cfg            =  &(struct div_cfg) {\
1194                .reg_off        = _offset,\
1195                .shift          = _shift,\
1196                .width          = _width,\
1197                .div_flags      = _div_flags,\
1198                .table          = _div_table,\
1199        },\
1200        .func           = _clk_hw_register_divider_table,\
1201}
1202
1203#define DIV(_id, _name, _parent, _flags, _offset, _shift, _width, _div_flags)\
1204        DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\
1205                  _div_flags, NULL)
1206
1207#define MUX(_id, _name, _parents, _flags, _offset, _shift, _width, _mux_flags)\
1208{\
1209        .id             = _id,\
1210        .name           = _name,\
1211        .parent_names   = _parents,\
1212        .num_parents    = ARRAY_SIZE(_parents),\
1213        .flags          = _flags,\
1214        .cfg            =  &(struct mux_cfg) {\
1215                .reg_off        = _offset,\
1216                .shift          = _shift,\
1217                .width          = _width,\
1218                .mux_flags      = _mux_flags,\
1219        },\
1220        .func           = _clk_hw_register_mux,\
1221}
1222
1223#define PLL(_id, _name, _parents, _flags, _offset_p, _offset_mux)\
1224{\
1225        .id             = _id,\
1226        .name           = _name,\
1227        .parent_names   = _parents,\
1228        .num_parents    = ARRAY_SIZE(_parents),\
1229        .flags          = CLK_IGNORE_UNUSED | (_flags),\
1230        .cfg            =  &(struct stm32_pll_cfg) {\
1231                .offset = _offset_p,\
1232                .muxoff = _offset_mux,\
1233        },\
1234        .func           = _clk_register_pll,\
1235}
1236
1237#define STM32_CKTIM(_name, _parent, _flags, _offset_apbdiv, _offset_timpre)\
1238{\
1239        .id             = NO_ID,\
1240        .name           = _name,\
1241        .parent_name    = _parent,\
1242        .flags          = _flags,\
1243        .cfg            =  &(struct stm32_cktim_cfg) {\
1244                .offset_apbdiv = _offset_apbdiv,\
1245                .offset_timpre = _offset_timpre,\
1246        },\
1247        .func           = _clk_register_cktim,\
1248}
1249
1250#define STM32_TIM(_id, _name, _parent, _offset_set, _bit_idx)\
1251                  GATE_MP1(_id, _name, _parent, CLK_SET_RATE_PARENT,\
1252                           _offset_set, _bit_idx, 0)
1253
1254/* STM32 GATE */
1255#define STM32_GATE(_id, _name, _parent, _flags, _gate)\
1256{\
1257        .id             = _id,\
1258        .name           = _name,\
1259        .parent_name    = _parent,\
1260        .flags          = _flags,\
1261        .cfg            = (struct stm32_gate_cfg *) {_gate},\
1262        .func           = _clk_stm32_register_gate,\
1263}
1264
1265#define _STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags, _mgate, _ops)\
1266        (&(struct stm32_gate_cfg) {\
1267                &(struct gate_cfg) {\
1268                        .reg_off        = _gate_offset,\
1269                        .bit_idx        = _gate_bit_idx,\
1270                        .gate_flags     = _gate_flags,\
1271                },\
1272                .mgate          = _mgate,\
1273                .ops            = _ops,\
1274        })
1275
1276#define _STM32_MGATE(_mgate)\
1277        (&per_gate_cfg[_mgate])
1278
1279#define _GATE(_gate_offset, _gate_bit_idx, _gate_flags)\
1280        _STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags,\
1281                    NULL, NULL)\
1282
1283#define _GATE_MP1(_gate_offset, _gate_bit_idx, _gate_flags)\
1284        _STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags,\
1285                    NULL, &mp1_gate_clk_ops)\
1286
1287#define _MGATE_MP1(_mgate)\
1288        .gate = &per_gate_cfg[_mgate]
1289
1290#define GATE_MP1(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\
1291        STM32_GATE(_id, _name, _parent, _flags,\
1292                   _GATE_MP1(_offset, _bit_idx, _gate_flags))
1293
1294#define MGATE_MP1(_id, _name, _parent, _flags, _mgate)\
1295        STM32_GATE(_id, _name, _parent, _flags,\
1296                   _STM32_MGATE(_mgate))
1297
1298#define _STM32_DIV(_div_offset, _div_shift, _div_width,\
1299                   _div_flags, _div_table, _ops)\
1300        .div = &(struct stm32_div_cfg) {\
1301                &(struct div_cfg) {\
1302                        .reg_off        = _div_offset,\
1303                        .shift          = _div_shift,\
1304                        .width          = _div_width,\
1305                        .div_flags      = _div_flags,\
1306                        .table          = _div_table,\
1307                },\
1308                .ops            = _ops,\
1309        }
1310
1311#define _DIV(_div_offset, _div_shift, _div_width, _div_flags, _div_table)\
1312        _STM32_DIV(_div_offset, _div_shift, _div_width,\
1313                   _div_flags, _div_table, NULL)\
1314
1315#define _DIV_RTC(_div_offset, _div_shift, _div_width, _div_flags, _div_table)\
1316        _STM32_DIV(_div_offset, _div_shift, _div_width,\
1317                   _div_flags, _div_table, &rtc_div_clk_ops)
1318
1319#define _STM32_MUX(_offset, _shift, _width, _mux_flags, _mmux, _ops)\
1320        .mux = &(struct stm32_mux_cfg) {\
1321                &(struct mux_cfg) {\
1322                        .reg_off        = _offset,\
1323                        .shift          = _shift,\
1324                        .width          = _width,\
1325                        .mux_flags      = _mux_flags,\
1326                        .table          = NULL,\
1327                },\
1328                .mmux           = _mmux,\
1329                .ops            = _ops,\
1330        }
1331
1332#define _MUX(_offset, _shift, _width, _mux_flags)\
1333        _STM32_MUX(_offset, _shift, _width, _mux_flags, NULL, NULL)\
1334
1335#define _MMUX(_mmux) .mux = &ker_mux_cfg[_mmux]
1336
1337#define PARENT(_parent) ((const char *[]) { _parent})
1338
1339#define _NO_MUX .mux = NULL
1340#define _NO_DIV .div = NULL
1341#define _NO_GATE .gate = NULL
1342
1343#define COMPOSITE(_id, _name, _parents, _flags, _gate, _mux, _div)\
1344{\
1345        .id             = _id,\
1346        .name           = _name,\
1347        .parent_names   = _parents,\
1348        .num_parents    = ARRAY_SIZE(_parents),\
1349        .flags          = _flags,\
1350        .cfg            = &(struct stm32_composite_cfg) {\
1351                _gate,\
1352                _mux,\
1353                _div,\
1354        },\
1355        .func           = _clk_stm32_register_composite,\
1356}
1357
1358#define PCLK(_id, _name, _parent, _flags, _mgate)\
1359        MGATE_MP1(_id, _name, _parent, _flags, _mgate)
1360
1361#define KCLK(_id, _name, _parents, _flags, _mgate, _mmux)\
1362             COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE |\
1363                       CLK_SET_RATE_NO_REPARENT | _flags,\
1364                       _MGATE_MP1(_mgate),\
1365                       _MMUX(_mmux),\
1366                       _NO_DIV)
1367
1368enum {
1369        G_SAI1,
1370        G_SAI2,
1371        G_SAI3,
1372        G_SAI4,
1373        G_SPI1,
1374        G_SPI2,
1375        G_SPI3,
1376        G_SPI4,
1377        G_SPI5,
1378        G_SPI6,
1379        G_SPDIF,
1380        G_I2C1,
1381        G_I2C2,
1382        G_I2C3,
1383        G_I2C4,
1384        G_I2C5,
1385        G_I2C6,
1386        G_USART2,
1387        G_UART4,
1388        G_USART3,
1389        G_UART5,
1390        G_USART1,
1391        G_USART6,
1392        G_UART7,
1393        G_UART8,
1394        G_LPTIM1,
1395        G_LPTIM2,
1396        G_LPTIM3,
1397        G_LPTIM4,
1398        G_LPTIM5,
1399        G_LTDC,
1400        G_DSI,
1401        G_QSPI,
1402        G_FMC,
1403        G_SDMMC1,
1404        G_SDMMC2,
1405        G_SDMMC3,
1406        G_USBO,
1407        G_USBPHY,
1408        G_RNG1,
1409        G_RNG2,
1410        G_FDCAN,
1411        G_DAC12,
1412        G_CEC,
1413        G_ADC12,
1414        G_GPU,
1415        G_STGEN,
1416        G_DFSDM,
1417        G_ADFSDM,
1418        G_TIM2,
1419        G_TIM3,
1420        G_TIM4,
1421        G_TIM5,
1422        G_TIM6,
1423        G_TIM7,
1424        G_TIM12,
1425        G_TIM13,
1426        G_TIM14,
1427        G_MDIO,
1428        G_TIM1,
1429        G_TIM8,
1430        G_TIM15,
1431        G_TIM16,
1432        G_TIM17,
1433        G_SYSCFG,
1434        G_VREF,
1435        G_TMPSENS,
1436        G_PMBCTRL,
1437        G_HDP,
1438        G_IWDG2,
1439        G_STGENRO,
1440        G_DMA1,
1441        G_DMA2,
1442        G_DMAMUX,
1443        G_DCMI,
1444        G_CRYP2,
1445        G_HASH2,
1446        G_CRC2,
1447        G_HSEM,
1448        G_IPCC,
1449        G_GPIOA,
1450        G_GPIOB,
1451        G_GPIOC,
1452        G_GPIOD,
1453        G_GPIOE,
1454        G_GPIOF,
1455        G_GPIOG,
1456        G_GPIOH,
1457        G_GPIOI,
1458        G_GPIOJ,
1459        G_GPIOK,
1460        G_MDMA,
1461        G_ETHCK,
1462        G_ETHTX,
1463        G_ETHRX,
1464        G_ETHMAC,
1465        G_CRC1,
1466        G_USBH,
1467        G_ETHSTP,
1468        G_RTCAPB,
1469        G_TZC1,
1470        G_TZC2,
1471        G_TZPC,
1472        G_IWDG1,
1473        G_BSEC,
1474        G_GPIOZ,
1475        G_CRYP1,
1476        G_HASH1,
1477        G_BKPSRAM,
1478        G_DDRPERFM,
1479
1480        G_LAST
1481};
1482
1483static struct stm32_mgate mp1_mgate[G_LAST];
1484
1485#define _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
1486               _mgate, _ops)\
1487        [_id] = {\
1488                &(struct gate_cfg) {\
1489                        .reg_off        = _gate_offset,\
1490                        .bit_idx        = _gate_bit_idx,\
1491                        .gate_flags     = _gate_flags,\
1492                },\
1493                .mgate          = _mgate,\
1494                .ops            = _ops,\
1495        }
1496
1497#define K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags)\
1498        _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
1499               NULL, &mp1_gate_clk_ops)
1500
1501#define K_MGATE(_id, _gate_offset, _gate_bit_idx, _gate_flags)\
1502        _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
1503               &mp1_mgate[_id], &mp1_mgate_clk_ops)
1504
1505/* Peripheral gates */
1506static struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
1507        /* Multi gates */
1508        K_GATE(G_MDIO,          RCC_APB1ENSETR, 31, 0),
1509        K_MGATE(G_DAC12,        RCC_APB1ENSETR, 29, 0),
1510        K_MGATE(G_CEC,          RCC_APB1ENSETR, 27, 0),
1511        K_MGATE(G_SPDIF,        RCC_APB1ENSETR, 26, 0),
1512        K_MGATE(G_I2C5,         RCC_APB1ENSETR, 24, 0),
1513        K_MGATE(G_I2C3,         RCC_APB1ENSETR, 23, 0),
1514        K_MGATE(G_I2C2,         RCC_APB1ENSETR, 22, 0),
1515        K_MGATE(G_I2C1,         RCC_APB1ENSETR, 21, 0),
1516        K_MGATE(G_UART8,        RCC_APB1ENSETR, 19, 0),
1517        K_MGATE(G_UART7,        RCC_APB1ENSETR, 18, 0),
1518        K_MGATE(G_UART5,        RCC_APB1ENSETR, 17, 0),
1519        K_MGATE(G_UART4,        RCC_APB1ENSETR, 16, 0),
1520        K_MGATE(G_USART3,       RCC_APB1ENSETR, 15, 0),
1521        K_MGATE(G_USART2,       RCC_APB1ENSETR, 14, 0),
1522        K_MGATE(G_SPI3,         RCC_APB1ENSETR, 12, 0),
1523        K_MGATE(G_SPI2,         RCC_APB1ENSETR, 11, 0),
1524        K_MGATE(G_LPTIM1,       RCC_APB1ENSETR, 9, 0),
1525        K_GATE(G_TIM14,         RCC_APB1ENSETR, 8, 0),
1526        K_GATE(G_TIM13,         RCC_APB1ENSETR, 7, 0),
1527        K_GATE(G_TIM12,         RCC_APB1ENSETR, 6, 0),
1528        K_GATE(G_TIM7,          RCC_APB1ENSETR, 5, 0),
1529        K_GATE(G_TIM6,          RCC_APB1ENSETR, 4, 0),
1530        K_GATE(G_TIM5,          RCC_APB1ENSETR, 3, 0),
1531        K_GATE(G_TIM4,          RCC_APB1ENSETR, 2, 0),
1532        K_GATE(G_TIM3,          RCC_APB1ENSETR, 1, 0),
1533        K_GATE(G_TIM2,          RCC_APB1ENSETR, 0, 0),
1534
1535        K_MGATE(G_FDCAN,        RCC_APB2ENSETR, 24, 0),
1536        K_GATE(G_ADFSDM,        RCC_APB2ENSETR, 21, 0),
1537        K_GATE(G_DFSDM,         RCC_APB2ENSETR, 20, 0),
1538        K_MGATE(G_SAI3,         RCC_APB2ENSETR, 18, 0),
1539        K_MGATE(G_SAI2,         RCC_APB2ENSETR, 17, 0),
1540        K_MGATE(G_SAI1,         RCC_APB2ENSETR, 16, 0),
1541        K_MGATE(G_USART6,       RCC_APB2ENSETR, 13, 0),
1542        K_MGATE(G_SPI5,         RCC_APB2ENSETR, 10, 0),
1543        K_MGATE(G_SPI4,         RCC_APB2ENSETR, 9, 0),
1544        K_MGATE(G_SPI1,         RCC_APB2ENSETR, 8, 0),
1545        K_GATE(G_TIM17,         RCC_APB2ENSETR, 4, 0),
1546        K_GATE(G_TIM16,         RCC_APB2ENSETR, 3, 0),
1547        K_GATE(G_TIM15,         RCC_APB2ENSETR, 2, 0),
1548        K_GATE(G_TIM8,          RCC_APB2ENSETR, 1, 0),
1549        K_GATE(G_TIM1,          RCC_APB2ENSETR, 0, 0),
1550
1551        K_GATE(G_HDP,           RCC_APB3ENSETR, 20, 0),
1552        K_GATE(G_PMBCTRL,       RCC_APB3ENSETR, 17, 0),
1553        K_GATE(G_TMPSENS,       RCC_APB3ENSETR, 16, 0),
1554        K_GATE(G_VREF,          RCC_APB3ENSETR, 13, 0),
1555        K_GATE(G_SYSCFG,        RCC_APB3ENSETR, 11, 0),
1556        K_MGATE(G_SAI4,         RCC_APB3ENSETR, 8, 0),
1557        K_MGATE(G_LPTIM5,       RCC_APB3ENSETR, 3, 0),
1558        K_MGATE(G_LPTIM4,       RCC_APB3ENSETR, 2, 0),
1559        K_MGATE(G_LPTIM3,       RCC_APB3ENSETR, 1, 0),
1560        K_MGATE(G_LPTIM2,       RCC_APB3ENSETR, 0, 0),
1561
1562        K_GATE(G_STGENRO,       RCC_APB4ENSETR, 20, 0),
1563        K_MGATE(G_USBPHY,       RCC_APB4ENSETR, 16, 0),
1564        K_GATE(G_IWDG2,         RCC_APB4ENSETR, 15, 0),
1565        K_GATE(G_DDRPERFM,      RCC_APB4ENSETR, 8, 0),
1566        K_MGATE(G_DSI,          RCC_APB4ENSETR, 4, 0),
1567        K_MGATE(G_LTDC,         RCC_APB4ENSETR, 0, 0),
1568
1569        K_GATE(G_STGEN,         RCC_APB5ENSETR, 20, 0),
1570        K_GATE(G_BSEC,          RCC_APB5ENSETR, 16, 0),
1571        K_GATE(G_IWDG1,         RCC_APB5ENSETR, 15, 0),
1572        K_GATE(G_TZPC,          RCC_APB5ENSETR, 13, 0),
1573        K_GATE(G_TZC2,          RCC_APB5ENSETR, 12, 0),
1574        K_GATE(G_TZC1,          RCC_APB5ENSETR, 11, 0),
1575        K_GATE(G_RTCAPB,        RCC_APB5ENSETR, 8, 0),
1576        K_MGATE(G_USART1,       RCC_APB5ENSETR, 4, 0),
1577        K_MGATE(G_I2C6,         RCC_APB5ENSETR, 3, 0),
1578        K_MGATE(G_I2C4,         RCC_APB5ENSETR, 2, 0),
1579        K_MGATE(G_SPI6,         RCC_APB5ENSETR, 0, 0),
1580
1581        K_MGATE(G_SDMMC3,       RCC_AHB2ENSETR, 16, 0),
1582        K_MGATE(G_USBO,         RCC_AHB2ENSETR, 8, 0),
1583        K_MGATE(G_ADC12,        RCC_AHB2ENSETR, 5, 0),
1584        K_GATE(G_DMAMUX,        RCC_AHB2ENSETR, 2, 0),
1585        K_GATE(G_DMA2,          RCC_AHB2ENSETR, 1, 0),
1586        K_GATE(G_DMA1,          RCC_AHB2ENSETR, 0, 0),
1587
1588        K_GATE(G_IPCC,          RCC_AHB3ENSETR, 12, 0),
1589        K_GATE(G_HSEM,          RCC_AHB3ENSETR, 11, 0),
1590        K_GATE(G_CRC2,          RCC_AHB3ENSETR, 7, 0),
1591        K_MGATE(G_RNG2,         RCC_AHB3ENSETR, 6, 0),
1592        K_GATE(G_HASH2,         RCC_AHB3ENSETR, 5, 0),
1593        K_GATE(G_CRYP2,         RCC_AHB3ENSETR, 4, 0),
1594        K_GATE(G_DCMI,          RCC_AHB3ENSETR, 0, 0),
1595
1596        K_GATE(G_GPIOK,         RCC_AHB4ENSETR, 10, 0),
1597        K_GATE(G_GPIOJ,         RCC_AHB4ENSETR, 9, 0),
1598        K_GATE(G_GPIOI,         RCC_AHB4ENSETR, 8, 0),
1599        K_GATE(G_GPIOH,         RCC_AHB4ENSETR, 7, 0),
1600        K_GATE(G_GPIOG,         RCC_AHB4ENSETR, 6, 0),
1601        K_GATE(G_GPIOF,         RCC_AHB4ENSETR, 5, 0),
1602        K_GATE(G_GPIOE,         RCC_AHB4ENSETR, 4, 0),
1603        K_GATE(G_GPIOD,         RCC_AHB4ENSETR, 3, 0),
1604        K_GATE(G_GPIOC,         RCC_AHB4ENSETR, 2, 0),
1605        K_GATE(G_GPIOB,         RCC_AHB4ENSETR, 1, 0),
1606        K_GATE(G_GPIOA,         RCC_AHB4ENSETR, 0, 0),
1607
1608        K_GATE(G_BKPSRAM,       RCC_AHB5ENSETR, 8, 0),
1609        K_MGATE(G_RNG1,         RCC_AHB5ENSETR, 6, 0),
1610        K_GATE(G_HASH1,         RCC_AHB5ENSETR, 5, 0),
1611        K_GATE(G_CRYP1,         RCC_AHB5ENSETR, 4, 0),
1612        K_GATE(G_GPIOZ,         RCC_AHB5ENSETR, 0, 0),
1613
1614        K_GATE(G_USBH,          RCC_AHB6ENSETR, 24, 0),
1615        K_GATE(G_CRC1,          RCC_AHB6ENSETR, 20, 0),
1616        K_MGATE(G_SDMMC2,       RCC_AHB6ENSETR, 17, 0),
1617        K_MGATE(G_SDMMC1,       RCC_AHB6ENSETR, 16, 0),
1618        K_MGATE(G_QSPI,         RCC_AHB6ENSETR, 14, 0),
1619        K_MGATE(G_FMC,          RCC_AHB6ENSETR, 12, 0),
1620        K_GATE(G_ETHMAC,        RCC_AHB6ENSETR, 10, 0),
1621        K_GATE(G_ETHRX,         RCC_AHB6ENSETR, 9, 0),
1622        K_GATE(G_ETHTX,         RCC_AHB6ENSETR, 8, 0),
1623        K_GATE(G_ETHCK,         RCC_AHB6ENSETR, 7, 0),
1624        K_MGATE(G_GPU,          RCC_AHB6ENSETR, 5, 0),
1625        K_GATE(G_MDMA,          RCC_AHB6ENSETR, 0, 0),
1626        K_GATE(G_ETHSTP,        RCC_AHB6LPENSETR, 11, 0),
1627};
1628
1629enum {
1630        M_SDMMC12,
1631        M_SDMMC3,
1632        M_FMC,
1633        M_QSPI,
1634        M_RNG1,
1635        M_RNG2,
1636        M_USBPHY,
1637        M_USBO,
1638        M_STGEN,
1639        M_SPDIF,
1640        M_SPI1,
1641        M_SPI23,
1642        M_SPI45,
1643        M_SPI6,
1644        M_CEC,
1645        M_I2C12,
1646        M_I2C35,
1647        M_I2C46,
1648        M_LPTIM1,
1649        M_LPTIM23,
1650        M_LPTIM45,
1651        M_USART1,
1652        M_UART24,
1653        M_UART35,
1654        M_USART6,
1655        M_UART78,
1656        M_SAI1,
1657        M_SAI2,
1658        M_SAI3,
1659        M_SAI4,
1660        M_DSI,
1661        M_FDCAN,
1662        M_ADC12,
1663        M_ETHCK,
1664        M_CKPER,
1665        M_LAST
1666};
1667
1668static struct stm32_mmux ker_mux[M_LAST];
1669
1670#define _K_MUX(_id, _offset, _shift, _width, _mux_flags, _mmux, _ops)\
1671        [_id] = {\
1672                &(struct mux_cfg) {\
1673                        .reg_off        = _offset,\
1674                        .shift          = _shift,\
1675                        .width          = _width,\
1676                        .mux_flags      = _mux_flags,\
1677                        .table          = NULL,\
1678                },\
1679                .mmux           = _mmux,\
1680                .ops            = _ops,\
1681        }
1682
1683#define K_MUX(_id, _offset, _shift, _width, _mux_flags)\
1684        _K_MUX(_id, _offset, _shift, _width, _mux_flags,\
1685                        NULL, NULL)
1686
1687#define K_MMUX(_id, _offset, _shift, _width, _mux_flags)\
1688        _K_MUX(_id, _offset, _shift, _width, _mux_flags,\
1689                        &ker_mux[_id], &clk_mmux_ops)
1690
1691static const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
1692        /* Kernel multi mux */
1693        K_MMUX(M_SDMMC12, RCC_SDMMC12CKSELR, 0, 3, 0),
1694        K_MMUX(M_SPI23, RCC_SPI2S23CKSELR, 0, 3, 0),
1695        K_MMUX(M_SPI45, RCC_SPI2S45CKSELR, 0, 3, 0),
1696        K_MMUX(M_I2C12, RCC_I2C12CKSELR, 0, 3, 0),
1697        K_MMUX(M_I2C35, RCC_I2C35CKSELR, 0, 3, 0),
1698        K_MMUX(M_LPTIM23, RCC_LPTIM23CKSELR, 0, 3, 0),
1699        K_MMUX(M_LPTIM45, RCC_LPTIM45CKSELR, 0, 3, 0),
1700        K_MMUX(M_UART24, RCC_UART24CKSELR, 0, 3, 0),
1701        K_MMUX(M_UART35, RCC_UART35CKSELR, 0, 3, 0),
1702        K_MMUX(M_UART78, RCC_UART78CKSELR, 0, 3, 0),
1703        K_MMUX(M_SAI1, RCC_SAI1CKSELR, 0, 3, 0),
1704        K_MMUX(M_ETHCK, RCC_ETHCKSELR, 0, 2, 0),
1705        K_MMUX(M_I2C46, RCC_I2C46CKSELR, 0, 3, 0),
1706
1707        /*  Kernel simple mux */
1708        K_MUX(M_RNG2, RCC_RNG2CKSELR, 0, 2, 0),
1709        K_MUX(M_SDMMC3, RCC_SDMMC3CKSELR, 0, 3, 0),
1710        K_MUX(M_FMC, RCC_FMCCKSELR, 0, 2, 0),
1711        K_MUX(M_QSPI, RCC_QSPICKSELR, 0, 2, 0),
1712        K_MUX(M_USBPHY, RCC_USBCKSELR, 0, 2, 0),
1713        K_MUX(M_USBO, RCC_USBCKSELR, 4, 1, 0),
1714        K_MUX(M_SPDIF, RCC_SPDIFCKSELR, 0, 2, 0),
1715        K_MUX(M_SPI1, RCC_SPI2S1CKSELR, 0, 3, 0),
1716        K_MUX(M_CEC, RCC_CECCKSELR, 0, 2, 0),
1717        K_MUX(M_LPTIM1, RCC_LPTIM1CKSELR, 0, 3, 0),
1718        K_MUX(M_USART6, RCC_UART6CKSELR, 0, 3, 0),
1719        K_MUX(M_FDCAN, RCC_FDCANCKSELR, 0, 2, 0),
1720        K_MUX(M_SAI2, RCC_SAI2CKSELR, 0, 3, 0),
1721        K_MUX(M_SAI3, RCC_SAI3CKSELR, 0, 3, 0),
1722        K_MUX(M_SAI4, RCC_SAI4CKSELR, 0, 3, 0),
1723        K_MUX(M_ADC12, RCC_ADCCKSELR, 0, 2, 0),
1724        K_MUX(M_DSI, RCC_DSICKSELR, 0, 1, 0),
1725        K_MUX(M_CKPER, RCC_CPERCKSELR, 0, 2, 0),
1726        K_MUX(M_RNG1, RCC_RNG1CKSELR, 0, 2, 0),
1727        K_MUX(M_STGEN, RCC_STGENCKSELR, 0, 2, 0),
1728        K_MUX(M_USART1, RCC_UART1CKSELR, 0, 3, 0),
1729        K_MUX(M_SPI6, RCC_SPI6CKSELR, 0, 3, 0),
1730};
1731
1732static const struct clock_config stm32mp1_clock_cfg[] = {
1733        /*  External / Internal Oscillators */
1734        GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0),
1735        /* ck_csi is used by IO compensation and should be critical */
1736        GATE_MP1(CK_CSI, "ck_csi", "clk-csi", CLK_IS_CRITICAL,
1737                 RCC_OCENSETR, 4, 0),
1738        COMPOSITE(CK_HSI, "ck_hsi", PARENT("clk-hsi"), 0,
1739                  _GATE_MP1(RCC_OCENSETR, 0, 0),
1740                  _NO_MUX,
1741                  _DIV(RCC_HSICFGR, 0, 2, CLK_DIVIDER_POWER_OF_TWO |
1742                       CLK_DIVIDER_READ_ONLY, NULL)),
1743        GATE(CK_LSI, "ck_lsi", "clk-lsi", 0, RCC_RDLSICR, 0, 0),
1744        GATE(CK_LSE, "ck_lse", "clk-lse", 0, RCC_BDCR, 0, 0),
1745
1746        FIXED_FACTOR(CK_HSE_DIV2, "clk-hse-div2", "ck_hse", 0, 1, 2),
1747
1748        /* PLLs */
1749        PLL(PLL1, "pll1", ref12_parents, 0, RCC_PLL1CR, RCC_RCK12SELR),
1750        PLL(PLL2, "pll2", ref12_parents, 0, RCC_PLL2CR, RCC_RCK12SELR),
1751        PLL(PLL3, "pll3", ref3_parents, 0, RCC_PLL3CR, RCC_RCK3SELR),
1752        PLL(PLL4, "pll4", ref4_parents, 0, RCC_PLL4CR, RCC_RCK4SELR),
1753
1754        /* ODF */
1755        COMPOSITE(PLL1_P, "pll1_p", PARENT("pll1"), 0,
1756                  _GATE(RCC_PLL1CR, 4, 0),
1757                  _NO_MUX,
1758                  _DIV(RCC_PLL1CFGR2, 0, 7, 0, NULL)),
1759
1760        COMPOSITE(PLL2_P, "pll2_p", PARENT("pll2"), 0,
1761                  _GATE(RCC_PLL2CR, 4, 0),
1762                  _NO_MUX,
1763                  _DIV(RCC_PLL2CFGR2, 0, 7, 0, NULL)),
1764
1765        COMPOSITE(PLL2_Q, "pll2_q", PARENT("pll2"), 0,
1766                  _GATE(RCC_PLL2CR, 5, 0),
1767                  _NO_MUX,
1768                  _DIV(RCC_PLL2CFGR2, 8, 7, 0, NULL)),
1769
1770        COMPOSITE(PLL2_R, "pll2_r", PARENT("pll2"), CLK_IS_CRITICAL,
1771                  _GATE(RCC_PLL2CR, 6, 0),
1772                  _NO_MUX,
1773                  _DIV(RCC_PLL2CFGR2, 16, 7, 0, NULL)),
1774
1775        COMPOSITE(PLL3_P, "pll3_p", PARENT("pll3"), 0,
1776                  _GATE(RCC_PLL3CR, 4, 0),
1777                  _NO_MUX,
1778                  _DIV(RCC_PLL3CFGR2, 0, 7, 0, NULL)),
1779
1780        COMPOSITE(PLL3_Q, "pll3_q", PARENT("pll3"), 0,
1781                  _GATE(RCC_PLL3CR, 5, 0),
1782                  _NO_MUX,
1783                  _DIV(RCC_PLL3CFGR2, 8, 7, 0, NULL)),
1784
1785        COMPOSITE(PLL3_R, "pll3_r", PARENT("pll3"), 0,
1786                  _GATE(RCC_PLL3CR, 6, 0),
1787                  _NO_MUX,
1788                  _DIV(RCC_PLL3CFGR2, 16, 7, 0, NULL)),
1789
1790        COMPOSITE(PLL4_P, "pll4_p", PARENT("pll4"), 0,
1791                  _GATE(RCC_PLL4CR, 4, 0),
1792                  _NO_MUX,
1793                  _DIV(RCC_PLL4CFGR2, 0, 7, 0, NULL)),
1794
1795        COMPOSITE(PLL4_Q, "pll4_q", PARENT("pll4"), 0,
1796                  _GATE(RCC_PLL4CR, 5, 0),
1797                  _NO_MUX,
1798                  _DIV(RCC_PLL4CFGR2, 8, 7, 0, NULL)),
1799
1800        COMPOSITE(PLL4_R, "pll4_r", PARENT("pll4"), 0,
1801                  _GATE(RCC_PLL4CR, 6, 0),
1802                  _NO_MUX,
1803                  _DIV(RCC_PLL4CFGR2, 16, 7, 0, NULL)),
1804
1805        /* MUX system clocks */
1806        MUX(CK_PER, "ck_per", per_src, CLK_OPS_PARENT_ENABLE,
1807            RCC_CPERCKSELR, 0, 2, 0),
1808
1809        MUX(CK_MPU, "ck_mpu", cpu_src, CLK_OPS_PARENT_ENABLE |
1810             CLK_IS_CRITICAL, RCC_MPCKSELR, 0, 2, 0),
1811
1812        COMPOSITE(CK_AXI, "ck_axi", axi_src, CLK_IS_CRITICAL |
1813                   CLK_OPS_PARENT_ENABLE,
1814                   _NO_GATE,
1815                   _MUX(RCC_ASSCKSELR, 0, 2, 0),
1816                   _DIV(RCC_AXIDIVR, 0, 3, 0, axi_div_table)),
1817
1818        COMPOSITE(CK_MCU, "ck_mcu", mcu_src, CLK_IS_CRITICAL |
1819                   CLK_OPS_PARENT_ENABLE,
1820                   _NO_GATE,
1821                   _MUX(RCC_MSSCKSELR, 0, 2, 0),
1822                   _DIV(RCC_MCUDIVR, 0, 4, 0, mcu_div_table)),
1823
1824        DIV_TABLE(NO_ID, "pclk1", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB1DIVR, 0,
1825                  3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1826
1827        DIV_TABLE(NO_ID, "pclk2", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB2DIVR, 0,
1828                  3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1829
1830        DIV_TABLE(NO_ID, "pclk3", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB3DIVR, 0,
1831                  3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1832
1833        DIV_TABLE(NO_ID, "pclk4", "ck_axi", CLK_IGNORE_UNUSED, RCC_APB4DIVR, 0,
1834                  3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1835
1836        DIV_TABLE(NO_ID, "pclk5", "ck_axi", CLK_IGNORE_UNUSED, RCC_APB5DIVR, 0,
1837                  3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1838
1839        /* Kernel Timers */
1840        STM32_CKTIM("ck1_tim", "pclk1", 0, RCC_APB1DIVR, RCC_TIMG1PRER),
1841        STM32_CKTIM("ck2_tim", "pclk2", 0, RCC_APB2DIVR, RCC_TIMG2PRER),
1842
1843        STM32_TIM(TIM2_K, "tim2_k", "ck1_tim", RCC_APB1ENSETR, 0),
1844        STM32_TIM(TIM3_K, "tim3_k", "ck1_tim", RCC_APB1ENSETR, 1),
1845        STM32_TIM(TIM4_K, "tim4_k", "ck1_tim", RCC_APB1ENSETR, 2),
1846        STM32_TIM(TIM5_K, "tim5_k", "ck1_tim", RCC_APB1ENSETR, 3),
1847        STM32_TIM(TIM6_K, "tim6_k", "ck1_tim", RCC_APB1ENSETR, 4),
1848        STM32_TIM(TIM7_K, "tim7_k", "ck1_tim", RCC_APB1ENSETR, 5),
1849        STM32_TIM(TIM12_K, "tim12_k", "ck1_tim", RCC_APB1ENSETR, 6),
1850        STM32_TIM(TIM13_K, "tim13_k", "ck1_tim", RCC_APB1ENSETR, 7),
1851        STM32_TIM(TIM14_K, "tim14_k", "ck1_tim", RCC_APB1ENSETR, 8),
1852        STM32_TIM(TIM1_K, "tim1_k", "ck2_tim", RCC_APB2ENSETR, 0),
1853        STM32_TIM(TIM8_K, "tim8_k", "ck2_tim", RCC_APB2ENSETR, 1),
1854        STM32_TIM(TIM15_K, "tim15_k", "ck2_tim", RCC_APB2ENSETR, 2),
1855        STM32_TIM(TIM16_K, "tim16_k", "ck2_tim", RCC_APB2ENSETR, 3),
1856        STM32_TIM(TIM17_K, "tim17_k", "ck2_tim", RCC_APB2ENSETR, 4),
1857
1858        /* Peripheral clocks */
1859        PCLK(TIM2, "tim2", "pclk1", CLK_IGNORE_UNUSED, G_TIM2),
1860        PCLK(TIM3, "tim3", "pclk1", CLK_IGNORE_UNUSED, G_TIM3),
1861        PCLK(TIM4, "tim4", "pclk1", CLK_IGNORE_UNUSED, G_TIM4),
1862        PCLK(TIM5, "tim5", "pclk1", CLK_IGNORE_UNUSED, G_TIM5),
1863        PCLK(TIM6, "tim6", "pclk1", CLK_IGNORE_UNUSED, G_TIM6),
1864        PCLK(TIM7, "tim7", "pclk1", CLK_IGNORE_UNUSED, G_TIM7),
1865        PCLK(TIM12, "tim12", "pclk1", CLK_IGNORE_UNUSED, G_TIM12),
1866        PCLK(TIM13, "tim13", "pclk1", CLK_IGNORE_UNUSED, G_TIM13),
1867        PCLK(TIM14, "tim14", "pclk1", CLK_IGNORE_UNUSED, G_TIM14),
1868        PCLK(LPTIM1, "lptim1", "pclk1", 0, G_LPTIM1),
1869        PCLK(SPI2, "spi2", "pclk1", 0, G_SPI2),
1870        PCLK(SPI3, "spi3", "pclk1", 0, G_SPI3),
1871        PCLK(USART2, "usart2", "pclk1", 0, G_USART2),
1872        PCLK(USART3, "usart3", "pclk1", 0, G_USART3),
1873        PCLK(UART4, "uart4", "pclk1", 0, G_UART4),
1874        PCLK(UART5, "uart5", "pclk1", 0, G_UART5),
1875        PCLK(UART7, "uart7", "pclk1", 0, G_UART7),
1876        PCLK(UART8, "uart8", "pclk1", 0, G_UART8),
1877        PCLK(I2C1, "i2c1", "pclk1", 0, G_I2C1),
1878        PCLK(I2C2, "i2c2", "pclk1", 0, G_I2C2),
1879        PCLK(I2C3, "i2c3", "pclk1", 0, G_I2C3),
1880        PCLK(I2C5, "i2c5", "pclk1", 0, G_I2C5),
1881        PCLK(SPDIF, "spdif", "pclk1", 0, G_SPDIF),
1882        PCLK(CEC, "cec", "pclk1", 0, G_CEC),
1883        PCLK(DAC12, "dac12", "pclk1", 0, G_DAC12),
1884        PCLK(MDIO, "mdio", "pclk1", 0, G_MDIO),
1885        PCLK(TIM1, "tim1", "pclk2", CLK_IGNORE_UNUSED, G_TIM1),
1886        PCLK(TIM8, "tim8", "pclk2", CLK_IGNORE_UNUSED, G_TIM8),
1887        PCLK(TIM15, "tim15", "pclk2", CLK_IGNORE_UNUSED, G_TIM15),
1888        PCLK(TIM16, "tim16", "pclk2", CLK_IGNORE_UNUSED, G_TIM16),
1889        PCLK(TIM17, "tim17", "pclk2", CLK_IGNORE_UNUSED, G_TIM17),
1890        PCLK(SPI1, "spi1", "pclk2", 0, G_SPI1),
1891        PCLK(SPI4, "spi4", "pclk2", 0, G_SPI4),
1892        PCLK(SPI5, "spi5", "pclk2", 0, G_SPI5),
1893        PCLK(USART6, "usart6", "pclk2", 0, G_USART6),
1894        PCLK(SAI1, "sai1", "pclk2", 0, G_SAI1),
1895        PCLK(SAI2, "sai2", "pclk2", 0, G_SAI2),
1896        PCLK(SAI3, "sai3", "pclk2", 0, G_SAI3),
1897        PCLK(DFSDM, "dfsdm", "pclk2", 0, G_DFSDM),
1898        PCLK(FDCAN, "fdcan", "pclk2", 0, G_FDCAN),
1899        PCLK(LPTIM2, "lptim2", "pclk3", 0, G_LPTIM2),
1900        PCLK(LPTIM3, "lptim3", "pclk3", 0, G_LPTIM3),
1901        PCLK(LPTIM4, "lptim4", "pclk3", 0, G_LPTIM4),
1902        PCLK(LPTIM5, "lptim5", "pclk3", 0, G_LPTIM5),
1903        PCLK(SAI4, "sai4", "pclk3", 0, G_SAI4),
1904        PCLK(SYSCFG, "syscfg", "pclk3", 0, G_SYSCFG),
1905        PCLK(VREF, "vref", "pclk3", 13, G_VREF),
1906        PCLK(TMPSENS, "tmpsens", "pclk3", 0, G_TMPSENS),
1907        PCLK(PMBCTRL, "pmbctrl", "pclk3", 0, G_PMBCTRL),
1908        PCLK(HDP, "hdp", "pclk3", 0, G_HDP),
1909        PCLK(LTDC, "ltdc", "pclk4", 0, G_LTDC),
1910        PCLK(DSI, "dsi", "pclk4", 0, G_DSI),
1911        PCLK(IWDG2, "iwdg2", "pclk4", 0, G_IWDG2),
1912        PCLK(USBPHY, "usbphy", "pclk4", 0, G_USBPHY),
1913        PCLK(STGENRO, "stgenro", "pclk4", 0, G_STGENRO),
1914        PCLK(SPI6, "spi6", "pclk5", 0, G_SPI6),
1915        PCLK(I2C4, "i2c4", "pclk5", 0, G_I2C4),
1916        PCLK(I2C6, "i2c6", "pclk5", 0, G_I2C6),
1917        PCLK(USART1, "usart1", "pclk5", 0, G_USART1),
1918        PCLK(RTCAPB, "rtcapb", "pclk5", CLK_IGNORE_UNUSED |
1919             CLK_IS_CRITICAL, G_RTCAPB),
1920        PCLK(TZC1, "tzc1", "ck_axi", CLK_IGNORE_UNUSED, G_TZC1),
1921        PCLK(TZC2, "tzc2", "ck_axi", CLK_IGNORE_UNUSED, G_TZC2),
1922        PCLK(TZPC, "tzpc", "pclk5", CLK_IGNORE_UNUSED, G_TZPC),
1923        PCLK(IWDG1, "iwdg1", "pclk5", 0, G_IWDG1),
1924        PCLK(BSEC, "bsec", "pclk5", CLK_IGNORE_UNUSED, G_BSEC),
1925        PCLK(STGEN, "stgen", "pclk5", CLK_IGNORE_UNUSED, G_STGEN),
1926        PCLK(DMA1, "dma1", "ck_mcu", 0, G_DMA1),
1927        PCLK(DMA2, "dma2", "ck_mcu",  0, G_DMA2),
1928        PCLK(DMAMUX, "dmamux", "ck_mcu", 0, G_DMAMUX),
1929        PCLK(ADC12, "adc12", "ck_mcu", 0, G_ADC12),
1930        PCLK(USBO, "usbo", "ck_mcu", 0, G_USBO),
1931        PCLK(SDMMC3, "sdmmc3", "ck_mcu", 0, G_SDMMC3),
1932        PCLK(DCMI, "dcmi", "ck_mcu", 0, G_DCMI),
1933        PCLK(CRYP2, "cryp2", "ck_mcu", 0, G_CRYP2),
1934        PCLK(HASH2, "hash2", "ck_mcu", 0, G_HASH2),
1935        PCLK(RNG2, "rng2", "ck_mcu", 0, G_RNG2),
1936        PCLK(CRC2, "crc2", "ck_mcu", 0, G_CRC2),
1937        PCLK(HSEM, "hsem", "ck_mcu", 0, G_HSEM),
1938        PCLK(IPCC, "ipcc", "ck_mcu", 0, G_IPCC),
1939        PCLK(GPIOA, "gpioa", "ck_mcu", 0, G_GPIOA),
1940        PCLK(GPIOB, "gpiob", "ck_mcu", 0, G_GPIOB),
1941        PCLK(GPIOC, "gpioc", "ck_mcu", 0, G_GPIOC),
1942        PCLK(GPIOD, "gpiod", "ck_mcu", 0, G_GPIOD),
1943        PCLK(GPIOE, "gpioe", "ck_mcu", 0, G_GPIOE),
1944        PCLK(GPIOF, "gpiof", "ck_mcu", 0, G_GPIOF),
1945        PCLK(GPIOG, "gpiog", "ck_mcu", 0, G_GPIOG),
1946        PCLK(GPIOH, "gpioh", "ck_mcu", 0, G_GPIOH),
1947        PCLK(GPIOI, "gpioi", "ck_mcu", 0, G_GPIOI),
1948        PCLK(GPIOJ, "gpioj", "ck_mcu", 0, G_GPIOJ),
1949        PCLK(GPIOK, "gpiok", "ck_mcu", 0, G_GPIOK),
1950        PCLK(GPIOZ, "gpioz", "ck_axi", CLK_IGNORE_UNUSED, G_GPIOZ),
1951        PCLK(CRYP1, "cryp1", "ck_axi", CLK_IGNORE_UNUSED, G_CRYP1),
1952        PCLK(HASH1, "hash1", "ck_axi", CLK_IGNORE_UNUSED, G_HASH1),
1953        PCLK(RNG1, "rng1", "ck_axi", 0, G_RNG1),
1954        PCLK(BKPSRAM, "bkpsram", "ck_axi", CLK_IGNORE_UNUSED, G_BKPSRAM),
1955        PCLK(MDMA, "mdma", "ck_axi", 0, G_MDMA),
1956        PCLK(GPU, "gpu", "ck_axi", 0, G_GPU),
1957        PCLK(ETHTX, "ethtx", "ck_axi", 0, G_ETHTX),
1958        PCLK(ETHRX, "ethrx", "ck_axi", 0, G_ETHRX),
1959        PCLK(ETHMAC, "ethmac", "ck_axi", 0, G_ETHMAC),
1960        PCLK(FMC, "fmc", "ck_axi", CLK_IGNORE_UNUSED, G_FMC),
1961        PCLK(QSPI, "qspi", "ck_axi", CLK_IGNORE_UNUSED, G_QSPI),
1962        PCLK(SDMMC1, "sdmmc1", "ck_axi", 0, G_SDMMC1),
1963        PCLK(SDMMC2, "sdmmc2", "ck_axi", 0, G_SDMMC2),
1964        PCLK(CRC1, "crc1", "ck_axi", 0, G_CRC1),
1965        PCLK(USBH, "usbh", "ck_axi", 0, G_USBH),
1966        PCLK(ETHSTP, "ethstp", "ck_axi", 0, G_ETHSTP),
1967        PCLK(DDRPERFM, "ddrperfm", "pclk4", 0, G_DDRPERFM),
1968
1969        /* Kernel clocks */
1970        KCLK(SDMMC1_K, "sdmmc1_k", sdmmc12_src, 0, G_SDMMC1, M_SDMMC12),
1971        KCLK(SDMMC2_K, "sdmmc2_k", sdmmc12_src, 0, G_SDMMC2, M_SDMMC12),
1972        KCLK(SDMMC3_K, "sdmmc3_k", sdmmc3_src, 0, G_SDMMC3, M_SDMMC3),
1973        KCLK(FMC_K, "fmc_k", fmc_src, 0, G_FMC, M_FMC),
1974        KCLK(QSPI_K, "qspi_k", qspi_src, 0, G_QSPI, M_QSPI),
1975        KCLK(RNG1_K, "rng1_k", rng_src, 0, G_RNG1, M_RNG1),
1976        KCLK(RNG2_K, "rng2_k", rng_src, 0, G_RNG2, M_RNG2),
1977        KCLK(USBPHY_K, "usbphy_k", usbphy_src, 0, G_USBPHY, M_USBPHY),
1978        KCLK(STGEN_K, "stgen_k", stgen_src, CLK_IS_CRITICAL, G_STGEN, M_STGEN),
1979        KCLK(SPDIF_K, "spdif_k", spdif_src, 0, G_SPDIF, M_SPDIF),
1980        KCLK(SPI1_K, "spi1_k", spi123_src, 0, G_SPI1, M_SPI1),
1981        KCLK(SPI2_K, "spi2_k", spi123_src, 0, G_SPI2, M_SPI23),
1982        KCLK(SPI3_K, "spi3_k", spi123_src, 0, G_SPI3, M_SPI23),
1983        KCLK(SPI4_K, "spi4_k", spi45_src, 0, G_SPI4, M_SPI45),
1984        KCLK(SPI5_K, "spi5_k", spi45_src, 0, G_SPI5, M_SPI45),
1985        KCLK(SPI6_K, "spi6_k", spi6_src, 0, G_SPI6, M_SPI6),
1986        KCLK(CEC_K, "cec_k", cec_src, 0, G_CEC, M_CEC),
1987        KCLK(I2C1_K, "i2c1_k", i2c12_src, 0, G_I2C1, M_I2C12),
1988        KCLK(I2C2_K, "i2c2_k", i2c12_src, 0, G_I2C2, M_I2C12),
1989        KCLK(I2C3_K, "i2c3_k", i2c35_src, 0, G_I2C3, M_I2C35),
1990        KCLK(I2C5_K, "i2c5_k", i2c35_src, 0, G_I2C5, M_I2C35),
1991        KCLK(I2C4_K, "i2c4_k", i2c46_src, 0, G_I2C4, M_I2C46),
1992        KCLK(I2C6_K, "i2c6_k", i2c46_src, 0, G_I2C6, M_I2C46),
1993        KCLK(LPTIM1_K, "lptim1_k", lptim1_src, 0, G_LPTIM1, M_LPTIM1),
1994        KCLK(LPTIM2_K, "lptim2_k", lptim23_src, 0, G_LPTIM2, M_LPTIM23),
1995        KCLK(LPTIM3_K, "lptim3_k", lptim23_src, 0, G_LPTIM3, M_LPTIM23),
1996        KCLK(LPTIM4_K, "lptim4_k", lptim45_src, 0, G_LPTIM4, M_LPTIM45),
1997        KCLK(LPTIM5_K, "lptim5_k", lptim45_src, 0, G_LPTIM5, M_LPTIM45),
1998        KCLK(USART1_K, "usart1_k", usart1_src, 0, G_USART1, M_USART1),
1999        KCLK(USART2_K, "usart2_k", usart234578_src, 0, G_USART2, M_UART24),
2000        KCLK(USART3_K, "usart3_k", usart234578_src, 0, G_USART3, M_UART35),
2001        KCLK(UART4_K, "uart4_k", usart234578_src, 0, G_UART4, M_UART24),
2002        KCLK(UART5_K, "uart5_k", usart234578_src, 0, G_UART5, M_UART35),
2003        KCLK(USART6_K, "uart6_k", usart6_src, 0, G_USART6, M_USART6),
2004        KCLK(UART7_K, "uart7_k", usart234578_src, 0, G_UART7, M_UART78),
2005        KCLK(UART8_K, "uart8_k", usart234578_src, 0, G_UART8, M_UART78),
2006        KCLK(FDCAN_K, "fdcan_k", fdcan_src, 0, G_FDCAN, M_FDCAN),
2007        KCLK(SAI1_K, "sai1_k", sai_src, 0, G_SAI1, M_SAI1),
2008        KCLK(SAI2_K, "sai2_k", sai2_src, 0, G_SAI2, M_SAI2),
2009        KCLK(SAI3_K, "sai3_k", sai_src, 0, G_SAI3, M_SAI3),
2010        KCLK(SAI4_K, "sai4_k", sai_src, 0, G_SAI4, M_SAI4),
2011        KCLK(ADC12_K, "adc12_k", adc12_src, 0, G_ADC12, M_ADC12),
2012        KCLK(DSI_K, "dsi_k", dsi_src, 0, G_DSI, M_DSI),
2013        KCLK(ADFSDM_K, "adfsdm_k", sai_src, 0, G_ADFSDM, M_SAI1),
2014        KCLK(USBO_K, "usbo_k", usbo_src, 0, G_USBO, M_USBO),
2015        KCLK(ETHCK_K, "ethck_k", eth_src, 0, G_ETHCK, M_ETHCK),
2016
2017        /* Particulary Kernel Clocks (no mux or no gate) */
2018        MGATE_MP1(DFSDM_K, "dfsdm_k", "ck_mcu", 0, G_DFSDM),
2019        MGATE_MP1(DSI_PX, "dsi_px", "pll4_q", CLK_SET_RATE_PARENT, G_DSI),
2020        MGATE_MP1(LTDC_PX, "ltdc_px", "pll4_q", CLK_SET_RATE_PARENT, G_LTDC),
2021        MGATE_MP1(GPU_K, "gpu_k", "pll2_q", 0, G_GPU),
2022        MGATE_MP1(DAC12_K, "dac12_k", "ck_lsi", 0, G_DAC12),
2023
2024        COMPOSITE(ETHPTP_K, "ethptp_k", eth_src, CLK_OPS_PARENT_ENABLE |
2025                  CLK_SET_RATE_NO_REPARENT,
2026                  _NO_GATE,
2027                  _MMUX(M_ETHCK),
2028                  _DIV(RCC_ETHCKSELR, 4, 4, 0, NULL)),
2029
2030        /* RTC clock */
2031        COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE,
2032                  _GATE(RCC_BDCR, 20, 0),
2033                  _MUX(RCC_BDCR, 16, 2, 0),
2034                  _DIV_RTC(RCC_RTCDIVR, 0, 6, 0, NULL)),
2035
2036        /* MCO clocks */
2037        COMPOSITE(CK_MCO1, "ck_mco1", mco1_src, CLK_OPS_PARENT_ENABLE |
2038                  CLK_SET_RATE_NO_REPARENT,
2039                  _GATE(RCC_MCO1CFGR, 12, 0),
2040                  _MUX(RCC_MCO1CFGR, 0, 3, 0),
2041                  _DIV(RCC_MCO1CFGR, 4, 4, 0, NULL)),
2042
2043        COMPOSITE(CK_MCO2, "ck_mco2", mco2_src, CLK_OPS_PARENT_ENABLE |
2044                  CLK_SET_RATE_NO_REPARENT,
2045                  _GATE(RCC_MCO2CFGR, 12, 0),
2046                  _MUX(RCC_MCO2CFGR, 0, 3, 0),
2047                  _DIV(RCC_MCO2CFGR, 4, 4, 0, NULL)),
2048
2049        /* Debug clocks */
2050        GATE(CK_DBG, "ck_sys_dbg", "ck_axi", CLK_IGNORE_UNUSED,
2051             RCC_DBGCFGR, 8, 0),
2052
2053        COMPOSITE(CK_TRACE, "ck_trace", ck_trace_src, CLK_OPS_PARENT_ENABLE,
2054                  _GATE(RCC_DBGCFGR, 9, 0),
2055                  _NO_MUX,
2056                  _DIV(RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table)),
2057};
2058
2059static const u32 stm32mp1_clock_secured[] = {
2060        CK_HSE,
2061        CK_HSI,
2062        CK_CSI,
2063        CK_LSI,
2064        CK_LSE,
2065        PLL1,
2066        PLL2,
2067        PLL1_P,
2068        PLL2_P,
2069        PLL2_Q,
2070        PLL2_R,
2071        CK_MPU,
2072        CK_AXI,
2073        SPI6,
2074        I2C4,
2075        I2C6,
2076        USART1,
2077        RTCAPB,
2078        TZC1,
2079        TZC2,
2080        TZPC,
2081        IWDG1,
2082        BSEC,
2083        STGEN,
2084        GPIOZ,
2085        CRYP1,
2086        HASH1,
2087        RNG1,
2088        BKPSRAM,
2089        RNG1_K,
2090        STGEN_K,
2091        SPI6_K,
2092        I2C4_K,
2093        I2C6_K,
2094        USART1_K,
2095        RTC,
2096};
2097
2098static bool stm32_check_security(const struct clock_config *cfg)
2099{
2100        int i;
2101
2102        for (i = 0; i < ARRAY_SIZE(stm32mp1_clock_secured); i++)
2103                if (cfg->id == stm32mp1_clock_secured[i])
2104                        return true;
2105        return false;
2106}
2107
2108struct stm32_rcc_match_data {
2109        const struct clock_config *cfg;
2110        unsigned int num;
2111        unsigned int maxbinding;
2112        u32 clear_offset;
2113        bool (*check_security)(const struct clock_config *cfg);
2114};
2115
2116static struct stm32_rcc_match_data stm32mp1_data = {
2117        .cfg            = stm32mp1_clock_cfg,
2118        .num            = ARRAY_SIZE(stm32mp1_clock_cfg),
2119        .maxbinding     = STM32MP1_LAST_CLK,
2120        .clear_offset   = RCC_CLR,
2121};
2122
2123static struct stm32_rcc_match_data stm32mp1_data_secure = {
2124        .cfg            = stm32mp1_clock_cfg,
2125        .num            = ARRAY_SIZE(stm32mp1_clock_cfg),
2126        .maxbinding     = STM32MP1_LAST_CLK,
2127        .clear_offset   = RCC_CLR,
2128        .check_security = &stm32_check_security
2129};
2130
2131static const struct of_device_id stm32mp1_match_data[] = {
2132        {
2133                .compatible = "st,stm32mp1-rcc",
2134                .data = &stm32mp1_data,
2135        },
2136        {
2137                .compatible = "st,stm32mp1-rcc-secure",
2138                .data = &stm32mp1_data_secure,
2139        },
2140        { }
2141};
2142MODULE_DEVICE_TABLE(of, stm32mp1_match_data);
2143
2144static int stm32_register_hw_clk(struct device *dev,
2145                                 struct clk_hw_onecell_data *clk_data,
2146                                 void __iomem *base, spinlock_t *lock,
2147                                 const struct clock_config *cfg)
2148{
2149        struct clk_hw **hws;
2150        struct clk_hw *hw = ERR_PTR(-ENOENT);
2151
2152        hws = clk_data->hws;
2153
2154        if (cfg->func)
2155                hw = (*cfg->func)(dev, clk_data, base, lock, cfg);
2156
2157        if (IS_ERR(hw)) {
2158                pr_err("Unable to register %s\n", cfg->name);
2159                return  PTR_ERR(hw);
2160        }
2161
2162        if (cfg->id != NO_ID)
2163                hws[cfg->id] = hw;
2164
2165        return 0;
2166}
2167
2168#define STM32_RESET_ID_MASK GENMASK(15, 0)
2169
2170struct stm32_reset_data {
2171        /* reset lock */
2172        spinlock_t                      lock;
2173        struct reset_controller_dev     rcdev;
2174        void __iomem                    *membase;
2175        u32                             clear_offset;
2176};
2177
2178static inline struct stm32_reset_data *
2179to_stm32_reset_data(struct reset_controller_dev *rcdev)
2180{
2181        return container_of(rcdev, struct stm32_reset_data, rcdev);
2182}
2183
2184static int stm32_reset_update(struct reset_controller_dev *rcdev,
2185                              unsigned long id, bool assert)
2186{
2187        struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
2188        int reg_width = sizeof(u32);
2189        int bank = id / (reg_width * BITS_PER_BYTE);
2190        int offset = id % (reg_width * BITS_PER_BYTE);
2191
2192        if (data->clear_offset) {
2193                void __iomem *addr;
2194
2195                addr = data->membase + (bank * reg_width);
2196                if (!assert)
2197                        addr += data->clear_offset;
2198
2199                writel(BIT(offset), addr);
2200
2201        } else {
2202                unsigned long flags;
2203                u32 reg;
2204
2205                spin_lock_irqsave(&data->lock, flags);
2206
2207                reg = readl(data->membase + (bank * reg_width));
2208
2209                if (assert)
2210                        reg |= BIT(offset);
2211                else
2212                        reg &= ~BIT(offset);
2213
2214                writel(reg, data->membase + (bank * reg_width));
2215
2216                spin_unlock_irqrestore(&data->lock, flags);
2217        }
2218
2219        return 0;
2220}
2221
2222static int stm32_reset_assert(struct reset_controller_dev *rcdev,
2223                              unsigned long id)
2224{
2225        return stm32_reset_update(rcdev, id, true);
2226}
2227
2228static int stm32_reset_deassert(struct reset_controller_dev *rcdev,
2229                                unsigned long id)
2230{
2231        return stm32_reset_update(rcdev, id, false);
2232}
2233
2234static int stm32_reset_status(struct reset_controller_dev *rcdev,
2235                              unsigned long id)
2236{
2237        struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
2238        int reg_width = sizeof(u32);
2239        int bank = id / (reg_width * BITS_PER_BYTE);
2240        int offset = id % (reg_width * BITS_PER_BYTE);
2241        u32 reg;
2242
2243        reg = readl(data->membase + (bank * reg_width));
2244
2245        return !!(reg & BIT(offset));
2246}
2247
2248static const struct reset_control_ops stm32_reset_ops = {
2249        .assert         = stm32_reset_assert,
2250        .deassert       = stm32_reset_deassert,
2251        .status         = stm32_reset_status,
2252};
2253
2254static int stm32_rcc_reset_init(struct device *dev, void __iomem *base,
2255                                const struct of_device_id *match)
2256{
2257        const struct stm32_rcc_match_data *data = match->data;
2258        struct stm32_reset_data *reset_data = NULL;
2259
2260        data = match->data;
2261
2262        reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
2263        if (!reset_data)
2264                return -ENOMEM;
2265
2266        spin_lock_init(&reset_data->lock);
2267        reset_data->membase = base;
2268        reset_data->rcdev.owner = THIS_MODULE;
2269        reset_data->rcdev.ops = &stm32_reset_ops;
2270        reset_data->rcdev.of_node = dev_of_node(dev);
2271        reset_data->rcdev.nr_resets = STM32_RESET_ID_MASK;
2272        reset_data->clear_offset = data->clear_offset;
2273
2274        return reset_controller_register(&reset_data->rcdev);
2275}
2276
2277static int stm32_rcc_clock_init(struct device *dev, void __iomem *base,
2278                                const struct of_device_id *match)
2279{
2280        const struct stm32_rcc_match_data *data = match->data;
2281        struct clk_hw_onecell_data *clk_data;
2282        struct clk_hw **hws;
2283        int err, n, max_binding;
2284
2285        max_binding =  data->maxbinding;
2286
2287        clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, max_binding),
2288                                GFP_KERNEL);
2289        if (!clk_data)
2290                return -ENOMEM;
2291
2292        clk_data->num = max_binding;
2293
2294        hws = clk_data->hws;
2295
2296        for (n = 0; n < max_binding; n++)
2297                hws[n] = ERR_PTR(-ENOENT);
2298
2299        for (n = 0; n < data->num; n++) {
2300                if (data->check_security && data->check_security(&data->cfg[n]))
2301                        continue;
2302
2303                err = stm32_register_hw_clk(dev, clk_data, base, &rlock,
2304                                            &data->cfg[n]);
2305                if (err) {
2306                        dev_err(dev, "Can't register clk %s: %d\n",
2307                                data->cfg[n].name, err);
2308
2309                        return err;
2310                }
2311        }
2312
2313        return of_clk_add_hw_provider(dev_of_node(dev), of_clk_hw_onecell_get, clk_data);
2314}
2315
2316static int stm32_rcc_init(struct device *dev, void __iomem *base,
2317                          const struct of_device_id *match_data)
2318{
2319        const struct of_device_id *match;
2320        int err;
2321
2322        match = of_match_node(match_data, dev_of_node(dev));
2323        if (!match) {
2324                dev_err(dev, "match data not found\n");
2325                return -ENODEV;
2326        }
2327
2328        /* RCC Reset Configuration */
2329        err = stm32_rcc_reset_init(dev, base, match);
2330        if (err) {
2331                pr_err("stm32mp1 reset failed to initialize\n");
2332                return err;
2333        }
2334
2335        /* RCC Clock Configuration */
2336        err = stm32_rcc_clock_init(dev, base, match);
2337        if (err) {
2338                pr_err("stm32mp1 clock failed to initialize\n");
2339                return err;
2340        }
2341
2342        return 0;
2343}
2344
2345static int stm32mp1_rcc_init(struct device *dev)
2346{
2347        void __iomem *base;
2348        int ret;
2349
2350        base = of_iomap(dev_of_node(dev), 0);
2351        if (!base) {
2352                pr_err("%pOFn: unable to map resource", dev_of_node(dev));
2353                ret = -ENOMEM;
2354                goto out;
2355        }
2356
2357        ret = stm32_rcc_init(dev, base, stm32mp1_match_data);
2358
2359out:
2360        if (ret) {
2361                if (base)
2362                        iounmap(base);
2363
2364                of_node_put(dev_of_node(dev));
2365        }
2366
2367        return ret;
2368}
2369
2370static int get_clock_deps(struct device *dev)
2371{
2372        static const char * const clock_deps_name[] = {
2373                "hsi", "hse", "csi", "lsi", "lse",
2374        };
2375        size_t deps_size = sizeof(struct clk *) * ARRAY_SIZE(clock_deps_name);
2376        struct clk **clk_deps;
2377        int i;
2378
2379        clk_deps = devm_kzalloc(dev, deps_size, GFP_KERNEL);
2380        if (!clk_deps)
2381                return -ENOMEM;
2382
2383        for (i = 0; i < ARRAY_SIZE(clock_deps_name); i++) {
2384                struct clk *clk = of_clk_get_by_name(dev_of_node(dev),
2385                                                     clock_deps_name[i]);
2386
2387                if (IS_ERR(clk)) {
2388                        if (PTR_ERR(clk) != -EINVAL && PTR_ERR(clk) != -ENOENT)
2389                                return PTR_ERR(clk);
2390                } else {
2391                        /* Device gets a reference count on the clock */
2392                        clk_deps[i] = devm_clk_get(dev, __clk_get_name(clk));
2393                        clk_put(clk);
2394                }
2395        }
2396
2397        return 0;
2398}
2399
2400static int stm32mp1_rcc_clocks_probe(struct platform_device *pdev)
2401{
2402        struct device *dev = &pdev->dev;
2403        int ret = get_clock_deps(dev);
2404
2405        if (!ret)
2406                ret = stm32mp1_rcc_init(dev);
2407
2408        return ret;
2409}
2410
2411static int stm32mp1_rcc_clocks_remove(struct platform_device *pdev)
2412{
2413        struct device *dev = &pdev->dev;
2414        struct device_node *child, *np = dev_of_node(dev);
2415
2416        for_each_available_child_of_node(np, child)
2417                of_clk_del_provider(child);
2418
2419        return 0;
2420}
2421
2422static struct platform_driver stm32mp1_rcc_clocks_driver = {
2423        .driver = {
2424                .name = "stm32mp1_rcc",
2425                .of_match_table = stm32mp1_match_data,
2426        },
2427        .probe = stm32mp1_rcc_clocks_probe,
2428        .remove = stm32mp1_rcc_clocks_remove,
2429};
2430
2431static int __init stm32mp1_clocks_init(void)
2432{
2433        return platform_driver_register(&stm32mp1_rcc_clocks_driver);
2434}
2435core_initcall(stm32mp1_clocks_init);
2436