linux/drivers/clk/clk-si5341.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Driver for Silicon Labs Si5340, Si5341, Si5342, Si5344 and Si5345
   4 * Copyright (C) 2019 Topic Embedded Products
   5 * Author: Mike Looijmans <mike.looijmans@topic.nl>
   6 *
   7 * The Si5341 has 10 outputs and 5 synthesizers.
   8 * The Si5340 is a smaller version of the Si5341 with only 4 outputs.
   9 * The Si5345 is similar to the Si5341, with the addition of fractional input
  10 * dividers and automatic input selection.
  11 * The Si5342 and Si5344 are smaller versions of the Si5345.
  12 */
  13
  14#include <linux/clk.h>
  15#include <linux/clk-provider.h>
  16#include <linux/delay.h>
  17#include <linux/gcd.h>
  18#include <linux/math64.h>
  19#include <linux/i2c.h>
  20#include <linux/module.h>
  21#include <linux/regmap.h>
  22#include <linux/regulator/consumer.h>
  23#include <linux/slab.h>
  24#include <asm/unaligned.h>
  25
  26#define SI5341_NUM_INPUTS 4
  27
  28#define SI5340_MAX_NUM_OUTPUTS 4
  29#define SI5341_MAX_NUM_OUTPUTS 10
  30#define SI5342_MAX_NUM_OUTPUTS 2
  31#define SI5344_MAX_NUM_OUTPUTS 4
  32#define SI5345_MAX_NUM_OUTPUTS 10
  33
  34#define SI5340_NUM_SYNTH 4
  35#define SI5341_NUM_SYNTH 5
  36#define SI5342_NUM_SYNTH 2
  37#define SI5344_NUM_SYNTH 4
  38#define SI5345_NUM_SYNTH 5
  39
  40/* Range of the synthesizer fractional divider */
  41#define SI5341_SYNTH_N_MIN      10
  42#define SI5341_SYNTH_N_MAX      4095
  43
  44/* The chip can get its input clock from 3 input pins or an XTAL */
  45
  46/* There is one PLL running at 13500\xE2\x80\x9314256 MHz */
  47#define SI5341_PLL_VCO_MIN 13500000000ull
  48#define SI5341_PLL_VCO_MAX 14256000000ull
  49
  50/* The 5 frequency synthesizers obtain their input from the PLL */
  51struct clk_si5341_synth {
  52        struct clk_hw hw;
  53        struct clk_si5341 *data;
  54        u8 index;
  55};
  56#define to_clk_si5341_synth(_hw) \
  57        container_of(_hw, struct clk_si5341_synth, hw)
  58
  59/* The output stages can be connected to any synth (full mux) */
  60struct clk_si5341_output {
  61        struct clk_hw hw;
  62        struct clk_si5341 *data;
  63        struct regulator *vddo_reg;
  64        u8 index;
  65};
  66#define to_clk_si5341_output(_hw) \
  67        container_of(_hw, struct clk_si5341_output, hw)
  68
  69struct clk_si5341 {
  70        struct clk_hw hw;
  71        struct regmap *regmap;
  72        struct i2c_client *i2c_client;
  73        struct clk_si5341_synth synth[SI5341_NUM_SYNTH];
  74        struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS];
  75        struct clk *input_clk[SI5341_NUM_INPUTS];
  76        const char *input_clk_name[SI5341_NUM_INPUTS];
  77        const u16 *reg_output_offset;
  78        const u16 *reg_rdiv_offset;
  79        u64 freq_vco; /* 13500\xE2\x80\x9314256 MHz */
  80        u8 num_outputs;
  81        u8 num_synth;
  82        u16 chip_id;
  83        bool xaxb_ext_clk;
  84        bool iovdd_33;
  85};
  86#define to_clk_si5341(_hw)      container_of(_hw, struct clk_si5341, hw)
  87
  88struct clk_si5341_output_config {
  89        u8 out_format_drv_bits;
  90        u8 out_cm_ampl_bits;
  91        u8 vdd_sel_bits;
  92        bool synth_master;
  93        bool always_on;
  94};
  95
  96#define SI5341_PAGE             0x0001
  97#define SI5341_PN_BASE          0x0002
  98#define SI5341_DEVICE_REV       0x0005
  99#define SI5341_STATUS           0x000C
 100#define SI5341_LOS              0x000D
 101#define SI5341_STATUS_STICKY    0x0011
 102#define SI5341_LOS_STICKY       0x0012
 103#define SI5341_SOFT_RST         0x001C
 104#define SI5341_IN_SEL           0x0021
 105#define SI5341_DEVICE_READY     0x00FE
 106#define SI5341_XAXB_CFG         0x090E
 107#define SI5341_IO_VDD_SEL       0x0943
 108#define SI5341_IN_EN            0x0949
 109#define SI5341_INX_TO_PFD_EN    0x094A
 110
 111/* Status bits */
 112#define SI5341_STATUS_SYSINCAL  BIT(0)
 113#define SI5341_STATUS_LOSXAXB   BIT(1)
 114#define SI5341_STATUS_LOSREF    BIT(2)
 115#define SI5341_STATUS_LOL       BIT(3)
 116
 117/* Input selection */
 118#define SI5341_IN_SEL_MASK      0x06
 119#define SI5341_IN_SEL_SHIFT     1
 120#define SI5341_IN_SEL_REGCTRL   0x01
 121#define SI5341_INX_TO_PFD_SHIFT 4
 122
 123/* XTAL config bits */
 124#define SI5341_XAXB_CFG_EXTCLK_EN       BIT(0)
 125#define SI5341_XAXB_CFG_PDNB            BIT(1)
 126
 127/* Input dividers (48-bit) */
 128#define SI5341_IN_PDIV(x)       (0x0208 + ((x) * 10))
 129#define SI5341_IN_PSET(x)       (0x020E + ((x) * 10))
 130#define SI5341_PX_UPD           0x0230
 131
 132/* PLL configuration */
 133#define SI5341_PLL_M_NUM        0x0235
 134#define SI5341_PLL_M_DEN        0x023B
 135
 136/* Output configuration */
 137#define SI5341_OUT_CONFIG(output)       \
 138                        ((output)->data->reg_output_offset[(output)->index])
 139#define SI5341_OUT_FORMAT(output)       (SI5341_OUT_CONFIG(output) + 1)
 140#define SI5341_OUT_CM(output)           (SI5341_OUT_CONFIG(output) + 2)
 141#define SI5341_OUT_MUX_SEL(output)      (SI5341_OUT_CONFIG(output) + 3)
 142#define SI5341_OUT_R_REG(output)        \
 143                        ((output)->data->reg_rdiv_offset[(output)->index])
 144
 145#define SI5341_OUT_MUX_VDD_SEL_MASK 0x38
 146
 147/* Synthesize N divider */
 148#define SI5341_SYNTH_N_NUM(x)   (0x0302 + ((x) * 11))
 149#define SI5341_SYNTH_N_DEN(x)   (0x0308 + ((x) * 11))
 150#define SI5341_SYNTH_N_UPD(x)   (0x030C + ((x) * 11))
 151
 152/* Synthesizer output enable, phase bypass, power mode */
 153#define SI5341_SYNTH_N_CLK_TO_OUTX_EN   0x0A03
 154#define SI5341_SYNTH_N_PIBYP            0x0A04
 155#define SI5341_SYNTH_N_PDNB             0x0A05
 156#define SI5341_SYNTH_N_CLK_DIS          0x0B4A
 157
 158#define SI5341_REGISTER_MAX     0xBFF
 159
 160/* SI5341_OUT_CONFIG bits */
 161#define SI5341_OUT_CFG_PDN              BIT(0)
 162#define SI5341_OUT_CFG_OE               BIT(1)
 163#define SI5341_OUT_CFG_RDIV_FORCE2      BIT(2)
 164
 165/* Static configuration (to be moved to firmware) */
 166struct si5341_reg_default {
 167        u16 address;
 168        u8 value;
 169};
 170
 171static const char * const si5341_input_clock_names[] = {
 172        "in0", "in1", "in2", "xtal"
 173};
 174
 175/* Output configuration registers 0..9 are not quite logically organized */
 176/* Also for si5345 */
 177static const u16 si5341_reg_output_offset[] = {
 178        0x0108,
 179        0x010D,
 180        0x0112,
 181        0x0117,
 182        0x011C,
 183        0x0121,
 184        0x0126,
 185        0x012B,
 186        0x0130,
 187        0x013A,
 188};
 189
 190/* for si5340, si5342 and si5344 */
 191static const u16 si5340_reg_output_offset[] = {
 192        0x0112,
 193        0x0117,
 194        0x0126,
 195        0x012B,
 196};
 197
 198/* The location of the R divider registers */
 199static const u16 si5341_reg_rdiv_offset[] = {
 200        0x024A,
 201        0x024D,
 202        0x0250,
 203        0x0253,
 204        0x0256,
 205        0x0259,
 206        0x025C,
 207        0x025F,
 208        0x0262,
 209        0x0268,
 210};
 211static const u16 si5340_reg_rdiv_offset[] = {
 212        0x0250,
 213        0x0253,
 214        0x025C,
 215        0x025F,
 216};
 217
 218/*
 219 * Programming sequence from ClockBuilder, settings to initialize the system
 220 * using only the XTAL input, without pre-divider.
 221 * This also contains settings that aren't mentioned anywhere in the datasheet.
 222 * The "known" settings like synth and output configuration are done later.
 223 */
 224static const struct si5341_reg_default si5341_reg_defaults[] = {
 225        { 0x0017, 0x3A }, /* INT mask (disable interrupts) */
 226        { 0x0018, 0xFF }, /* INT mask */
 227        { 0x0021, 0x0F }, /* Select XTAL as input */
 228        { 0x0022, 0x00 }, /* Not in datasheet */
 229        { 0x002B, 0x02 }, /* SPI config */
 230        { 0x002C, 0x20 }, /* LOS enable for XTAL */
 231        { 0x002D, 0x00 }, /* LOS timing */
 232        { 0x002E, 0x00 },
 233        { 0x002F, 0x00 },
 234        { 0x0030, 0x00 },
 235        { 0x0031, 0x00 },
 236        { 0x0032, 0x00 },
 237        { 0x0033, 0x00 },
 238        { 0x0034, 0x00 },
 239        { 0x0035, 0x00 },
 240        { 0x0036, 0x00 },
 241        { 0x0037, 0x00 },
 242        { 0x0038, 0x00 }, /* LOS setting (thresholds) */
 243        { 0x0039, 0x00 },
 244        { 0x003A, 0x00 },
 245        { 0x003B, 0x00 },
 246        { 0x003C, 0x00 },
 247        { 0x003D, 0x00 }, /* LOS setting (thresholds) end */
 248        { 0x0041, 0x00 }, /* LOS0_DIV_SEL */
 249        { 0x0042, 0x00 }, /* LOS1_DIV_SEL */
 250        { 0x0043, 0x00 }, /* LOS2_DIV_SEL */
 251        { 0x0044, 0x00 }, /* LOS3_DIV_SEL */
 252        { 0x009E, 0x00 }, /* Not in datasheet */
 253        { 0x0102, 0x01 }, /* Enable outputs */
 254        { 0x013F, 0x00 }, /* Not in datasheet */
 255        { 0x0140, 0x00 }, /* Not in datasheet */
 256        { 0x0141, 0x40 }, /* OUT LOS */
 257        { 0x0202, 0x00 }, /* XAXB_FREQ_OFFSET (=0)*/
 258        { 0x0203, 0x00 },
 259        { 0x0204, 0x00 },
 260        { 0x0205, 0x00 },
 261        { 0x0206, 0x00 }, /* PXAXB (2^x) */
 262        { 0x0208, 0x00 }, /* Px divider setting (usually 0) */
 263        { 0x0209, 0x00 },
 264        { 0x020A, 0x00 },
 265        { 0x020B, 0x00 },
 266        { 0x020C, 0x00 },
 267        { 0x020D, 0x00 },
 268        { 0x020E, 0x00 },
 269        { 0x020F, 0x00 },
 270        { 0x0210, 0x00 },
 271        { 0x0211, 0x00 },
 272        { 0x0212, 0x00 },
 273        { 0x0213, 0x00 },
 274        { 0x0214, 0x00 },
 275        { 0x0215, 0x00 },
 276        { 0x0216, 0x00 },
 277        { 0x0217, 0x00 },
 278        { 0x0218, 0x00 },
 279        { 0x0219, 0x00 },
 280        { 0x021A, 0x00 },
 281        { 0x021B, 0x00 },
 282        { 0x021C, 0x00 },
 283        { 0x021D, 0x00 },
 284        { 0x021E, 0x00 },
 285        { 0x021F, 0x00 },
 286        { 0x0220, 0x00 },
 287        { 0x0221, 0x00 },
 288        { 0x0222, 0x00 },
 289        { 0x0223, 0x00 },
 290        { 0x0224, 0x00 },
 291        { 0x0225, 0x00 },
 292        { 0x0226, 0x00 },
 293        { 0x0227, 0x00 },
 294        { 0x0228, 0x00 },
 295        { 0x0229, 0x00 },
 296        { 0x022A, 0x00 },
 297        { 0x022B, 0x00 },
 298        { 0x022C, 0x00 },
 299        { 0x022D, 0x00 },
 300        { 0x022E, 0x00 },
 301        { 0x022F, 0x00 }, /* Px divider setting (usually 0) end */
 302        { 0x026B, 0x00 }, /* DESIGN_ID (ASCII string) */
 303        { 0x026C, 0x00 },
 304        { 0x026D, 0x00 },
 305        { 0x026E, 0x00 },
 306        { 0x026F, 0x00 },
 307        { 0x0270, 0x00 },
 308        { 0x0271, 0x00 },
 309        { 0x0272, 0x00 }, /* DESIGN_ID (ASCII string) end */
 310        { 0x0339, 0x1F }, /* N_FSTEP_MSK */
 311        { 0x033B, 0x00 }, /* Nx_FSTEPW (Frequency step) */
 312        { 0x033C, 0x00 },
 313        { 0x033D, 0x00 },
 314        { 0x033E, 0x00 },
 315        { 0x033F, 0x00 },
 316        { 0x0340, 0x00 },
 317        { 0x0341, 0x00 },
 318        { 0x0342, 0x00 },
 319        { 0x0343, 0x00 },
 320        { 0x0344, 0x00 },
 321        { 0x0345, 0x00 },
 322        { 0x0346, 0x00 },
 323        { 0x0347, 0x00 },
 324        { 0x0348, 0x00 },
 325        { 0x0349, 0x00 },
 326        { 0x034A, 0x00 },
 327        { 0x034B, 0x00 },
 328        { 0x034C, 0x00 },
 329        { 0x034D, 0x00 },
 330        { 0x034E, 0x00 },
 331        { 0x034F, 0x00 },
 332        { 0x0350, 0x00 },
 333        { 0x0351, 0x00 },
 334        { 0x0352, 0x00 },
 335        { 0x0353, 0x00 },
 336        { 0x0354, 0x00 },
 337        { 0x0355, 0x00 },
 338        { 0x0356, 0x00 },
 339        { 0x0357, 0x00 },
 340        { 0x0358, 0x00 }, /* Nx_FSTEPW (Frequency step) end */
 341        { 0x0359, 0x00 }, /* Nx_DELAY */
 342        { 0x035A, 0x00 },
 343        { 0x035B, 0x00 },
 344        { 0x035C, 0x00 },
 345        { 0x035D, 0x00 },
 346        { 0x035E, 0x00 },
 347        { 0x035F, 0x00 },
 348        { 0x0360, 0x00 },
 349        { 0x0361, 0x00 },
 350        { 0x0362, 0x00 }, /* Nx_DELAY end */
 351        { 0x0802, 0x00 }, /* Not in datasheet */
 352        { 0x0803, 0x00 }, /* Not in datasheet */
 353        { 0x0804, 0x00 }, /* Not in datasheet */
 354        { 0x090E, 0x02 }, /* XAXB_EXTCLK_EN=0 XAXB_PDNB=1 (use XTAL) */
 355        { 0x091C, 0x04 }, /* ZDM_EN=4 (Normal mode) */
 356        { 0x0949, 0x00 }, /* IN_EN (disable input clocks) */
 357        { 0x094A, 0x00 }, /* INx_TO_PFD_EN (disabled) */
 358        { 0x0A02, 0x00 }, /* Not in datasheet */
 359        { 0x0B44, 0x0F }, /* PDIV_ENB (datasheet does not mention what it is) */
 360        { 0x0B57, 0x10 }, /* VCO_RESET_CALCODE (not described in datasheet) */
 361        { 0x0B58, 0x05 }, /* VCO_RESET_CALCODE (not described in datasheet) */
 362};
 363
 364/* Read and interpret a 44-bit followed by a 32-bit value in the regmap */
 365static int si5341_decode_44_32(struct regmap *regmap, unsigned int reg,
 366        u64 *val1, u32 *val2)
 367{
 368        int err;
 369        u8 r[10];
 370
 371        err = regmap_bulk_read(regmap, reg, r, 10);
 372        if (err < 0)
 373                return err;
 374
 375        *val1 = ((u64)((r[5] & 0x0f) << 8 | r[4]) << 32) |
 376                 (get_unaligned_le32(r));
 377        *val2 = get_unaligned_le32(&r[6]);
 378
 379        return 0;
 380}
 381
 382static int si5341_encode_44_32(struct regmap *regmap, unsigned int reg,
 383        u64 n_num, u32 n_den)
 384{
 385        u8 r[10];
 386
 387        /* Shift left as far as possible without overflowing */
 388        while (!(n_num & BIT_ULL(43)) && !(n_den & BIT(31))) {
 389                n_num <<= 1;
 390                n_den <<= 1;
 391        }
 392
 393        /* 44 bits (6 bytes) numerator */
 394        put_unaligned_le32(n_num, r);
 395        r[4] = (n_num >> 32) & 0xff;
 396        r[5] = (n_num >> 40) & 0x0f;
 397        /* 32 bits denominator */
 398        put_unaligned_le32(n_den, &r[6]);
 399
 400        /* Program the fraction */
 401        return regmap_bulk_write(regmap, reg, r, sizeof(r));
 402}
 403
 404/* VCO, we assume it runs at a constant frequency */
 405static unsigned long si5341_clk_recalc_rate(struct clk_hw *hw,
 406                unsigned long parent_rate)
 407{
 408        struct clk_si5341 *data = to_clk_si5341(hw);
 409        int err;
 410        u64 res;
 411        u64 m_num;
 412        u32 m_den;
 413        unsigned int shift;
 414
 415        /* Assume that PDIV is not being used, just read the PLL setting */
 416        err = si5341_decode_44_32(data->regmap, SI5341_PLL_M_NUM,
 417                                &m_num, &m_den);
 418        if (err < 0)
 419                return 0;
 420
 421        if (!m_num || !m_den)
 422                return 0;
 423
 424        /*
 425         * Though m_num is 64-bit, only the upper bits are actually used. While
 426         * calculating m_num and m_den, they are shifted as far as possible to
 427         * the left. To avoid 96-bit division here, we just shift them back so
 428         * we can do with just 64 bits.
 429         */
 430        shift = 0;
 431        res = m_num;
 432        while (res & 0xffff00000000ULL) {
 433                ++shift;
 434                res >>= 1;
 435        }
 436        res *= parent_rate;
 437        do_div(res, (m_den >> shift));
 438
 439        /* We cannot return the actual frequency in 32 bit, store it locally */
 440        data->freq_vco = res;
 441
 442        /* Report kHz since the value is out of range */
 443        do_div(res, 1000);
 444
 445        return (unsigned long)res;
 446}
 447
 448static int si5341_clk_get_selected_input(struct clk_si5341 *data)
 449{
 450        int err;
 451        u32 val;
 452
 453        err = regmap_read(data->regmap, SI5341_IN_SEL, &val);
 454        if (err < 0)
 455                return err;
 456
 457        return (val & SI5341_IN_SEL_MASK) >> SI5341_IN_SEL_SHIFT;
 458}
 459
 460static u8 si5341_clk_get_parent(struct clk_hw *hw)
 461{
 462        struct clk_si5341 *data = to_clk_si5341(hw);
 463        int res = si5341_clk_get_selected_input(data);
 464
 465        if (res < 0)
 466                return 0; /* Apparently we cannot report errors */
 467
 468        return res;
 469}
 470
 471static int si5341_clk_reparent(struct clk_si5341 *data, u8 index)
 472{
 473        int err;
 474        u8 val;
 475
 476        val = (index << SI5341_IN_SEL_SHIFT) & SI5341_IN_SEL_MASK;
 477        /* Enable register-based input selection */
 478        val |= SI5341_IN_SEL_REGCTRL;
 479
 480        err = regmap_update_bits(data->regmap,
 481                SI5341_IN_SEL, SI5341_IN_SEL_REGCTRL | SI5341_IN_SEL_MASK, val);
 482        if (err < 0)
 483                return err;
 484
 485        if (index < 3) {
 486                /* Enable input buffer for selected input */
 487                err = regmap_update_bits(data->regmap,
 488                                SI5341_IN_EN, 0x07, BIT(index));
 489                if (err < 0)
 490                        return err;
 491
 492                /* Enables the input to phase detector */
 493                err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN,
 494                                0x7 << SI5341_INX_TO_PFD_SHIFT,
 495                                BIT(index + SI5341_INX_TO_PFD_SHIFT));
 496                if (err < 0)
 497                        return err;
 498
 499                /* Power down XTAL oscillator and buffer */
 500                err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG,
 501                                SI5341_XAXB_CFG_PDNB, 0);
 502                if (err < 0)
 503                        return err;
 504
 505                /*
 506                 * Set the P divider to "1". There's no explanation in the
 507                 * datasheet of these registers, but the clockbuilder software
 508                 * programs a "1" when the input is being used.
 509                 */
 510                err = regmap_write(data->regmap, SI5341_IN_PDIV(index), 1);
 511                if (err < 0)
 512                        return err;
 513
 514                err = regmap_write(data->regmap, SI5341_IN_PSET(index), 1);
 515                if (err < 0)
 516                        return err;
 517
 518                /* Set update PDIV bit */
 519                err = regmap_write(data->regmap, SI5341_PX_UPD, BIT(index));
 520                if (err < 0)
 521                        return err;
 522        } else {
 523                /* Disable all input buffers */
 524                err = regmap_update_bits(data->regmap, SI5341_IN_EN, 0x07, 0);
 525                if (err < 0)
 526                        return err;
 527
 528                /* Disable input to phase detector */
 529                err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN,
 530                                0x7 << SI5341_INX_TO_PFD_SHIFT, 0);
 531                if (err < 0)
 532                        return err;
 533
 534                /* Power up XTAL oscillator and buffer, select clock mode */
 535                err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG,
 536                                SI5341_XAXB_CFG_PDNB | SI5341_XAXB_CFG_EXTCLK_EN,
 537                                SI5341_XAXB_CFG_PDNB | (data->xaxb_ext_clk ?
 538                                        SI5341_XAXB_CFG_EXTCLK_EN : 0));
 539                if (err < 0)
 540                        return err;
 541        }
 542
 543        return 0;
 544}
 545
 546static int si5341_clk_set_parent(struct clk_hw *hw, u8 index)
 547{
 548        struct clk_si5341 *data = to_clk_si5341(hw);
 549
 550        return si5341_clk_reparent(data, index);
 551}
 552
 553static const struct clk_ops si5341_clk_ops = {
 554        .set_parent = si5341_clk_set_parent,
 555        .get_parent = si5341_clk_get_parent,
 556        .recalc_rate = si5341_clk_recalc_rate,
 557};
 558
 559/* Synthesizers, there are 5 synthesizers that connect to any of the outputs */
 560
 561/* The synthesizer is on if all power and enable bits are set */
 562static int si5341_synth_clk_is_on(struct clk_hw *hw)
 563{
 564        struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
 565        int err;
 566        u32 val;
 567        u8 index = synth->index;
 568
 569        err = regmap_read(synth->data->regmap,
 570                        SI5341_SYNTH_N_CLK_TO_OUTX_EN, &val);
 571        if (err < 0)
 572                return 0;
 573
 574        if (!(val & BIT(index)))
 575                return 0;
 576
 577        err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_PDNB, &val);
 578        if (err < 0)
 579                return 0;
 580
 581        if (!(val & BIT(index)))
 582                return 0;
 583
 584        /* This bit must be 0 for the synthesizer to receive clock input */
 585        err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_CLK_DIS, &val);
 586        if (err < 0)
 587                return 0;
 588
 589        return !(val & BIT(index));
 590}
 591
 592static void si5341_synth_clk_unprepare(struct clk_hw *hw)
 593{
 594        struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
 595        u8 index = synth->index; /* In range 0..5 */
 596        u8 mask = BIT(index);
 597
 598        /* Disable output */
 599        regmap_update_bits(synth->data->regmap,
 600                SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, 0);
 601        /* Power down */
 602        regmap_update_bits(synth->data->regmap,
 603                SI5341_SYNTH_N_PDNB, mask, 0);
 604        /* Disable clock input to synth (set to 1 to disable) */
 605        regmap_update_bits(synth->data->regmap,
 606                SI5341_SYNTH_N_CLK_DIS, mask, mask);
 607}
 608
 609static int si5341_synth_clk_prepare(struct clk_hw *hw)
 610{
 611        struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
 612        int err;
 613        u8 index = synth->index;
 614        u8 mask = BIT(index);
 615
 616        /* Power up */
 617        err = regmap_update_bits(synth->data->regmap,
 618                SI5341_SYNTH_N_PDNB, mask, mask);
 619        if (err < 0)
 620                return err;
 621
 622        /* Enable clock input to synth (set bit to 0 to enable) */
 623        err = regmap_update_bits(synth->data->regmap,
 624                SI5341_SYNTH_N_CLK_DIS, mask, 0);
 625        if (err < 0)
 626                return err;
 627
 628        /* Enable output */
 629        return regmap_update_bits(synth->data->regmap,
 630                SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, mask);
 631}
 632
 633/* Synth clock frequency: Fvco * n_den / n_den, with Fvco in 13500-14256 MHz */
 634static unsigned long si5341_synth_clk_recalc_rate(struct clk_hw *hw,
 635                unsigned long parent_rate)
 636{
 637        struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
 638        u64 f;
 639        u64 n_num;
 640        u32 n_den;
 641        int err;
 642
 643        err = si5341_decode_44_32(synth->data->regmap,
 644                        SI5341_SYNTH_N_NUM(synth->index), &n_num, &n_den);
 645        if (err < 0)
 646                return err;
 647        /* Check for bogus/uninitialized settings */
 648        if (!n_num || !n_den)
 649                return 0;
 650
 651        /*
 652         * n_num and n_den are shifted left as much as possible, so to prevent
 653         * overflow in 64-bit math, we shift n_den 4 bits to the right
 654         */
 655        f = synth->data->freq_vco;
 656        f *= n_den >> 4;
 657
 658        /* Now we need to to 64-bit division: f/n_num */
 659        /* And compensate for the 4 bits we dropped */
 660        f = div64_u64(f, (n_num >> 4));
 661
 662        return f;
 663}
 664
 665static long si5341_synth_clk_round_rate(struct clk_hw *hw, unsigned long rate,
 666                unsigned long *parent_rate)
 667{
 668        struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
 669        u64 f;
 670
 671        /* The synthesizer accuracy is such that anything in range will work */
 672        f = synth->data->freq_vco;
 673        do_div(f, SI5341_SYNTH_N_MAX);
 674        if (rate < f)
 675                return f;
 676
 677        f = synth->data->freq_vco;
 678        do_div(f, SI5341_SYNTH_N_MIN);
 679        if (rate > f)
 680                return f;
 681
 682        return rate;
 683}
 684
 685static int si5341_synth_program(struct clk_si5341_synth *synth,
 686        u64 n_num, u32 n_den, bool is_integer)
 687{
 688        int err;
 689        u8 index = synth->index;
 690
 691        err = si5341_encode_44_32(synth->data->regmap,
 692                        SI5341_SYNTH_N_NUM(index), n_num, n_den);
 693
 694        err = regmap_update_bits(synth->data->regmap,
 695                SI5341_SYNTH_N_PIBYP, BIT(index), is_integer ? BIT(index) : 0);
 696        if (err < 0)
 697                return err;
 698
 699        return regmap_write(synth->data->regmap,
 700                SI5341_SYNTH_N_UPD(index), 0x01);
 701}
 702
 703
 704static int si5341_synth_clk_set_rate(struct clk_hw *hw, unsigned long rate,
 705                unsigned long parent_rate)
 706{
 707        struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
 708        u64 n_num;
 709        u32 n_den;
 710        u32 r;
 711        u32 g;
 712        bool is_integer;
 713
 714        n_num = synth->data->freq_vco;
 715
 716        /* see if there's an integer solution */
 717        r = do_div(n_num, rate);
 718        is_integer = (r == 0);
 719        if (is_integer) {
 720                /* Integer divider equal to n_num */
 721                n_den = 1;
 722        } else {
 723                /* Calculate a fractional solution */
 724                g = gcd(r, rate);
 725                n_den = rate / g;
 726                n_num *= n_den;
 727                n_num += r / g;
 728        }
 729
 730        dev_dbg(&synth->data->i2c_client->dev,
 731                        "%s(%u): n=0x%llx d=0x%x %s\n", __func__,
 732                                synth->index, n_num, n_den,
 733                                is_integer ? "int" : "frac");
 734
 735        return si5341_synth_program(synth, n_num, n_den, is_integer);
 736}
 737
 738static const struct clk_ops si5341_synth_clk_ops = {
 739        .is_prepared = si5341_synth_clk_is_on,
 740        .prepare = si5341_synth_clk_prepare,
 741        .unprepare = si5341_synth_clk_unprepare,
 742        .recalc_rate = si5341_synth_clk_recalc_rate,
 743        .round_rate = si5341_synth_clk_round_rate,
 744        .set_rate = si5341_synth_clk_set_rate,
 745};
 746
 747static int si5341_output_clk_is_on(struct clk_hw *hw)
 748{
 749        struct clk_si5341_output *output = to_clk_si5341_output(hw);
 750        int err;
 751        u32 val;
 752
 753        err = regmap_read(output->data->regmap,
 754                        SI5341_OUT_CONFIG(output), &val);
 755        if (err < 0)
 756                return err;
 757
 758        /* Bit 0=PDN, 1=OE so only a value of 0x2 enables the output */
 759        return (val & 0x03) == SI5341_OUT_CFG_OE;
 760}
 761
 762/* Disables and then powers down the output */
 763static void si5341_output_clk_unprepare(struct clk_hw *hw)
 764{
 765        struct clk_si5341_output *output = to_clk_si5341_output(hw);
 766
 767        regmap_update_bits(output->data->regmap,
 768                        SI5341_OUT_CONFIG(output),
 769                        SI5341_OUT_CFG_OE, 0);
 770        regmap_update_bits(output->data->regmap,
 771                        SI5341_OUT_CONFIG(output),
 772                        SI5341_OUT_CFG_PDN, SI5341_OUT_CFG_PDN);
 773}
 774
 775/* Powers up and then enables the output */
 776static int si5341_output_clk_prepare(struct clk_hw *hw)
 777{
 778        struct clk_si5341_output *output = to_clk_si5341_output(hw);
 779        int err;
 780
 781        err = regmap_update_bits(output->data->regmap,
 782                        SI5341_OUT_CONFIG(output),
 783                        SI5341_OUT_CFG_PDN, 0);
 784        if (err < 0)
 785                return err;
 786
 787        return regmap_update_bits(output->data->regmap,
 788                        SI5341_OUT_CONFIG(output),
 789                        SI5341_OUT_CFG_OE, SI5341_OUT_CFG_OE);
 790}
 791
 792static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw,
 793                unsigned long parent_rate)
 794{
 795        struct clk_si5341_output *output = to_clk_si5341_output(hw);
 796        int err;
 797        u32 val;
 798        u32 r_divider;
 799        u8 r[3];
 800
 801        err = regmap_bulk_read(output->data->regmap,
 802                        SI5341_OUT_R_REG(output), r, 3);
 803        if (err < 0)
 804                return err;
 805
 806        /* Calculate value as 24-bit integer*/
 807        r_divider = r[2] << 16 | r[1] << 8 | r[0];
 808
 809        /* If Rx_REG is zero, the divider is disabled, so return a "0" rate */
 810        if (!r_divider)
 811                return 0;
 812
 813        /* Divider is 2*(Rx_REG+1) */
 814        r_divider += 1;
 815        r_divider <<= 1;
 816
 817        err = regmap_read(output->data->regmap,
 818                        SI5341_OUT_CONFIG(output), &val);
 819        if (err < 0)
 820                return err;
 821
 822        if (val & SI5341_OUT_CFG_RDIV_FORCE2)
 823                r_divider = 2;
 824
 825        return parent_rate / r_divider;
 826}
 827
 828static long si5341_output_clk_round_rate(struct clk_hw *hw, unsigned long rate,
 829                unsigned long *parent_rate)
 830{
 831        unsigned long r;
 832
 833        if (!rate)
 834                return 0;
 835
 836        r = *parent_rate >> 1;
 837
 838        /* If rate is an even divisor, no changes to parent required */
 839        if (r && !(r % rate))
 840                return (long)rate;
 841
 842        if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
 843                if (rate > 200000000) {
 844                        /* minimum r-divider is 2 */
 845                        r = 2;
 846                } else {
 847                        /* Take a parent frequency near 400 MHz */
 848                        r = (400000000u / rate) & ~1;
 849                }
 850                *parent_rate = r * rate;
 851        } else {
 852                /* We cannot change our parent's rate, report what we can do */
 853                r /= rate;
 854                rate = *parent_rate / (r << 1);
 855        }
 856
 857        return rate;
 858}
 859
 860static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate,
 861                unsigned long parent_rate)
 862{
 863        struct clk_si5341_output *output = to_clk_si5341_output(hw);
 864        u32 r_div;
 865        int err;
 866        u8 r[3];
 867
 868        if (!rate)
 869                return -EINVAL;
 870
 871        /* Frequency divider is (r_div + 1) * 2 */
 872        r_div = (parent_rate / rate) >> 1;
 873
 874        if (r_div <= 1)
 875                r_div = 0;
 876        else if (r_div >= BIT(24))
 877                r_div = BIT(24) - 1;
 878        else
 879                --r_div;
 880
 881        /* For a value of "2", we set the "OUT0_RDIV_FORCE2" bit */
 882        err = regmap_update_bits(output->data->regmap,
 883                        SI5341_OUT_CONFIG(output),
 884                        SI5341_OUT_CFG_RDIV_FORCE2,
 885                        (r_div == 0) ? SI5341_OUT_CFG_RDIV_FORCE2 : 0);
 886        if (err < 0)
 887                return err;
 888
 889        /* Always write Rx_REG, because a zero value disables the divider */
 890        r[0] = r_div ? (r_div & 0xff) : 1;
 891        r[1] = (r_div >> 8) & 0xff;
 892        r[2] = (r_div >> 16) & 0xff;
 893        err = regmap_bulk_write(output->data->regmap,
 894                        SI5341_OUT_R_REG(output), r, 3);
 895
 896        return 0;
 897}
 898
 899static int si5341_output_reparent(struct clk_si5341_output *output, u8 index)
 900{
 901        return regmap_update_bits(output->data->regmap,
 902                SI5341_OUT_MUX_SEL(output), 0x07, index);
 903}
 904
 905static int si5341_output_set_parent(struct clk_hw *hw, u8 index)
 906{
 907        struct clk_si5341_output *output = to_clk_si5341_output(hw);
 908
 909        if (index >= output->data->num_synth)
 910                return -EINVAL;
 911
 912        return si5341_output_reparent(output, index);
 913}
 914
 915static u8 si5341_output_get_parent(struct clk_hw *hw)
 916{
 917        struct clk_si5341_output *output = to_clk_si5341_output(hw);
 918        u32 val;
 919
 920        regmap_read(output->data->regmap, SI5341_OUT_MUX_SEL(output), &val);
 921
 922        return val & 0x7;
 923}
 924
 925static const struct clk_ops si5341_output_clk_ops = {
 926        .is_prepared = si5341_output_clk_is_on,
 927        .prepare = si5341_output_clk_prepare,
 928        .unprepare = si5341_output_clk_unprepare,
 929        .recalc_rate = si5341_output_clk_recalc_rate,
 930        .round_rate = si5341_output_clk_round_rate,
 931        .set_rate = si5341_output_clk_set_rate,
 932        .set_parent = si5341_output_set_parent,
 933        .get_parent = si5341_output_get_parent,
 934};
 935
 936/*
 937 * The chip can be bought in a pre-programmed version, or one can program the
 938 * NVM in the chip to boot up in a preset mode. This routine tries to determine
 939 * if that's the case, or if we need to reset and program everything from
 940 * scratch. Returns negative error, or true/false.
 941 */
 942static int si5341_is_programmed_already(struct clk_si5341 *data)
 943{
 944        int err;
 945        u8 r[4];
 946
 947        /* Read the PLL divider value, it must have a non-zero value */
 948        err = regmap_bulk_read(data->regmap, SI5341_PLL_M_DEN,
 949                        r, ARRAY_SIZE(r));
 950        if (err < 0)
 951                return err;
 952
 953        return !!get_unaligned_le32(r);
 954}
 955
 956static struct clk_hw *
 957of_clk_si5341_get(struct of_phandle_args *clkspec, void *_data)
 958{
 959        struct clk_si5341 *data = _data;
 960        unsigned int idx = clkspec->args[1];
 961        unsigned int group = clkspec->args[0];
 962
 963        switch (group) {
 964        case 0:
 965                if (idx >= data->num_outputs) {
 966                        dev_err(&data->i2c_client->dev,
 967                                "invalid output index %u\n", idx);
 968                        return ERR_PTR(-EINVAL);
 969                }
 970                return &data->clk[idx].hw;
 971        case 1:
 972                if (idx >= data->num_synth) {
 973                        dev_err(&data->i2c_client->dev,
 974                                "invalid synthesizer index %u\n", idx);
 975                        return ERR_PTR(-EINVAL);
 976                }
 977                return &data->synth[idx].hw;
 978        case 2:
 979                if (idx > 0) {
 980                        dev_err(&data->i2c_client->dev,
 981                                "invalid PLL index %u\n", idx);
 982                        return ERR_PTR(-EINVAL);
 983                }
 984                return &data->hw;
 985        default:
 986                dev_err(&data->i2c_client->dev, "invalid group %u\n", group);
 987                return ERR_PTR(-EINVAL);
 988        }
 989}
 990
 991static int si5341_probe_chip_id(struct clk_si5341 *data)
 992{
 993        int err;
 994        u8 reg[4];
 995        u16 model;
 996
 997        err = regmap_bulk_read(data->regmap, SI5341_PN_BASE, reg,
 998                                ARRAY_SIZE(reg));
 999        if (err < 0) {
1000                dev_err(&data->i2c_client->dev, "Failed to read chip ID\n");
1001                return err;
1002        }
1003
1004        model = get_unaligned_le16(reg);
1005
1006        dev_info(&data->i2c_client->dev, "Chip: %x Grade: %u Rev: %u\n",
1007                 model, reg[2], reg[3]);
1008
1009        switch (model) {
1010        case 0x5340:
1011                data->num_outputs = SI5340_MAX_NUM_OUTPUTS;
1012                data->num_synth = SI5340_NUM_SYNTH;
1013                data->reg_output_offset = si5340_reg_output_offset;
1014                data->reg_rdiv_offset = si5340_reg_rdiv_offset;
1015                break;
1016        case 0x5341:
1017                data->num_outputs = SI5341_MAX_NUM_OUTPUTS;
1018                data->num_synth = SI5341_NUM_SYNTH;
1019                data->reg_output_offset = si5341_reg_output_offset;
1020                data->reg_rdiv_offset = si5341_reg_rdiv_offset;
1021                break;
1022        case 0x5342:
1023                data->num_outputs = SI5342_MAX_NUM_OUTPUTS;
1024                data->num_synth = SI5342_NUM_SYNTH;
1025                data->reg_output_offset = si5340_reg_output_offset;
1026                data->reg_rdiv_offset = si5340_reg_rdiv_offset;
1027                break;
1028        case 0x5344:
1029                data->num_outputs = SI5344_MAX_NUM_OUTPUTS;
1030                data->num_synth = SI5344_NUM_SYNTH;
1031                data->reg_output_offset = si5340_reg_output_offset;
1032                data->reg_rdiv_offset = si5340_reg_rdiv_offset;
1033                break;
1034        case 0x5345:
1035                data->num_outputs = SI5345_MAX_NUM_OUTPUTS;
1036                data->num_synth = SI5345_NUM_SYNTH;
1037                data->reg_output_offset = si5341_reg_output_offset;
1038                data->reg_rdiv_offset = si5341_reg_rdiv_offset;
1039                break;
1040        default:
1041                dev_err(&data->i2c_client->dev, "Model '%x' not supported\n",
1042                        model);
1043                return -EINVAL;
1044        }
1045
1046        data->chip_id = model;
1047
1048        return 0;
1049}
1050
1051/* Read active settings into the regmap cache for later reference */
1052static int si5341_read_settings(struct clk_si5341 *data)
1053{
1054        int err;
1055        u8 i;
1056        u8 r[10];
1057
1058        err = regmap_bulk_read(data->regmap, SI5341_PLL_M_NUM, r, 10);
1059        if (err < 0)
1060                return err;
1061
1062        err = regmap_bulk_read(data->regmap,
1063                                SI5341_SYNTH_N_CLK_TO_OUTX_EN, r, 3);
1064        if (err < 0)
1065                return err;
1066
1067        err = regmap_bulk_read(data->regmap,
1068                                SI5341_SYNTH_N_CLK_DIS, r, 1);
1069        if (err < 0)
1070                return err;
1071
1072        for (i = 0; i < data->num_synth; ++i) {
1073                err = regmap_bulk_read(data->regmap,
1074                                        SI5341_SYNTH_N_NUM(i), r, 10);
1075                if (err < 0)
1076                        return err;
1077        }
1078
1079        for (i = 0; i < data->num_outputs; ++i) {
1080                err = regmap_bulk_read(data->regmap,
1081                                        data->reg_output_offset[i], r, 4);
1082                if (err < 0)
1083                        return err;
1084
1085                err = regmap_bulk_read(data->regmap,
1086                                        data->reg_rdiv_offset[i], r, 3);
1087                if (err < 0)
1088                        return err;
1089        }
1090
1091        return 0;
1092}
1093
1094static int si5341_write_multiple(struct clk_si5341 *data,
1095        const struct si5341_reg_default *values, unsigned int num_values)
1096{
1097        unsigned int i;
1098        int res;
1099
1100        for (i = 0; i < num_values; ++i) {
1101                res = regmap_write(data->regmap,
1102                        values[i].address, values[i].value);
1103                if (res < 0) {
1104                        dev_err(&data->i2c_client->dev,
1105                                "Failed to write %#x:%#x\n",
1106                                values[i].address, values[i].value);
1107                        return res;
1108                }
1109        }
1110
1111        return 0;
1112}
1113
1114static const struct si5341_reg_default si5341_preamble[] = {
1115        { 0x0B25, 0x00 },
1116        { 0x0502, 0x01 },
1117        { 0x0505, 0x03 },
1118        { 0x0957, 0x17 },
1119        { 0x0B4E, 0x1A },
1120};
1121
1122static const struct si5341_reg_default si5345_preamble[] = {
1123        { 0x0B25, 0x00 },
1124        { 0x0540, 0x01 },
1125};
1126
1127static int si5341_send_preamble(struct clk_si5341 *data)
1128{
1129        int res;
1130        u32 revision;
1131
1132        /* For revision 2 and up, the values are slightly different */
1133        res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
1134        if (res < 0)
1135                return res;
1136
1137        /* Write "preamble" as specified by datasheet */
1138        res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xD8 : 0xC0);
1139        if (res < 0)
1140                return res;
1141
1142        /* The si5342..si5345 require a different preamble */
1143        if (data->chip_id > 0x5341)
1144                res = si5341_write_multiple(data,
1145                        si5345_preamble, ARRAY_SIZE(si5345_preamble));
1146        else
1147                res = si5341_write_multiple(data,
1148                        si5341_preamble, ARRAY_SIZE(si5341_preamble));
1149        if (res < 0)
1150                return res;
1151
1152        /* Datasheet specifies a 300ms wait after sending the preamble */
1153        msleep(300);
1154
1155        return 0;
1156}
1157
1158/* Perform a soft reset and write post-amble */
1159static int si5341_finalize_defaults(struct clk_si5341 *data)
1160{
1161        int res;
1162        u32 revision;
1163
1164        res = regmap_write(data->regmap, SI5341_IO_VDD_SEL,
1165                           data->iovdd_33 ? 1 : 0);
1166        if (res < 0)
1167                return res;
1168
1169        res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
1170        if (res < 0)
1171                return res;
1172
1173        dev_dbg(&data->i2c_client->dev, "%s rev=%u\n", __func__, revision);
1174
1175        res = regmap_write(data->regmap, SI5341_SOFT_RST, 0x01);
1176        if (res < 0)
1177                return res;
1178
1179        /* The si5342..si5345 have an additional post-amble */
1180        if (data->chip_id > 0x5341) {
1181                res = regmap_write(data->regmap, 0x540, 0x0);
1182                if (res < 0)
1183                        return res;
1184        }
1185
1186        /* Datasheet does not explain these nameless registers */
1187        res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xDB : 0xC3);
1188        if (res < 0)
1189                return res;
1190        res = regmap_write(data->regmap, 0x0B25, 0x02);
1191        if (res < 0)
1192                return res;
1193
1194        return 0;
1195}
1196
1197
1198static const struct regmap_range si5341_regmap_volatile_range[] = {
1199        regmap_reg_range(0x000C, 0x0012), /* Status */
1200        regmap_reg_range(0x001C, 0x001E), /* reset, finc/fdec */
1201        regmap_reg_range(0x00E2, 0x00FE), /* NVM, interrupts, device ready */
1202        /* Update bits for P divider and synth config */
1203        regmap_reg_range(SI5341_PX_UPD, SI5341_PX_UPD),
1204        regmap_reg_range(SI5341_SYNTH_N_UPD(0), SI5341_SYNTH_N_UPD(0)),
1205        regmap_reg_range(SI5341_SYNTH_N_UPD(1), SI5341_SYNTH_N_UPD(1)),
1206        regmap_reg_range(SI5341_SYNTH_N_UPD(2), SI5341_SYNTH_N_UPD(2)),
1207        regmap_reg_range(SI5341_SYNTH_N_UPD(3), SI5341_SYNTH_N_UPD(3)),
1208        regmap_reg_range(SI5341_SYNTH_N_UPD(4), SI5341_SYNTH_N_UPD(4)),
1209};
1210
1211static const struct regmap_access_table si5341_regmap_volatile = {
1212        .yes_ranges = si5341_regmap_volatile_range,
1213        .n_yes_ranges = ARRAY_SIZE(si5341_regmap_volatile_range),
1214};
1215
1216/* Pages 0, 1, 2, 3, 9, A, B are valid, so there are 12 pages */
1217static const struct regmap_range_cfg si5341_regmap_ranges[] = {
1218        {
1219                .range_min = 0,
1220                .range_max = SI5341_REGISTER_MAX,
1221                .selector_reg = SI5341_PAGE,
1222                .selector_mask = 0xff,
1223                .selector_shift = 0,
1224                .window_start = 0,
1225                .window_len = 256,
1226        },
1227};
1228
1229static int si5341_wait_device_ready(struct i2c_client *client)
1230{
1231        int count;
1232
1233        /* Datasheet warns: Any attempt to read or write any register other
1234         * than DEVICE_READY before DEVICE_READY reads as 0x0F may corrupt the
1235         * NVM programming and may corrupt the register contents, as they are
1236         * read from NVM. Note that this includes accesses to the PAGE register.
1237         * Also: DEVICE_READY is available on every register page, so no page
1238         * change is needed to read it.
1239         * Do this outside regmap to avoid automatic PAGE register access.
1240         * May take up to 300ms to complete.
1241         */
1242        for (count = 0; count < 15; ++count) {
1243                s32 result = i2c_smbus_read_byte_data(client,
1244                                                      SI5341_DEVICE_READY);
1245                if (result < 0)
1246                        return result;
1247                if (result == 0x0F)
1248                        return 0;
1249                msleep(20);
1250        }
1251        dev_err(&client->dev, "timeout waiting for DEVICE_READY\n");
1252        return -EIO;
1253}
1254
1255static const struct regmap_config si5341_regmap_config = {
1256        .reg_bits = 8,
1257        .val_bits = 8,
1258        .cache_type = REGCACHE_RBTREE,
1259        .ranges = si5341_regmap_ranges,
1260        .num_ranges = ARRAY_SIZE(si5341_regmap_ranges),
1261        .max_register = SI5341_REGISTER_MAX,
1262        .volatile_table = &si5341_regmap_volatile,
1263};
1264
1265static int si5341_dt_parse_dt(struct clk_si5341 *data,
1266                              struct clk_si5341_output_config *config)
1267{
1268        struct device_node *child;
1269        struct device_node *np = data->i2c_client->dev.of_node;
1270        u32 num;
1271        u32 val;
1272
1273        memset(config, 0, sizeof(struct clk_si5341_output_config) *
1274                                SI5341_MAX_NUM_OUTPUTS);
1275
1276        for_each_child_of_node(np, child) {
1277                if (of_property_read_u32(child, "reg", &num)) {
1278                        dev_err(&data->i2c_client->dev, "missing reg property of %s\n",
1279                                child->name);
1280                        goto put_child;
1281                }
1282
1283                if (num >= SI5341_MAX_NUM_OUTPUTS) {
1284                        dev_err(&data->i2c_client->dev, "invalid clkout %d\n", num);
1285                        goto put_child;
1286                }
1287
1288                if (!of_property_read_u32(child, "silabs,format", &val)) {
1289                        /* Set cm and ampl conservatively to 3v3 settings */
1290                        switch (val) {
1291                        case 1: /* normal differential */
1292                                config[num].out_cm_ampl_bits = 0x33;
1293                                break;
1294                        case 2: /* low-power differential */
1295                                config[num].out_cm_ampl_bits = 0x13;
1296                                break;
1297                        case 4: /* LVCMOS */
1298                                config[num].out_cm_ampl_bits = 0x33;
1299                                /* Set SI recommended impedance for LVCMOS */
1300                                config[num].out_format_drv_bits |= 0xc0;
1301                                break;
1302                        default:
1303                                dev_err(&data->i2c_client->dev,
1304                                        "invalid silabs,format %u for %u\n",
1305                                        val, num);
1306                                goto put_child;
1307                        }
1308                        config[num].out_format_drv_bits &= ~0x07;
1309                        config[num].out_format_drv_bits |= val & 0x07;
1310                        /* Always enable the SYNC feature */
1311                        config[num].out_format_drv_bits |= 0x08;
1312                }
1313
1314                if (!of_property_read_u32(child, "silabs,common-mode", &val)) {
1315                        if (val > 0xf) {
1316                                dev_err(&data->i2c_client->dev,
1317                                        "invalid silabs,common-mode %u\n",
1318                                        val);
1319                                goto put_child;
1320                        }
1321                        config[num].out_cm_ampl_bits &= 0xf0;
1322                        config[num].out_cm_ampl_bits |= val & 0x0f;
1323                }
1324
1325                if (!of_property_read_u32(child, "silabs,amplitude", &val)) {
1326                        if (val > 0xf) {
1327                                dev_err(&data->i2c_client->dev,
1328                                        "invalid silabs,amplitude %u\n",
1329                                        val);
1330                                goto put_child;
1331                        }
1332                        config[num].out_cm_ampl_bits &= 0x0f;
1333                        config[num].out_cm_ampl_bits |= (val << 4) & 0xf0;
1334                }
1335
1336                if (of_property_read_bool(child, "silabs,disable-high"))
1337                        config[num].out_format_drv_bits |= 0x10;
1338
1339                config[num].synth_master =
1340                        of_property_read_bool(child, "silabs,synth-master");
1341
1342                config[num].always_on =
1343                        of_property_read_bool(child, "always-on");
1344
1345                config[num].vdd_sel_bits = 0x08;
1346                if (data->clk[num].vddo_reg) {
1347                        int vdd = regulator_get_voltage(data->clk[num].vddo_reg);
1348
1349                        switch (vdd) {
1350                        case 3300000:
1351                                config[num].vdd_sel_bits |= 0 << 4;
1352                                break;
1353                        case 1800000:
1354                                config[num].vdd_sel_bits |= 1 << 4;
1355                                break;
1356                        case 2500000:
1357                                config[num].vdd_sel_bits |= 2 << 4;
1358                                break;
1359                        default:
1360                                dev_err(&data->i2c_client->dev,
1361                                        "unsupported vddo voltage %d for %s\n",
1362                                        vdd, child->name);
1363                                goto put_child;
1364                        }
1365                } else {
1366                        /* chip seems to default to 2.5V when not set */
1367                        dev_warn(&data->i2c_client->dev,
1368                                "no regulator set, defaulting vdd_sel to 2.5V for %s\n",
1369                                child->name);
1370                        config[num].vdd_sel_bits |= 2 << 4;
1371                }
1372        }
1373
1374        return 0;
1375
1376put_child:
1377        of_node_put(child);
1378        return -EINVAL;
1379}
1380
1381/*
1382 * If not pre-configured, calculate and set the PLL configuration manually.
1383 * For low-jitter performance, the PLL should be set such that the synthesizers
1384 * only need integer division.
1385 * Without any user guidance, we'll set the PLL to 14GHz, which still allows
1386 * the chip to generate any frequency on its outputs, but jitter performance
1387 * may be sub-optimal.
1388 */
1389static int si5341_initialize_pll(struct clk_si5341 *data)
1390{
1391        struct device_node *np = data->i2c_client->dev.of_node;
1392        u32 m_num = 0;
1393        u32 m_den = 0;
1394        int sel;
1395
1396        if (of_property_read_u32(np, "silabs,pll-m-num", &m_num)) {
1397                dev_err(&data->i2c_client->dev,
1398                        "PLL configuration requires silabs,pll-m-num\n");
1399        }
1400        if (of_property_read_u32(np, "silabs,pll-m-den", &m_den)) {
1401                dev_err(&data->i2c_client->dev,
1402                        "PLL configuration requires silabs,pll-m-den\n");
1403        }
1404
1405        if (!m_num || !m_den) {
1406                dev_err(&data->i2c_client->dev,
1407                        "PLL configuration invalid, assume 14GHz\n");
1408                sel = si5341_clk_get_selected_input(data);
1409                if (sel < 0)
1410                        return sel;
1411
1412                m_den = clk_get_rate(data->input_clk[sel]) / 10;
1413                m_num = 1400000000;
1414        }
1415
1416        return si5341_encode_44_32(data->regmap,
1417                        SI5341_PLL_M_NUM, m_num, m_den);
1418}
1419
1420static int si5341_clk_select_active_input(struct clk_si5341 *data)
1421{
1422        int res;
1423        int err;
1424        int i;
1425
1426        res = si5341_clk_get_selected_input(data);
1427        if (res < 0)
1428                return res;
1429
1430        /* If the current register setting is invalid, pick the first input */
1431        if (!data->input_clk[res]) {
1432                dev_dbg(&data->i2c_client->dev,
1433                        "Input %d not connected, rerouting\n", res);
1434                res = -ENODEV;
1435                for (i = 0; i < SI5341_NUM_INPUTS; ++i) {
1436                        if (data->input_clk[i]) {
1437                                res = i;
1438                                break;
1439                        }
1440                }
1441                if (res < 0) {
1442                        dev_err(&data->i2c_client->dev,
1443                                "No clock input available\n");
1444                        return res;
1445                }
1446        }
1447
1448        /* Make sure the selected clock is also enabled and routed */
1449        err = si5341_clk_reparent(data, res);
1450        if (err < 0)
1451                return err;
1452
1453        err = clk_prepare_enable(data->input_clk[res]);
1454        if (err < 0)
1455                return err;
1456
1457        return res;
1458}
1459
1460static ssize_t input_present_show(struct device *dev,
1461                                  struct device_attribute *attr,
1462                                  char *buf)
1463{
1464        struct clk_si5341 *data = dev_get_drvdata(dev);
1465        u32 status;
1466        int res = regmap_read(data->regmap, SI5341_STATUS, &status);
1467
1468        if (res < 0)
1469                return res;
1470        res = !(status & SI5341_STATUS_LOSREF);
1471        return snprintf(buf, PAGE_SIZE, "%d\n", res);
1472}
1473static DEVICE_ATTR_RO(input_present);
1474
1475static ssize_t input_present_sticky_show(struct device *dev,
1476                                         struct device_attribute *attr,
1477                                         char *buf)
1478{
1479        struct clk_si5341 *data = dev_get_drvdata(dev);
1480        u32 status;
1481        int res = regmap_read(data->regmap, SI5341_STATUS_STICKY, &status);
1482
1483        if (res < 0)
1484                return res;
1485        res = !(status & SI5341_STATUS_LOSREF);
1486        return snprintf(buf, PAGE_SIZE, "%d\n", res);
1487}
1488static DEVICE_ATTR_RO(input_present_sticky);
1489
1490static ssize_t pll_locked_show(struct device *dev,
1491                               struct device_attribute *attr,
1492                               char *buf)
1493{
1494        struct clk_si5341 *data = dev_get_drvdata(dev);
1495        u32 status;
1496        int res = regmap_read(data->regmap, SI5341_STATUS, &status);
1497
1498        if (res < 0)
1499                return res;
1500        res = !(status & SI5341_STATUS_LOL);
1501        return snprintf(buf, PAGE_SIZE, "%d\n", res);
1502}
1503static DEVICE_ATTR_RO(pll_locked);
1504
1505static ssize_t pll_locked_sticky_show(struct device *dev,
1506                                      struct device_attribute *attr,
1507                                      char *buf)
1508{
1509        struct clk_si5341 *data = dev_get_drvdata(dev);
1510        u32 status;
1511        int res = regmap_read(data->regmap, SI5341_STATUS_STICKY, &status);
1512
1513        if (res < 0)
1514                return res;
1515        res = !(status & SI5341_STATUS_LOL);
1516        return snprintf(buf, PAGE_SIZE, "%d\n", res);
1517}
1518static DEVICE_ATTR_RO(pll_locked_sticky);
1519
1520static ssize_t clear_sticky_store(struct device *dev,
1521                                  struct device_attribute *attr,
1522                                  const char *buf, size_t count)
1523{
1524        struct clk_si5341 *data = dev_get_drvdata(dev);
1525        long val;
1526
1527        if (kstrtol(buf, 10, &val))
1528                return -EINVAL;
1529        if (val) {
1530                int res = regmap_write(data->regmap, SI5341_STATUS_STICKY, 0);
1531
1532                if (res < 0)
1533                        return res;
1534        }
1535        return count;
1536}
1537static DEVICE_ATTR_WO(clear_sticky);
1538
1539static const struct attribute *si5341_attributes[] = {
1540        &dev_attr_input_present.attr,
1541        &dev_attr_input_present_sticky.attr,
1542        &dev_attr_pll_locked.attr,
1543        &dev_attr_pll_locked_sticky.attr,
1544        &dev_attr_clear_sticky.attr,
1545        NULL
1546};
1547
1548static int si5341_probe(struct i2c_client *client,
1549                const struct i2c_device_id *id)
1550{
1551        struct clk_si5341 *data;
1552        struct clk_init_data init;
1553        struct clk *input;
1554        const char *root_clock_name;
1555        const char *synth_clock_names[SI5341_NUM_SYNTH];
1556        int err;
1557        unsigned int i;
1558        struct clk_si5341_output_config config[SI5341_MAX_NUM_OUTPUTS];
1559        bool initialization_required;
1560        u32 status;
1561
1562        data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
1563        if (!data)
1564                return -ENOMEM;
1565
1566        data->i2c_client = client;
1567
1568        /* Must be done before otherwise touching hardware */
1569        err = si5341_wait_device_ready(client);
1570        if (err)
1571                return err;
1572
1573        for (i = 0; i < SI5341_NUM_INPUTS; ++i) {
1574                input = devm_clk_get(&client->dev, si5341_input_clock_names[i]);
1575                if (IS_ERR(input)) {
1576                        if (PTR_ERR(input) == -EPROBE_DEFER)
1577                                return -EPROBE_DEFER;
1578                        data->input_clk_name[i] = si5341_input_clock_names[i];
1579                } else {
1580                        data->input_clk[i] = input;
1581                        data->input_clk_name[i] = __clk_get_name(input);
1582                }
1583        }
1584
1585        for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) {
1586                char reg_name[10];
1587
1588                snprintf(reg_name, sizeof(reg_name), "vddo%d", i);
1589                data->clk[i].vddo_reg = devm_regulator_get_optional(
1590                        &client->dev, reg_name);
1591                if (IS_ERR(data->clk[i].vddo_reg)) {
1592                        err = PTR_ERR(data->clk[i].vddo_reg);
1593                        data->clk[i].vddo_reg = NULL;
1594                        if (err == -ENODEV)
1595                                continue;
1596                        goto cleanup;
1597                } else {
1598                        err = regulator_enable(data->clk[i].vddo_reg);
1599                        if (err) {
1600                                dev_err(&client->dev,
1601                                        "failed to enable %s regulator: %d\n",
1602                                        reg_name, err);
1603                                data->clk[i].vddo_reg = NULL;
1604                                goto cleanup;
1605                        }
1606                }
1607        }
1608
1609        err = si5341_dt_parse_dt(data, config);
1610        if (err)
1611                goto cleanup;
1612
1613        if (of_property_read_string(client->dev.of_node, "clock-output-names",
1614                        &init.name))
1615                init.name = client->dev.of_node->name;
1616        root_clock_name = init.name;
1617
1618        data->regmap = devm_regmap_init_i2c(client, &si5341_regmap_config);
1619        if (IS_ERR(data->regmap)) {
1620                err = PTR_ERR(data->regmap);
1621                goto cleanup;
1622        }
1623
1624        i2c_set_clientdata(client, data);
1625
1626        err = si5341_probe_chip_id(data);
1627        if (err < 0)
1628                goto cleanup;
1629
1630        if (of_property_read_bool(client->dev.of_node, "silabs,reprogram")) {
1631                initialization_required = true;
1632        } else {
1633                err = si5341_is_programmed_already(data);
1634                if (err < 0)
1635                        goto cleanup;
1636
1637                initialization_required = !err;
1638        }
1639        data->xaxb_ext_clk = of_property_read_bool(client->dev.of_node,
1640                                                   "silabs,xaxb-ext-clk");
1641        data->iovdd_33 = of_property_read_bool(client->dev.of_node,
1642                                               "silabs,iovdd-33");
1643
1644        if (initialization_required) {
1645                /* Populate the regmap cache in preparation for "cache only" */
1646                err = si5341_read_settings(data);
1647                if (err < 0)
1648                        goto cleanup;
1649
1650                err = si5341_send_preamble(data);
1651                if (err < 0)
1652                        goto cleanup;
1653
1654                /*
1655                 * We intend to send all 'final' register values in a single
1656                 * transaction. So cache all register writes until we're done
1657                 * configuring.
1658                 */
1659                regcache_cache_only(data->regmap, true);
1660
1661                /* Write the configuration pairs from the firmware blob */
1662                err = si5341_write_multiple(data, si5341_reg_defaults,
1663                                        ARRAY_SIZE(si5341_reg_defaults));
1664                if (err < 0)
1665                        goto cleanup;
1666        }
1667
1668        /* Input must be up and running at this point */
1669        err = si5341_clk_select_active_input(data);
1670        if (err < 0)
1671                goto cleanup;
1672
1673        if (initialization_required) {
1674                /* PLL configuration is required */
1675                err = si5341_initialize_pll(data);
1676                if (err < 0)
1677                        goto cleanup;
1678        }
1679
1680        /* Register the PLL */
1681        init.parent_names = data->input_clk_name;
1682        init.num_parents = SI5341_NUM_INPUTS;
1683        init.ops = &si5341_clk_ops;
1684        init.flags = 0;
1685        data->hw.init = &init;
1686
1687        err = devm_clk_hw_register(&client->dev, &data->hw);
1688        if (err) {
1689                dev_err(&client->dev, "clock registration failed\n");
1690                goto cleanup;
1691        }
1692
1693        init.num_parents = 1;
1694        init.parent_names = &root_clock_name;
1695        init.ops = &si5341_synth_clk_ops;
1696        for (i = 0; i < data->num_synth; ++i) {
1697                synth_clock_names[i] = devm_kasprintf(&client->dev, GFP_KERNEL,
1698                                "%s.N%u", client->dev.of_node->name, i);
1699                init.name = synth_clock_names[i];
1700                data->synth[i].index = i;
1701                data->synth[i].data = data;
1702                data->synth[i].hw.init = &init;
1703                err = devm_clk_hw_register(&client->dev, &data->synth[i].hw);
1704                if (err) {
1705                        dev_err(&client->dev,
1706                                "synth N%u registration failed\n", i);
1707                }
1708        }
1709
1710        init.num_parents = data->num_synth;
1711        init.parent_names = synth_clock_names;
1712        init.ops = &si5341_output_clk_ops;
1713        for (i = 0; i < data->num_outputs; ++i) {
1714                init.name = kasprintf(GFP_KERNEL, "%s.%d",
1715                        client->dev.of_node->name, i);
1716                init.flags = config[i].synth_master ? CLK_SET_RATE_PARENT : 0;
1717                data->clk[i].index = i;
1718                data->clk[i].data = data;
1719                data->clk[i].hw.init = &init;
1720                if (config[i].out_format_drv_bits & 0x07) {
1721                        regmap_write(data->regmap,
1722                                SI5341_OUT_FORMAT(&data->clk[i]),
1723                                config[i].out_format_drv_bits);
1724                        regmap_write(data->regmap,
1725                                SI5341_OUT_CM(&data->clk[i]),
1726                                config[i].out_cm_ampl_bits);
1727                        regmap_update_bits(data->regmap,
1728                                SI5341_OUT_MUX_SEL(&data->clk[i]),
1729                                SI5341_OUT_MUX_VDD_SEL_MASK,
1730                                config[i].vdd_sel_bits);
1731                }
1732                err = devm_clk_hw_register(&client->dev, &data->clk[i].hw);
1733                kfree(init.name); /* clock framework made a copy of the name */
1734                if (err) {
1735                        dev_err(&client->dev,
1736                                "output %u registration failed\n", i);
1737                        goto cleanup;
1738                }
1739                if (config[i].always_on)
1740                        clk_prepare(data->clk[i].hw.clk);
1741        }
1742
1743        err = of_clk_add_hw_provider(client->dev.of_node, of_clk_si5341_get,
1744                        data);
1745        if (err) {
1746                dev_err(&client->dev, "unable to add clk provider\n");
1747                goto cleanup;
1748        }
1749
1750        if (initialization_required) {
1751                /* Synchronize */
1752                regcache_cache_only(data->regmap, false);
1753                err = regcache_sync(data->regmap);
1754                if (err < 0)
1755                        goto cleanup;
1756
1757                err = si5341_finalize_defaults(data);
1758                if (err < 0)
1759                        goto cleanup;
1760        }
1761
1762        /* wait for device to report input clock present and PLL lock */
1763        err = regmap_read_poll_timeout(data->regmap, SI5341_STATUS, status,
1764                !(status & (SI5341_STATUS_LOSREF | SI5341_STATUS_LOL)),
1765               10000, 250000);
1766        if (err) {
1767                dev_err(&client->dev, "Error waiting for input clock or PLL lock\n");
1768                goto cleanup;
1769        }
1770
1771        /* clear sticky alarm bits from initialization */
1772        err = regmap_write(data->regmap, SI5341_STATUS_STICKY, 0);
1773        if (err) {
1774                dev_err(&client->dev, "unable to clear sticky status\n");
1775                goto cleanup;
1776        }
1777
1778        err = sysfs_create_files(&client->dev.kobj, si5341_attributes);
1779        if (err) {
1780                dev_err(&client->dev, "unable to create sysfs files\n");
1781                goto cleanup;
1782        }
1783
1784        /* Free the names, clk framework makes copies */
1785        for (i = 0; i < data->num_synth; ++i)
1786                 devm_kfree(&client->dev, (void *)synth_clock_names[i]);
1787
1788        return 0;
1789
1790cleanup:
1791        for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) {
1792                if (data->clk[i].vddo_reg)
1793                        regulator_disable(data->clk[i].vddo_reg);
1794        }
1795        return err;
1796}
1797
1798static int si5341_remove(struct i2c_client *client)
1799{
1800        struct clk_si5341 *data = i2c_get_clientdata(client);
1801        int i;
1802
1803        sysfs_remove_files(&client->dev.kobj, si5341_attributes);
1804
1805        for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) {
1806                if (data->clk[i].vddo_reg)
1807                        regulator_disable(data->clk[i].vddo_reg);
1808        }
1809
1810        return 0;
1811}
1812
1813static const struct i2c_device_id si5341_id[] = {
1814        { "si5340", 0 },
1815        { "si5341", 1 },
1816        { "si5342", 2 },
1817        { "si5344", 4 },
1818        { "si5345", 5 },
1819        { }
1820};
1821MODULE_DEVICE_TABLE(i2c, si5341_id);
1822
1823static const struct of_device_id clk_si5341_of_match[] = {
1824        { .compatible = "silabs,si5340" },
1825        { .compatible = "silabs,si5341" },
1826        { .compatible = "silabs,si5342" },
1827        { .compatible = "silabs,si5344" },
1828        { .compatible = "silabs,si5345" },
1829        { }
1830};
1831MODULE_DEVICE_TABLE(of, clk_si5341_of_match);
1832
1833static struct i2c_driver si5341_driver = {
1834        .driver = {
1835                .name = "si5341",
1836                .of_match_table = clk_si5341_of_match,
1837        },
1838        .probe          = si5341_probe,
1839        .remove         = si5341_remove,
1840        .id_table       = si5341_id,
1841};
1842module_i2c_driver(si5341_driver);
1843
1844MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");
1845MODULE_DESCRIPTION("Si5341 driver");
1846MODULE_LICENSE("GPL");
1847