linux/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
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   1/*
   2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
   3 * reserved.
   4 *
   5 * This software is available to you under a choice of one of two
   6 * licenses.  You may choose to be licensed under the terms of the GNU
   7 * General Public License (GPL) Version 2, available from the file
   8 * COPYING in the main directory of this source tree, or the NetLogic
   9 * license below:
  10 *
  11 * Redistribution and use in source and binary forms, with or without
  12 * modification, are permitted provided that the following conditions
  13 * are met:
  14 *
  15 * 1. Redistributions of source code must retain the above copyright
  16 *    notice, this list of conditions and the following disclaimer.
  17 * 2. Redistributions in binary form must reproduce the above copyright
  18 *    notice, this list of conditions and the following disclaimer in
  19 *    the documentation and/or other materials provided with the
  20 *    distribution.
  21 *
  22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
  23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
  26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33 */
  34
  35#ifndef __NLM_HAL_IOMAP_H__
  36#define __NLM_HAL_IOMAP_H__
  37
  38#define XLP_DEFAULT_IO_BASE             0x18000000
  39#define XLP_DEFAULT_PCI_ECFG_BASE       XLP_DEFAULT_IO_BASE
  40#define XLP_DEFAULT_PCI_CFG_BASE        0x1c000000
  41
  42#define NMI_BASE                        0xbfc00000
  43#define XLP_IO_CLK                      133333333
  44
  45#define XLP_PCIE_CFG_SIZE               0x1000          /* 4K */
  46#define XLP_PCIE_DEV_BLK_SIZE           (8 * XLP_PCIE_CFG_SIZE)
  47#define XLP_PCIE_BUS_BLK_SIZE           (256 * XLP_PCIE_DEV_BLK_SIZE)
  48#define XLP_IO_SIZE                     (64 << 20)      /* ECFG space size */
  49#define XLP_IO_PCI_HDRSZ                0x100
  50#define XLP_IO_DEV(node, dev)           ((dev) + (node) * 8)
  51#define XLP_IO_PCI_OFFSET(b, d, f)      (((b) << 20) | ((d) << 15) | ((f) << 12))
  52
  53#define XLP_HDR_OFFSET(node, bus, dev, fn) \
  54                XLP_IO_PCI_OFFSET(bus, XLP_IO_DEV(node, dev), fn)
  55
  56#define XLP_IO_BRIDGE_OFFSET(node)      XLP_HDR_OFFSET(node, 0, 0, 0)
  57/* coherent inter chip */
  58#define XLP_IO_CIC0_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 0, 1)
  59#define XLP_IO_CIC1_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 0, 2)
  60#define XLP_IO_CIC2_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 0, 3)
  61#define XLP_IO_PIC_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 0, 4)
  62
  63#define XLP_IO_PCIE_OFFSET(node, i)     XLP_HDR_OFFSET(node, 0, 1, i)
  64#define XLP_IO_PCIE0_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 1, 0)
  65#define XLP_IO_PCIE1_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 1, 1)
  66#define XLP_IO_PCIE2_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 1, 2)
  67#define XLP_IO_PCIE3_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 1, 3)
  68
  69#define XLP_IO_USB_OFFSET(node, i)      XLP_HDR_OFFSET(node, 0, 2, i)
  70#define XLP_IO_USB_EHCI0_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 0)
  71#define XLP_IO_USB_OHCI0_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 1)
  72#define XLP_IO_USB_OHCI1_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 2)
  73#define XLP_IO_USB_EHCI1_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 3)
  74#define XLP_IO_USB_OHCI2_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 4)
  75#define XLP_IO_USB_OHCI3_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 5)
  76
  77#define XLP_IO_SATA_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 3, 2)
  78
  79/* XLP2xx has an updated USB block */
  80#define XLP2XX_IO_USB_OFFSET(node, i)   XLP_HDR_OFFSET(node, 0, 4, i)
  81#define XLP2XX_IO_USB_XHCI0_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 4, 1)
  82#define XLP2XX_IO_USB_XHCI1_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 4, 2)
  83#define XLP2XX_IO_USB_XHCI2_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 4, 3)
  84
  85#define XLP_IO_NAE_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 3, 0)
  86#define XLP_IO_POE_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 3, 1)
  87
  88#define XLP_IO_CMS_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 4, 0)
  89
  90#define XLP_IO_DMA_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 5, 1)
  91#define XLP_IO_SEC_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 5, 2)
  92#define XLP_IO_CMP_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 5, 3)
  93
  94#define XLP_IO_UART_OFFSET(node, i)     XLP_HDR_OFFSET(node, 0, 6, i)
  95#define XLP_IO_UART0_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 6, 0)
  96#define XLP_IO_UART1_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 6, 1)
  97#define XLP_IO_I2C_OFFSET(node, i)      XLP_HDR_OFFSET(node, 0, 6, 2 + i)
  98#define XLP_IO_I2C0_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 6, 2)
  99#define XLP_IO_I2C1_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 6, 3)
 100#define XLP_IO_GPIO_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 6, 4)
 101/* on 2XX, all I2C busses are on the same block */
 102#define XLP2XX_IO_I2C_OFFSET(node)      XLP_HDR_OFFSET(node, 0, 6, 7)
 103
 104/* system management */
 105#define XLP_IO_SYS_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 6, 5)
 106#define XLP_IO_JTAG_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 6, 6)
 107
 108/* Flash */
 109#define XLP_IO_NOR_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 7, 0)
 110#define XLP_IO_NAND_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 7, 1)
 111#define XLP_IO_SPI_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 7, 2)
 112#define XLP_IO_MMC_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 7, 3)
 113
 114/* Things have changed drastically in XLP 9XX */
 115#define XLP9XX_HDR_OFFSET(n, d, f)      \
 116                        XLP_IO_PCI_OFFSET(xlp9xx_get_socbus(n), d, f)
 117
 118#define XLP9XX_IO_BRIDGE_OFFSET(node)   XLP_IO_PCI_OFFSET(0, 0, node)
 119#define XLP9XX_IO_PIC_OFFSET(node)      XLP9XX_HDR_OFFSET(node, 2, 0)
 120#define XLP9XX_IO_UART_OFFSET(node)     XLP9XX_HDR_OFFSET(node, 2, 2)
 121#define XLP9XX_IO_SYS_OFFSET(node)      XLP9XX_HDR_OFFSET(node, 6, 0)
 122#define XLP9XX_IO_FUSE_OFFSET(node)     XLP9XX_HDR_OFFSET(node, 6, 1)
 123#define XLP9XX_IO_CLOCK_OFFSET(node)    XLP9XX_HDR_OFFSET(node, 6, 2)
 124#define XLP9XX_IO_POWER_OFFSET(node)    XLP9XX_HDR_OFFSET(node, 6, 3)
 125#define XLP9XX_IO_JTAG_OFFSET(node)     XLP9XX_HDR_OFFSET(node, 6, 4)
 126
 127#define XLP9XX_IO_PCIE_OFFSET(node, i)  XLP9XX_HDR_OFFSET(node, 1, i)
 128#define XLP9XX_IO_PCIE0_OFFSET(node)    XLP9XX_HDR_OFFSET(node, 1, 0)
 129#define XLP9XX_IO_PCIE2_OFFSET(node)    XLP9XX_HDR_OFFSET(node, 1, 2)
 130#define XLP9XX_IO_PCIE3_OFFSET(node)    XLP9XX_HDR_OFFSET(node, 1, 3)
 131
 132/* XLP9xx USB block */
 133#define XLP9XX_IO_USB_OFFSET(node, i)           XLP9XX_HDR_OFFSET(node, 4, i)
 134#define XLP9XX_IO_USB_XHCI0_OFFSET(node)        XLP9XX_HDR_OFFSET(node, 4, 1)
 135#define XLP9XX_IO_USB_XHCI1_OFFSET(node)        XLP9XX_HDR_OFFSET(node, 4, 2)
 136
 137/* XLP9XX on-chip SATA controller */
 138#define XLP9XX_IO_SATA_OFFSET(node)             XLP9XX_HDR_OFFSET(node, 3, 2)
 139
 140/* Flash */
 141#define XLP9XX_IO_NOR_OFFSET(node)              XLP9XX_HDR_OFFSET(node, 7, 0)
 142#define XLP9XX_IO_NAND_OFFSET(node)             XLP9XX_HDR_OFFSET(node, 7, 1)
 143#define XLP9XX_IO_SPI_OFFSET(node)              XLP9XX_HDR_OFFSET(node, 7, 2)
 144#define XLP9XX_IO_MMC_OFFSET(node)              XLP9XX_HDR_OFFSET(node, 7, 3)
 145
 146/* PCI config header register id's */
 147#define XLP_PCI_CFGREG0                 0x00
 148#define XLP_PCI_CFGREG1                 0x01
 149#define XLP_PCI_CFGREG2                 0x02
 150#define XLP_PCI_CFGREG3                 0x03
 151#define XLP_PCI_CFGREG4                 0x04
 152#define XLP_PCI_CFGREG5                 0x05
 153#define XLP_PCI_DEVINFO_REG0            0x30
 154#define XLP_PCI_DEVINFO_REG1            0x31
 155#define XLP_PCI_DEVINFO_REG2            0x32
 156#define XLP_PCI_DEVINFO_REG3            0x33
 157#define XLP_PCI_DEVINFO_REG4            0x34
 158#define XLP_PCI_DEVINFO_REG5            0x35
 159#define XLP_PCI_DEVINFO_REG6            0x36
 160#define XLP_PCI_DEVINFO_REG7            0x37
 161#define XLP_PCI_DEVSCRATCH_REG0         0x38
 162#define XLP_PCI_DEVSCRATCH_REG1         0x39
 163#define XLP_PCI_DEVSCRATCH_REG2         0x3a
 164#define XLP_PCI_DEVSCRATCH_REG3         0x3b
 165#define XLP_PCI_MSGSTN_REG              0x3c
 166#define XLP_PCI_IRTINFO_REG             0x3d
 167#define XLP_PCI_UCODEINFO_REG           0x3e
 168#define XLP_PCI_SBB_WT_REG              0x3f
 169
 170/* PCI IDs for SoC device */
 171#define PCI_VENDOR_NETLOGIC             0x184e
 172
 173#define PCI_DEVICE_ID_NLM_ROOT          0x1001
 174#define PCI_DEVICE_ID_NLM_ICI           0x1002
 175#define PCI_DEVICE_ID_NLM_PIC           0x1003
 176#define PCI_DEVICE_ID_NLM_PCIE          0x1004
 177#define PCI_DEVICE_ID_NLM_EHCI          0x1007
 178#define PCI_DEVICE_ID_NLM_OHCI          0x1008
 179#define PCI_DEVICE_ID_NLM_NAE           0x1009
 180#define PCI_DEVICE_ID_NLM_POE           0x100A
 181#define PCI_DEVICE_ID_NLM_FMN           0x100B
 182#define PCI_DEVICE_ID_NLM_RAID          0x100D
 183#define PCI_DEVICE_ID_NLM_SAE           0x100D
 184#define PCI_DEVICE_ID_NLM_RSA           0x100E
 185#define PCI_DEVICE_ID_NLM_CMP           0x100F
 186#define PCI_DEVICE_ID_NLM_UART          0x1010
 187#define PCI_DEVICE_ID_NLM_I2C           0x1011
 188#define PCI_DEVICE_ID_NLM_NOR           0x1015
 189#define PCI_DEVICE_ID_NLM_NAND          0x1016
 190#define PCI_DEVICE_ID_NLM_MMC           0x1018
 191#define PCI_DEVICE_ID_NLM_SATA          0x101A
 192#define PCI_DEVICE_ID_NLM_XHCI          0x101D
 193
 194#define PCI_DEVICE_ID_XLP9XX_MMC        0x9018
 195#define PCI_DEVICE_ID_XLP9XX_SATA       0x901A
 196#define PCI_DEVICE_ID_XLP9XX_XHCI       0x901D
 197
 198#ifndef __ASSEMBLY__
 199
 200#define nlm_read_pci_reg(b, r)          nlm_read_reg(b, r)
 201#define nlm_write_pci_reg(b, r, v)      nlm_write_reg(b, r, v)
 202
 203static inline int xlp9xx_get_socbus(int node)
 204{
 205        uint64_t socbridge;
 206
 207        if (node == 0)
 208                return 1;
 209        socbridge = nlm_pcicfg_base(XLP9XX_IO_BRIDGE_OFFSET(node));
 210        return (nlm_read_pci_reg(socbridge, 0x6) >> 8) & 0xff;
 211}
 212#endif /* !__ASSEMBLY */
 213
 214#endif /* __NLM_HAL_IOMAP_H__ */
 215