linux/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
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   1/*
   2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
   3 * reserved.
   4 *
   5 * This software is available to you under a choice of one of two
   6 * licenses.  You may choose to be licensed under the terms of the GNU
   7 * General Public License (GPL) Version 2, available from the file
   8 * COPYING in the main directory of this source tree, or the NetLogic
   9 * license below:
  10 *
  11 * Redistribution and use in source and binary forms, with or without
  12 * modification, are permitted provided that the following conditions
  13 * are met:
  14 *
  15 * 1. Redistributions of source code must retain the above copyright
  16 *    notice, this list of conditions and the following disclaimer.
  17 * 2. Redistributions in binary form must reproduce the above copyright
  18 *    notice, this list of conditions and the following disclaimer in
  19 *    the documentation and/or other materials provided with the
  20 *    distribution.
  21 *
  22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
  23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
  26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33 */
  34
  35#ifndef __NLM_HAL_BRIDGE_H__
  36#define __NLM_HAL_BRIDGE_H__
  37
  38/**
  39* @file_name mio.h
  40* @author Netlogic Microsystems
  41* @brief Basic definitions of XLP memory and io subsystem
  42*/
  43
  44/*
  45 * BRIDGE specific registers
  46 *
  47 * These registers start after the PCIe header, which has 0x40
  48 * standard entries
  49 */
  50#define BRIDGE_MODE                     0x00
  51#define BRIDGE_PCI_CFG_BASE             0x01
  52#define BRIDGE_PCI_CFG_LIMIT            0x02
  53#define BRIDGE_PCIE_CFG_BASE            0x03
  54#define BRIDGE_PCIE_CFG_LIMIT           0x04
  55#define BRIDGE_BUSNUM_BAR0              0x05
  56#define BRIDGE_BUSNUM_BAR1              0x06
  57#define BRIDGE_BUSNUM_BAR2              0x07
  58#define BRIDGE_BUSNUM_BAR3              0x08
  59#define BRIDGE_BUSNUM_BAR4              0x09
  60#define BRIDGE_BUSNUM_BAR5              0x0a
  61#define BRIDGE_BUSNUM_BAR6              0x0b
  62#define BRIDGE_FLASH_BAR0               0x0c
  63#define BRIDGE_FLASH_BAR1               0x0d
  64#define BRIDGE_FLASH_BAR2               0x0e
  65#define BRIDGE_FLASH_BAR3               0x0f
  66#define BRIDGE_FLASH_LIMIT0             0x10
  67#define BRIDGE_FLASH_LIMIT1             0x11
  68#define BRIDGE_FLASH_LIMIT2             0x12
  69#define BRIDGE_FLASH_LIMIT3             0x13
  70
  71#define BRIDGE_DRAM_BAR(i)              (0x14 + (i))
  72#define BRIDGE_DRAM_LIMIT(i)            (0x1c + (i))
  73#define BRIDGE_DRAM_NODE_TRANSLN(i)     (0x24 + (i))
  74#define BRIDGE_DRAM_CHNL_TRANSLN(i)     (0x2c + (i))
  75
  76#define BRIDGE_PCIEMEM_BASE0            0x34
  77#define BRIDGE_PCIEMEM_BASE1            0x35
  78#define BRIDGE_PCIEMEM_BASE2            0x36
  79#define BRIDGE_PCIEMEM_BASE3            0x37
  80#define BRIDGE_PCIEMEM_LIMIT0           0x38
  81#define BRIDGE_PCIEMEM_LIMIT1           0x39
  82#define BRIDGE_PCIEMEM_LIMIT2           0x3a
  83#define BRIDGE_PCIEMEM_LIMIT3           0x3b
  84#define BRIDGE_PCIEIO_BASE0             0x3c
  85#define BRIDGE_PCIEIO_BASE1             0x3d
  86#define BRIDGE_PCIEIO_BASE2             0x3e
  87#define BRIDGE_PCIEIO_BASE3             0x3f
  88#define BRIDGE_PCIEIO_LIMIT0            0x40
  89#define BRIDGE_PCIEIO_LIMIT1            0x41
  90#define BRIDGE_PCIEIO_LIMIT2            0x42
  91#define BRIDGE_PCIEIO_LIMIT3            0x43
  92#define BRIDGE_PCIEMEM_BASE4            0x44
  93#define BRIDGE_PCIEMEM_BASE5            0x45
  94#define BRIDGE_PCIEMEM_BASE6            0x46
  95#define BRIDGE_PCIEMEM_LIMIT4           0x47
  96#define BRIDGE_PCIEMEM_LIMIT5           0x48
  97#define BRIDGE_PCIEMEM_LIMIT6           0x49
  98#define BRIDGE_PCIEIO_BASE4             0x4a
  99#define BRIDGE_PCIEIO_BASE5             0x4b
 100#define BRIDGE_PCIEIO_BASE6             0x4c
 101#define BRIDGE_PCIEIO_LIMIT4            0x4d
 102#define BRIDGE_PCIEIO_LIMIT5            0x4e
 103#define BRIDGE_PCIEIO_LIMIT6            0x4f
 104#define BRIDGE_NBU_EVENT_CNT_CTL        0x50
 105#define BRIDGE_EVNTCTR1_LOW             0x51
 106#define BRIDGE_EVNTCTR1_HI              0x52
 107#define BRIDGE_EVNT_CNT_CTL2            0x53
 108#define BRIDGE_EVNTCTR2_LOW             0x54
 109#define BRIDGE_EVNTCTR2_HI              0x55
 110#define BRIDGE_TRACEBUF_MATCH0          0x56
 111#define BRIDGE_TRACEBUF_MATCH1          0x57
 112#define BRIDGE_TRACEBUF_MATCH_LOW       0x58
 113#define BRIDGE_TRACEBUF_MATCH_HI        0x59
 114#define BRIDGE_TRACEBUF_CTRL            0x5a
 115#define BRIDGE_TRACEBUF_INIT            0x5b
 116#define BRIDGE_TRACEBUF_ACCESS          0x5c
 117#define BRIDGE_TRACEBUF_READ_DATA0      0x5d
 118#define BRIDGE_TRACEBUF_READ_DATA1      0x5d
 119#define BRIDGE_TRACEBUF_READ_DATA2      0x5f
 120#define BRIDGE_TRACEBUF_READ_DATA3      0x60
 121#define BRIDGE_TRACEBUF_STATUS          0x61
 122#define BRIDGE_ADDRESS_ERROR0           0x62
 123#define BRIDGE_ADDRESS_ERROR1           0x63
 124#define BRIDGE_ADDRESS_ERROR2           0x64
 125#define BRIDGE_TAG_ECC_ADDR_ERROR0      0x65
 126#define BRIDGE_TAG_ECC_ADDR_ERROR1      0x66
 127#define BRIDGE_TAG_ECC_ADDR_ERROR2      0x67
 128#define BRIDGE_LINE_FLUSH0              0x68
 129#define BRIDGE_LINE_FLUSH1              0x69
 130#define BRIDGE_NODE_ID                  0x6a
 131#define BRIDGE_ERROR_INTERRUPT_EN       0x6b
 132#define BRIDGE_PCIE0_WEIGHT             0x2c0
 133#define BRIDGE_PCIE1_WEIGHT             0x2c1
 134#define BRIDGE_PCIE2_WEIGHT             0x2c2
 135#define BRIDGE_PCIE3_WEIGHT             0x2c3
 136#define BRIDGE_USB_WEIGHT               0x2c4
 137#define BRIDGE_NET_WEIGHT               0x2c5
 138#define BRIDGE_POE_WEIGHT               0x2c6
 139#define BRIDGE_CMS_WEIGHT               0x2c7
 140#define BRIDGE_DMAENG_WEIGHT            0x2c8
 141#define BRIDGE_SEC_WEIGHT               0x2c9
 142#define BRIDGE_COMP_WEIGHT              0x2ca
 143#define BRIDGE_GIO_WEIGHT               0x2cb
 144#define BRIDGE_FLASH_WEIGHT             0x2cc
 145
 146/* FIXME verify */
 147#define BRIDGE_9XX_FLASH_BAR(i)         (0x11 + (i))
 148#define BRIDGE_9XX_FLASH_BAR_LIMIT(i)   (0x15 + (i))
 149
 150#define BRIDGE_9XX_DRAM_BAR(i)          (0x19 + (i))
 151#define BRIDGE_9XX_DRAM_LIMIT(i)        (0x29 + (i))
 152#define BRIDGE_9XX_DRAM_NODE_TRANSLN(i) (0x39 + (i))
 153#define BRIDGE_9XX_DRAM_CHNL_TRANSLN(i) (0x49 + (i))
 154
 155#define BRIDGE_9XX_ADDRESS_ERROR0       0x9d
 156#define BRIDGE_9XX_ADDRESS_ERROR1       0x9e
 157#define BRIDGE_9XX_ADDRESS_ERROR2       0x9f
 158
 159#define BRIDGE_9XX_PCIEMEM_BASE0        0x59
 160#define BRIDGE_9XX_PCIEMEM_BASE1        0x5a
 161#define BRIDGE_9XX_PCIEMEM_BASE2        0x5b
 162#define BRIDGE_9XX_PCIEMEM_BASE3        0x5c
 163#define BRIDGE_9XX_PCIEMEM_LIMIT0       0x5d
 164#define BRIDGE_9XX_PCIEMEM_LIMIT1       0x5e
 165#define BRIDGE_9XX_PCIEMEM_LIMIT2       0x5f
 166#define BRIDGE_9XX_PCIEMEM_LIMIT3       0x60
 167#define BRIDGE_9XX_PCIEIO_BASE0         0x61
 168#define BRIDGE_9XX_PCIEIO_BASE1         0x62
 169#define BRIDGE_9XX_PCIEIO_BASE2         0x63
 170#define BRIDGE_9XX_PCIEIO_BASE3         0x64
 171#define BRIDGE_9XX_PCIEIO_LIMIT0        0x65
 172#define BRIDGE_9XX_PCIEIO_LIMIT1        0x66
 173#define BRIDGE_9XX_PCIEIO_LIMIT2        0x67
 174#define BRIDGE_9XX_PCIEIO_LIMIT3        0x68
 175
 176#ifndef __ASSEMBLY__
 177
 178#define nlm_read_bridge_reg(b, r)       nlm_read_reg(b, r)
 179#define nlm_write_bridge_reg(b, r, v)   nlm_write_reg(b, r, v)
 180#define nlm_get_bridge_pcibase(node)    nlm_pcicfg_base(cpu_is_xlp9xx() ? \
 181                XLP9XX_IO_BRIDGE_OFFSET(node) : XLP_IO_BRIDGE_OFFSET(node))
 182#define nlm_get_bridge_regbase(node)    \
 183                        (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ)
 184
 185#endif /* __ASSEMBLY__ */
 186#endif /* __NLM_HAL_BRIDGE_H__ */
 187