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7#ifndef __MIPS_ASM_MIPS_CPS_H__
8# error Please include asm/mips-cps.h rather than asm/mips-gic.h
9#endif
10
11#ifndef __MIPS_ASM_MIPS_GIC_H__
12#define __MIPS_ASM_MIPS_GIC_H__
13
14#include <linux/bitops.h>
15
16
17extern void __iomem *mips_gic_base;
18
19
20#define MIPS_GIC_SHARED_OFS 0x00000
21#define MIPS_GIC_SHARED_SZ 0x08000
22#define MIPS_GIC_LOCAL_OFS 0x08000
23#define MIPS_GIC_LOCAL_SZ 0x04000
24#define MIPS_GIC_REDIR_OFS 0x0c000
25#define MIPS_GIC_REDIR_SZ 0x04000
26#define MIPS_GIC_USER_OFS 0x10000
27#define MIPS_GIC_USER_SZ 0x10000
28
29
30#define GIC_ACCESSOR_RO(sz, off, name) \
31 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_SHARED_OFS + off, name)
32
33
34#define GIC_ACCESSOR_RW(sz, off, name) \
35 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name)
36
37
38#define GIC_VX_ACCESSOR_RO(sz, off, name) \
39 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name) \
40 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)
41
42
43#define GIC_VX_ACCESSOR_RW(sz, off, name) \
44 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name) \
45 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)
46
47
48#define GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \
49static inline void __iomem *addr_gic_##name(unsigned int intr) \
50{ \
51 return mips_gic_base + (off) + (intr * (stride)); \
52} \
53 \
54static inline unsigned int read_gic_##name(unsigned int intr) \
55{ \
56 BUILD_BUG_ON(sz != 32); \
57 return __raw_readl(addr_gic_##name(intr)); \
58}
59
60
61#define GIC_ACCESSOR_RW_INTR_REG(sz, off, stride, name) \
62 GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \
63 \
64static inline void write_gic_##name(unsigned int intr, \
65 unsigned int val) \
66{ \
67 BUILD_BUG_ON(sz != 32); \
68 __raw_writel(val, addr_gic_##name(intr)); \
69}
70
71
72#define GIC_VX_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \
73 GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off, \
74 stride, vl_##name) \
75 GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, \
76 stride, vo_##name)
77
78
79#define GIC_VX_ACCESSOR_RW_INTR_REG(sz, off, stride, name) \
80 GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off, \
81 stride, vl_##name) \
82 GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, \
83 stride, vo_##name)
84
85
86#define GIC_ACCESSOR_RO_INTR_BIT(off, name) \
87static inline void __iomem *addr_gic_##name(void) \
88{ \
89 return mips_gic_base + (off); \
90} \
91 \
92static inline unsigned int read_gic_##name(unsigned int intr) \
93{ \
94 void __iomem *addr = addr_gic_##name(); \
95 unsigned int val; \
96 \
97 if (mips_cm_is64) { \
98 addr += (intr / 64) * sizeof(uint64_t); \
99 val = __raw_readq(addr) >> intr % 64; \
100 } else { \
101 addr += (intr / 32) * sizeof(uint32_t); \
102 val = __raw_readl(addr) >> intr % 32; \
103 } \
104 \
105 return val & 0x1; \
106}
107
108
109#define GIC_ACCESSOR_RW_INTR_BIT(off, name) \
110 GIC_ACCESSOR_RO_INTR_BIT(off, name) \
111 \
112static inline void write_gic_##name(unsigned int intr) \
113{ \
114 void __iomem *addr = addr_gic_##name(); \
115 \
116 if (mips_cm_is64) { \
117 addr += (intr / 64) * sizeof(uint64_t); \
118 __raw_writeq(BIT(intr % 64), addr); \
119 } else { \
120 addr += (intr / 32) * sizeof(uint32_t); \
121 __raw_writel(BIT(intr % 32), addr); \
122 } \
123} \
124 \
125static inline void change_gic_##name(unsigned int intr, \
126 unsigned int val) \
127{ \
128 void __iomem *addr = addr_gic_##name(); \
129 \
130 if (mips_cm_is64) { \
131 uint64_t _val; \
132 \
133 addr += (intr / 64) * sizeof(uint64_t); \
134 _val = __raw_readq(addr); \
135 _val &= ~BIT_ULL(intr % 64); \
136 _val |= (uint64_t)val << (intr % 64); \
137 __raw_writeq(_val, addr); \
138 } else { \
139 uint32_t _val; \
140 \
141 addr += (intr / 32) * sizeof(uint32_t); \
142 _val = __raw_readl(addr); \
143 _val &= ~BIT(intr % 32); \
144 _val |= val << (intr % 32); \
145 __raw_writel(_val, addr); \
146 } \
147}
148
149
150#define GIC_VX_ACCESSOR_RO_INTR_BIT(sz, off, name) \
151 GIC_ACCESSOR_RO_INTR_BIT(sz, MIPS_GIC_LOCAL_OFS + off, \
152 vl_##name) \
153 GIC_ACCESSOR_RO_INTR_BIT(sz, MIPS_GIC_REDIR_OFS + off, \
154 vo_##name)
155
156
157#define GIC_VX_ACCESSOR_RW_INTR_BIT(sz, off, name) \
158 GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_LOCAL_OFS + off, \
159 vl_##name) \
160 GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_REDIR_OFS + off, \
161 vo_##name)
162
163
164GIC_ACCESSOR_RW(32, 0x000, config)
165#define GIC_CONFIG_COUNTSTOP BIT(28)
166#define GIC_CONFIG_COUNTBITS GENMASK(27, 24)
167#define GIC_CONFIG_NUMINTERRUPTS GENMASK(23, 16)
168#define GIC_CONFIG_PVPS GENMASK(6, 0)
169
170
171GIC_ACCESSOR_RW(64, 0x010, counter)
172GIC_ACCESSOR_RW(32, 0x010, counter_32l)
173GIC_ACCESSOR_RW(32, 0x014, counter_32h)
174
175
176GIC_ACCESSOR_RW_INTR_BIT(0x100, pol)
177#define GIC_POL_ACTIVE_LOW 0
178#define GIC_POL_ACTIVE_HIGH 1
179#define GIC_POL_FALLING_EDGE 0
180#define GIC_POL_RISING_EDGE 1
181
182
183GIC_ACCESSOR_RW_INTR_BIT(0x180, trig)
184#define GIC_TRIG_LEVEL 0
185#define GIC_TRIG_EDGE 1
186
187
188GIC_ACCESSOR_RW_INTR_BIT(0x200, dual)
189#define GIC_DUAL_SINGLE 0
190#define GIC_DUAL_DUAL 1
191
192
193GIC_ACCESSOR_RW(32, 0x280, wedge)
194#define GIC_WEDGE_RW BIT(31)
195#define GIC_WEDGE_INTR GENMASK(7, 0)
196
197
198GIC_ACCESSOR_RW_INTR_BIT(0x300, rmask)
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200
201GIC_ACCESSOR_RW_INTR_BIT(0x380, smask)
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203
204GIC_ACCESSOR_RO_INTR_BIT(0x400, mask)
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206
207GIC_ACCESSOR_RO_INTR_BIT(0x480, pend)
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209
210GIC_ACCESSOR_RW_INTR_REG(32, 0x500, 0x4, map_pin)
211#define GIC_MAP_PIN_MAP_TO_PIN BIT(31)
212#define GIC_MAP_PIN_MAP_TO_NMI BIT(30)
213#define GIC_MAP_PIN_MAP GENMASK(5, 0)
214
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216GIC_ACCESSOR_RW_INTR_REG(32, 0x2000, 0x20, map_vp)
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219GIC_VX_ACCESSOR_RW(32, 0x000, ctl)
220#define GIC_VX_CTL_FDC_ROUTABLE BIT(4)
221#define GIC_VX_CTL_SWINT_ROUTABLE BIT(3)
222#define GIC_VX_CTL_PERFCNT_ROUTABLE BIT(2)
223#define GIC_VX_CTL_TIMER_ROUTABLE BIT(1)
224#define GIC_VX_CTL_EIC BIT(0)
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227GIC_VX_ACCESSOR_RO(32, 0x004, pend)
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230GIC_VX_ACCESSOR_RO(32, 0x008, mask)
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233GIC_VX_ACCESSOR_RW(32, 0x00c, rmask)
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236GIC_VX_ACCESSOR_RW(32, 0x010, smask)
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239GIC_VX_ACCESSOR_RW_INTR_REG(32, 0x040, 0x4, map)
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242GIC_VX_ACCESSOR_RW(32, 0x040, wd_map)
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245GIC_VX_ACCESSOR_RW(32, 0x044, compare_map)
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248GIC_VX_ACCESSOR_RW(32, 0x048, timer_map)
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251GIC_VX_ACCESSOR_RW(32, 0x04c, fdc_map)
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254GIC_VX_ACCESSOR_RW(32, 0x050, perfctr_map)
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257GIC_VX_ACCESSOR_RW(32, 0x054, swint0_map)
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260GIC_VX_ACCESSOR_RW(32, 0x058, swint1_map)
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263GIC_VX_ACCESSOR_RW(32, 0x080, other)
264#define GIC_VX_OTHER_VPNUM GENMASK(5, 0)
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267GIC_VX_ACCESSOR_RO(32, 0x088, ident)
268#define GIC_VX_IDENT_VPNUM GENMASK(5, 0)
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271GIC_VX_ACCESSOR_RW(64, 0x0a0, compare)
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274GIC_VX_ACCESSOR_RW_INTR_REG(32, 0x100, 0x4, eic_shadow_set)
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289enum mips_gic_local_interrupt {
290 GIC_LOCAL_INT_WD,
291 GIC_LOCAL_INT_COMPARE,
292 GIC_LOCAL_INT_TIMER,
293 GIC_LOCAL_INT_PERFCTR,
294 GIC_LOCAL_INT_SWINT0,
295 GIC_LOCAL_INT_SWINT1,
296 GIC_LOCAL_INT_FDC,
297 GIC_NUM_LOCAL_INTRS
298};
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308static inline bool mips_gic_present(void)
309{
310 return IS_ENABLED(CONFIG_MIPS_GIC) && mips_gic_base;
311}
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328static inline unsigned int
329mips_gic_vx_map_reg(enum mips_gic_local_interrupt intr)
330{
331
332 if (intr <= GIC_LOCAL_INT_TIMER)
333 return intr;
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336 if (intr == GIC_LOCAL_INT_FDC)
337 return GIC_LOCAL_INT_TIMER + 1;
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339
340 return intr + 1;
341}
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351extern int gic_get_c0_compare_int(void);
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361extern int gic_get_c0_perfcount_int(void);
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371extern int gic_get_c0_fdc_int(void);
372
373#endif
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