LXR linux/drivers/thunderbolt/tb

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Thunderbolt driver - Port/Switch config area registers
   4 *
   5 * Every thunderbolt device consists (logically) of a switch with multiple
   6 * ports. Every port contains up to four config regions (HOPS, PORT, SWITCH,
   7 * COUNTERS) which are used to configure the device.
   8 *
   9 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
  10 * Copyright (C) 2018, Intel Corporation
  11 */
  12
  13#ifndef _TB_REGS
  14#define _TB_REGS
  15
  16#include <linux/types.h>
  17
  18
  19#define TB_ROUTE_SHIFT 8  /* number of bits in a port entry of a route */
  20
  21
  22/*
  23 * TODO: should be 63? But we do not know how to receive frames larger than 256
  24 * bytes at the frame level. (header + checksum = 16, 60*4 = 240)
  25 */
  26#define TB_MAX_CONFIG_RW_LENGTH 60
  27
  28enum tb_switch_cap {
  29        TB_SWITCH_CAP_TMU               = 0x03,
  30        TB_SWITCH_CAP_VSE               = 0x05,
  31};
  32
  33enum tb_switch_vse_cap {
  34        TB_VSE_CAP_PLUG_EVENTS          = 0x01, /* also EEPROM */
  35        TB_VSE_CAP_TIME2                = 0x03,
  36        TB_VSE_CAP_IECS                 = 0x04,
  37        TB_VSE_CAP_LINK_CONTROLLER      = 0x06, /* also IECS */
  38};
  39
  40enum tb_port_cap {
  41        TB_PORT_CAP_PHY                 = 0x01,
  42        TB_PORT_CAP_POWER               = 0x02,
  43        TB_PORT_CAP_TIME1               = 0x03,
  44        TB_PORT_CAP_ADAP                = 0x04,
  45        TB_PORT_CAP_VSE                 = 0x05,
  46        TB_PORT_CAP_USB4                = 0x06,
  47};
  48
  49enum tb_port_state {
  50        TB_PORT_DISABLED        = 0, /* tb_cap_phy.disable == 1 */
  51        TB_PORT_CONNECTING      = 1, /* retry */
  52        TB_PORT_UP              = 2,
  53        TB_PORT_UNPLUGGED       = 7,
  54};
  55
  56/* capability headers */
  57
  58struct tb_cap_basic {
  59        u8 next;
  60        /* enum tb_cap cap:8; prevent "narrower than values of its type" */
  61        u8 cap; /* if cap == 0x05 then we have a extended capability */
  62} __packed;
  63
  64/**
  65 * struct tb_cap_extended_short - Switch extended short capability
  66 * @next: Pointer to the next capability. If @next and @length are zero
  67 *        then we have a long cap.
  68 * @cap: Base capability ID (see &enum tb_switch_cap)
  69 * @vsec_id: Vendor specific capability ID (see &enum switch_vse_cap)
  70 * @length: Length of this capability
  71 */
  72struct tb_cap_extended_short {
  73        u8 next;
  74        u8 cap;
  75        u8 vsec_id;
  76        u8 length;
  77} __packed;
  78
  79/**
  80 * struct tb_cap_extended_long - Switch extended long capability
  81 * @zero1: This field should be zero
  82 * @cap: Base capability ID (see &enum tb_switch_cap)
  83 * @vsec_id: Vendor specific capability ID (see &enum switch_vse_cap)
  84 * @zero2: This field should be zero
  85 * @next: Pointer to the next capability
  86 * @length: Length of this capability
  87 */
  88struct tb_cap_extended_long {
  89        u8 zero1;
  90        u8 cap;
  91        u8 vsec_id;
  92        u8 zero2;
  93        u16 next;
  94        u16 length;
  95} __packed;
  96
  97/**
  98 * struct tb_cap_any - Structure capable of hold every capability
  99 * @basic: Basic capability
 100 * @extended_short: Vendor specific capability
 101 * @extended_long: Vendor specific extended capability
 102 */
 103struct tb_cap_any {
 104        union {
 105                struct tb_cap_basic basic;
 106                struct tb_cap_extended_short extended_short;
 107                struct tb_cap_extended_long extended_long;
 108        };
 109} __packed;
 110
 111/* capabilities */
 112
 113struct tb_cap_link_controller {
 114        struct tb_cap_extended_long cap_header;
 115        u32 count:4; /* number of link controllers */
 116        u32 unknown1:4;
 117        u32 base_offset:8; /*
 118                            * offset (into this capability) of the configuration
 119                            * area of the first link controller
 120                            */
 121        u32 length:12; /* link controller configuration area length */
 122        u32 unknown2:4; /* TODO check that length is correct */
 123} __packed;
 124
 125struct tb_cap_phy {
 126        struct tb_cap_basic cap_header;
 127        u32 unknown1:16;
 128        u32 unknown2:14;
 129        bool disable:1;
 130        u32 unknown3:11;
 131        enum tb_port_state state:4;
 132        u32 unknown4:2;
 133} __packed;
 134
 135struct tb_eeprom_ctl {
 136        bool clock:1; /* send pulse to transfer one bit */
 137        bool access_low:1; /* set to 0 before access */
 138        bool data_out:1; /* to eeprom */
 139        bool data_in:1; /* from eeprom */
 140        bool access_high:1; /* set to 1 before access */
 141        bool not_present:1; /* should be 0 */
 142        bool unknown1:1;
 143        bool present:1; /* should be 1 */
 144        u32 unknown2:24;
 145} __packed;
 146
 147struct tb_cap_plug_events {
 148        struct tb_cap_extended_short cap_header;
 149        u32 __unknown1:2;
 150        u32 plug_events:5;
 151        u32 __unknown2:25;
 152        u32 __unknown3;
 153        u32 __unknown4;
 154        struct tb_eeprom_ctl eeprom_ctl;
 155        u32 __unknown5[7];
 156        u32 drom_offset; /* 32 bit register, but eeprom addresses are 16 bit */
 157} __packed;
 158
 159/* device headers */
 160
 161/* Present on port 0 in TB_CFG_SWITCH at address zero. */
 162struct tb_regs_switch_header {
 163        /* DWORD 0 */
 164        u16 vendor_id;
 165        u16 device_id;
 166        /* DWORD 1 */
 167        u32 first_cap_offset:8;
 168        u32 upstream_port_number:6;
 169        u32 max_port_number:6;
 170        u32 depth:3;
 171        u32 __unknown1:1;
 172        u32 revision:8;
 173        /* DWORD 2 */
 174        u32 route_lo;
 175        /* DWORD 3 */
 176        u32 route_hi:31;
 177        bool enabled:1;
 178        /* DWORD 4 */
 179        u32 plug_events_delay:8; /*
 180                                  * RW, pause between plug events in
 181                                  * milliseconds. Writing 0x00 is interpreted
 182                                  * as 255ms.
 183                                  */
 184        u32 cmuv:8;
 185        u32 __unknown4:8;
 186        u32 thunderbolt_version:8;
 187} __packed;
 188
 189/* USB4 version 1.0 */
 190#define USB4_VERSION_1_0                        0x20
 191
 192#define ROUTER_CS_1                             0x01
 193#define ROUTER_CS_4                             0x04
 194#define ROUTER_CS_5                             0x05
 195#define ROUTER_CS_5_SLP                         BIT(0)
 196#define ROUTER_CS_5_WOP                         BIT(1)
 197#define ROUTER_CS_5_WOU                         BIT(2)
 198#define ROUTER_CS_5_WOD                         BIT(3)
 199#define ROUTER_CS_5_C3S                         BIT(23)
 200#define ROUTER_CS_5_PTO                         BIT(24)
 201#define ROUTER_CS_5_UTO                         BIT(25)
 202#define ROUTER_CS_5_HCO                         BIT(26)
 203#define ROUTER_CS_5_CV                          BIT(31)
 204#define ROUTER_CS_6                             0x06
 205#define ROUTER_CS_6_SLPR                        BIT(0)
 206#define ROUTER_CS_6_TNS                         BIT(1)
 207#define ROUTER_CS_6_WOPS                        BIT(2)
 208#define ROUTER_CS_6_WOUS                        BIT(3)
 209#define ROUTER_CS_6_HCI                         BIT(18)
 210#define ROUTER_CS_6_CR                          BIT(25)
 211#define ROUTER_CS_7                             0x07
 212#define ROUTER_CS_9                             0x09
 213#define ROUTER_CS_25                            0x19
 214#define ROUTER_CS_26                            0x1a
 215#define ROUTER_CS_26_OPCODE_MASK                GENMASK(15, 0)
 216#define ROUTER_CS_26_STATUS_MASK                GENMASK(29, 24)
 217#define ROUTER_CS_26_STATUS_SHIFT               24
 218#define ROUTER_CS_26_ONS                        BIT(30)
 219#define ROUTER_CS_26_OV                         BIT(31)
 220
 221/* USB4 router operations opcodes */
 222enum usb4_switch_op {
 223        USB4_SWITCH_OP_QUERY_DP_RESOURCE = 0x10,
 224        USB4_SWITCH_OP_ALLOC_DP_RESOURCE = 0x11,
 225        USB4_SWITCH_OP_DEALLOC_DP_RESOURCE = 0x12,
 226        USB4_SWITCH_OP_NVM_WRITE = 0x20,
 227        USB4_SWITCH_OP_NVM_AUTH = 0x21,
 228        USB4_SWITCH_OP_NVM_READ = 0x22,
 229        USB4_SWITCH_OP_NVM_SET_OFFSET = 0x23,
 230        USB4_SWITCH_OP_DROM_READ = 0x24,
 231        USB4_SWITCH_OP_NVM_SECTOR_SIZE = 0x25,
 232        USB4_SWITCH_OP_BUFFER_ALLOC = 0x33,
 233};
 234
 235/* Router TMU configuration */
 236#define TMU_RTR_CS_0                            0x00
 237#define TMU_RTR_CS_0_TD                         BIT(27)
 238#define TMU_RTR_CS_0_UCAP                       BIT(30)
 239#define TMU_RTR_CS_1                            0x01
 240#define TMU_RTR_CS_1_LOCAL_TIME_NS_MASK         GENMASK(31, 16)
 241#define TMU_RTR_CS_1_LOCAL_TIME_NS_SHIFT        16
 242#define TMU_RTR_CS_2                            0x02
 243#define TMU_RTR_CS_3                            0x03
 244#define TMU_RTR_CS_3_LOCAL_TIME_NS_MASK         GENMASK(15, 0)
 245#define TMU_RTR_CS_3_TS_PACKET_INTERVAL_MASK    GENMASK(31, 16)
 246#define TMU_RTR_CS_3_TS_PACKET_INTERVAL_SHIFT   16
 247#define TMU_RTR_CS_22                           0x16
 248#define TMU_RTR_CS_24                           0x18
 249
 250enum tb_port_type {
 251        TB_TYPE_INACTIVE        = 0x000000,
 252        TB_TYPE_PORT            = 0x000001,
 253        TB_TYPE_NHI             = 0x000002,
 254        /* TB_TYPE_ETHERNET     = 0x020000, lower order bits are not known */
 255        /* TB_TYPE_SATA         = 0x080000, lower order bits are not known */
 256        TB_TYPE_DP_HDMI_IN      = 0x0e0101,
 257        TB_TYPE_DP_HDMI_OUT     = 0x0e0102,
 258        TB_TYPE_PCIE_DOWN       = 0x100101,
 259        TB_TYPE_PCIE_UP         = 0x100102,
 260        TB_TYPE_USB3_DOWN       = 0x200101,
 261        TB_TYPE_USB3_UP         = 0x200102,
 262};
 263
 264/* Present on every port in TB_CF_PORT at address zero. */
 265struct tb_regs_port_header {
 266        /* DWORD 0 */
 267        u16 vendor_id;
 268        u16 device_id;
 269        /* DWORD 1 */
 270        u32 first_cap_offset:8;
 271        u32 max_counters:11;
 272        u32 counters_support:1;
 273        u32 __unknown1:4;
 274        u32 revision:8;
 275        /* DWORD 2 */
 276        enum tb_port_type type:24;
 277        u32 thunderbolt_version:8;
 278        /* DWORD 3 */
 279        u32 __unknown2:20;
 280        u32 port_number:6;
 281        u32 __unknown3:6;
 282        /* DWORD 4 */
 283        u32 nfc_credits;
 284        /* DWORD 5 */
 285        u32 max_in_hop_id:11;
 286        u32 max_out_hop_id:11;
 287        u32 __unknown4:10;
 288        /* DWORD 6 */
 289        u32 __unknown5;
 290        /* DWORD 7 */
 291        u32 __unknown6;
 292
 293} __packed;
 294
 295/* Basic adapter configuration registers */
 296#define ADP_CS_4                                0x04
 297#define ADP_CS_4_NFC_BUFFERS_MASK               GENMASK(9, 0)
 298#define ADP_CS_4_TOTAL_BUFFERS_MASK             GENMASK(29, 20)
 299#define ADP_CS_4_TOTAL_BUFFERS_SHIFT            20
 300#define ADP_CS_4_LCK                            BIT(31)
 301#define ADP_CS_5                                0x05
 302#define ADP_CS_5_LCA_MASK                       GENMASK(28, 22)
 303#define ADP_CS_5_LCA_SHIFT                      22
 304
 305/* TMU adapter registers */
 306#define TMU_ADP_CS_3                            0x03
 307#define TMU_ADP_CS_3_UDM                        BIT(29)
 308
 309/* Lane adapter registers */
 310#define LANE_ADP_CS_0                           0x00
 311#define LANE_ADP_CS_0_SUPPORTED_WIDTH_MASK      GENMASK(25, 20)
 312#define LANE_ADP_CS_0_SUPPORTED_WIDTH_SHIFT     20
 313#define LANE_ADP_CS_1                           0x01
 314#define LANE_ADP_CS_1_TARGET_WIDTH_MASK         GENMASK(9, 4)
 315#define LANE_ADP_CS_1_TARGET_WIDTH_SHIFT        4
 316#define LANE_ADP_CS_1_TARGET_WIDTH_SINGLE       0x1
 317#define LANE_ADP_CS_1_TARGET_WIDTH_DUAL         0x3
 318#define LANE_ADP_CS_1_LD                        BIT(14)
 319#define LANE_ADP_CS_1_LB                        BIT(15)
 320#define LANE_ADP_CS_1_CURRENT_SPEED_MASK        GENMASK(19, 16)
 321#define LANE_ADP_CS_1_CURRENT_SPEED_SHIFT       16
 322#define LANE_ADP_CS_1_CURRENT_SPEED_GEN2        0x8
 323#define LANE_ADP_CS_1_CURRENT_SPEED_GEN3        0x4
 324#define LANE_ADP_CS_1_CURRENT_WIDTH_MASK        GENMASK(25, 20)
 325#define LANE_ADP_CS_1_CURRENT_WIDTH_SHIFT       20
 326
 327/* USB4 port registers */
 328#define PORT_CS_1                               0x01
 329#define PORT_CS_1_LENGTH_SHIFT                  8
 330#define PORT_CS_1_TARGET_MASK                   GENMASK(18, 16)
 331#define PORT_CS_1_TARGET_SHIFT                  16
 332#define PORT_CS_1_RETIMER_INDEX_SHIFT           20
 333#define PORT_CS_1_WNR_WRITE                     BIT(24)
 334#define PORT_CS_1_NR                            BIT(25)
 335#define PORT_CS_1_RC                            BIT(26)
 336#define PORT_CS_1_PND                           BIT(31)
 337#define PORT_CS_2                               0x02
 338#define PORT_CS_18                              0x12
 339#define PORT_CS_18_BE                           BIT(8)
 340#define PORT_CS_18_TCM                          BIT(9)
 341#define PORT_CS_18_WOU4S                        BIT(18)
 342#define PORT_CS_19                              0x13
 343#define PORT_CS_19_PC                           BIT(3)
 344#define PORT_CS_19_PID                          BIT(4)
 345#define PORT_CS_19_WOC                          BIT(16)
 346#define PORT_CS_19_WOD                          BIT(17)
 347#define PORT_CS_19_WOU4                         BIT(18)
 348
 349/* Display Port adapter registers */
 350#define ADP_DP_CS_0                             0x00
 351#define ADP_DP_CS_0_VIDEO_HOPID_MASK            GENMASK(26, 16)
 352#define ADP_DP_CS_0_VIDEO_HOPID_SHIFT           16
 353#define ADP_DP_CS_0_AE                          BIT(30)
 354#define ADP_DP_CS_0_VE                          BIT(31)
 355#define ADP_DP_CS_1_AUX_TX_HOPID_MASK           GENMASK(10, 0)
 356#define ADP_DP_CS_1_AUX_RX_HOPID_MASK           GENMASK(21, 11)
 357#define ADP_DP_CS_1_AUX_RX_HOPID_SHIFT          11
 358#define ADP_DP_CS_2                             0x02
 359#define ADP_DP_CS_2_HDP                         BIT(6)
 360#define ADP_DP_CS_3                             0x03
 361#define ADP_DP_CS_3_HDPC                        BIT(9)
 362#define DP_LOCAL_CAP                            0x04
 363#define DP_REMOTE_CAP                           0x05
 364#define DP_STATUS_CTRL                          0x06
 365#define DP_STATUS_CTRL_CMHS                     BIT(25)
 366#define DP_STATUS_CTRL_UF                       BIT(26)
 367#define DP_COMMON_CAP                           0x07
 368/*
 369 * DP_COMMON_CAP offsets work also for DP_LOCAL_CAP and DP_REMOTE_CAP
 370 * with exception of DPRX done.
 371 */
 372#define DP_COMMON_CAP_RATE_MASK                 GENMASK(11, 8)
 373#define DP_COMMON_CAP_RATE_SHIFT                8
 374#define DP_COMMON_CAP_RATE_RBR                  0x0
 375#define DP_COMMON_CAP_RATE_HBR                  0x1
 376#define DP_COMMON_CAP_RATE_HBR2                 0x2
 377#define DP_COMMON_CAP_RATE_HBR3                 0x3
 378#define DP_COMMON_CAP_LANES_MASK                GENMASK(14, 12)
 379#define DP_COMMON_CAP_LANES_SHIFT               12
 380#define DP_COMMON_CAP_1_LANE                    0x0
 381#define DP_COMMON_CAP_2_LANES                   0x1
 382#define DP_COMMON_CAP_4_LANES                   0x2
 383#define DP_COMMON_CAP_DPRX_DONE                 BIT(31)
 384
 385/* PCIe adapter registers */
 386#define ADP_PCIE_CS_0                           0x00
 387#define ADP_PCIE_CS_0_PE                        BIT(31)
 388
 389/* USB adapter registers */
 390#define ADP_USB3_CS_0                           0x00
 391#define ADP_USB3_CS_0_V                         BIT(30)
 392#define ADP_USB3_CS_0_PE                        BIT(31)
 393#define ADP_USB3_CS_1                           0x01
 394#define ADP_USB3_CS_1_CUBW_MASK                 GENMASK(11, 0)
 395#define ADP_USB3_CS_1_CDBW_MASK                 GENMASK(23, 12)
 396#define ADP_USB3_CS_1_CDBW_SHIFT                12
 397#define ADP_USB3_CS_1_HCA                       BIT(31)
 398#define ADP_USB3_CS_2                           0x02
 399#define ADP_USB3_CS_2_AUBW_MASK                 GENMASK(11, 0)
 400#define ADP_USB3_CS_2_ADBW_MASK                 GENMASK(23, 12)
 401#define ADP_USB3_CS_2_ADBW_SHIFT                12
 402#define ADP_USB3_CS_2_CMR                       BIT(31)
 403#define ADP_USB3_CS_3                           0x03
 404#define ADP_USB3_CS_3_SCALE_MASK                GENMASK(5, 0)
 405#define ADP_USB3_CS_4                           0x04
 406#define ADP_USB3_CS_4_ALR_MASK                  GENMASK(6, 0)
 407#define ADP_USB3_CS_4_ALR_20G                   0x1
 408#define ADP_USB3_CS_4_ULV                       BIT(7)
 409#define ADP_USB3_CS_4_MSLR_MASK                 GENMASK(18, 12)
 410#define ADP_USB3_CS_4_MSLR_SHIFT                12
 411#define ADP_USB3_CS_4_MSLR_20G                  0x1
 412
 413/* Hop register from TB_CFG_HOPS. 8 byte per entry. */
 414struct tb_regs_hop {
 415        /* DWORD 0 */
 416        u32 next_hop:11; /*
 417                          * hop to take after sending the packet through
 418                          * out_port (on the incoming port of the next switch)
 419                          */
 420        u32 out_port:6; /* next port of the path (on the same switch) */
 421        u32 initial_credits:8;
 422        u32 unknown1:6; /* set to zero */
 423        bool enable:1;
 424
 425        /* DWORD 1 */
 426        u32 weight:4;
 427        u32 unknown2:4; /* set to zero */
 428        u32 priority:3;
 429        bool drop_packages:1;
 430        u32 counter:11; /* index into TB_CFG_COUNTERS on this port */
 431        bool counter_enable:1;
 432        bool ingress_fc:1;
 433        bool egress_fc:1;
 434        bool ingress_shared_buffer:1;
 435        bool egress_shared_buffer:1;
 436        bool pending:1;
 437        u32 unknown3:3; /* set to zero */
 438} __packed;
 439
 440/* Common link controller registers */
 441#define TB_LC_DESC                      0x02
 442#define TB_LC_DESC_NLC_MASK             GENMASK(3, 0)
 443#define TB_LC_DESC_SIZE_SHIFT           8
 444#define TB_LC_DESC_SIZE_MASK            GENMASK(15, 8)
 445#define TB_LC_DESC_PORT_SIZE_SHIFT      16
 446#define TB_LC_DESC_PORT_SIZE_MASK       GENMASK(27, 16)
 447#define TB_LC_FUSE                      0x03
 448#define TB_LC_SNK_ALLOCATION            0x10
 449#define TB_LC_SNK_ALLOCATION_SNK0_MASK  GENMASK(3, 0)
 450#define TB_LC_SNK_ALLOCATION_SNK0_CM    0x1
 451#define TB_LC_SNK_ALLOCATION_SNK1_SHIFT 4
 452#define TB_LC_SNK_ALLOCATION_SNK1_MASK  GENMASK(7, 4)
 453#define TB_LC_SNK_ALLOCATION_SNK1_CM    0x1
 454#define TB_LC_POWER                     0x740
 455
 456/* Link controller registers */
 457#define TB_LC_PORT_ATTR                 0x8d
 458#define TB_LC_PORT_ATTR_BE              BIT(12)
 459
 460#define TB_LC_SX_CTRL                   0x96
 461#define TB_LC_SX_CTRL_WOC               BIT(1)
 462#define TB_LC_SX_CTRL_WOD               BIT(2)
 463#define TB_LC_SX_CTRL_WODPC             BIT(3)
 464#define TB_LC_SX_CTRL_WODPD             BIT(4)
 465#define TB_LC_SX_CTRL_WOU4              BIT(5)
 466#define TB_LC_SX_CTRL_WOP               BIT(6)
 467#define TB_LC_SX_CTRL_L1C               BIT(16)
 468#define TB_LC_SX_CTRL_L1D               BIT(17)
 469#define TB_LC_SX_CTRL_L2C               BIT(20)
 470#define TB_LC_SX_CTRL_L2D               BIT(21)
 471#define TB_LC_SX_CTRL_SLI               BIT(29)
 472#define TB_LC_SX_CTRL_UPSTREAM          BIT(30)
 473#define TB_LC_SX_CTRL_SLP               BIT(31)
 474
 475#endif
 476