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7#ifndef _QED_H
8#define _QED_H
9
10#include <linux/types.h>
11#include <linux/io.h>
12#include <linux/delay.h>
13#include <linux/firmware.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/mutex.h>
17#include <linux/pci.h>
18#include <linux/slab.h>
19#include <linux/string.h>
20#include <linux/workqueue.h>
21#include <linux/zlib.h>
22#include <linux/hashtable.h>
23#include <linux/qed/qed_if.h>
24#include "qed_debug.h"
25#include "qed_hsi.h"
26
27extern const struct qed_common_ops qed_common_ops_pass;
28
29#define QED_MAJOR_VERSION 8
30#define QED_MINOR_VERSION 37
31#define QED_REVISION_VERSION 0
32#define QED_ENGINEERING_VERSION 20
33
34#define QED_VERSION \
35 ((QED_MAJOR_VERSION << 24) | (QED_MINOR_VERSION << 16) | \
36 (QED_REVISION_VERSION << 8) | QED_ENGINEERING_VERSION)
37
38#define STORM_FW_VERSION \
39 ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \
40 (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
41
42#define MAX_HWFNS_PER_DEVICE (4)
43#define NAME_SIZE 16
44#define VER_SIZE 16
45
46#define QED_WFQ_UNIT 100
47
48#define QED_WID_SIZE (1024)
49#define QED_MIN_WIDS (4)
50#define QED_PF_DEMS_SIZE (4)
51
52#define QED_LLH_DONT_CARE 0
53
54
55enum qed_coalescing_mode {
56 QED_COAL_MODE_DISABLE,
57 QED_COAL_MODE_ENABLE
58};
59
60enum qed_nvm_cmd {
61 QED_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
62 QED_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
63 QED_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
64 QED_GET_MCP_NVM_RESP = 0xFFFFFF00
65};
66
67struct qed_eth_cb_ops;
68struct qed_dev_info;
69union qed_mcp_protocol_stats;
70enum qed_mcp_protocol_type;
71enum qed_mfw_tlv_type;
72union qed_mfw_tlv_data;
73
74
75#define QED_MFW_GET_FIELD(name, field) \
76 (((name) & (field ## _MASK)) >> (field ## _SHIFT))
77
78#define QED_MFW_SET_FIELD(name, field, value) \
79 do { \
80 (name) &= ~(field ## _MASK); \
81 (name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK));\
82 } while (0)
83
84static inline u32 qed_db_addr(u32 cid, u32 DEMS)
85{
86 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
87 (cid * QED_PF_DEMS_SIZE);
88
89 return db_addr;
90}
91
92static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS)
93{
94 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
95 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
96
97 return db_addr;
98}
99
100#define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
101 ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
102 ~((1 << (p_hwfn->cdev->cache_shift)) - 1))
103
104#define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++)
105
106#define D_TRINE(val, cond1, cond2, true1, true2, def) \
107 (val == (cond1) ? true1 : \
108 (val == (cond2) ? true2 : def))
109
110
111struct qed_ptt_pool;
112struct qed_spq;
113struct qed_sb_info;
114struct qed_sb_attn_info;
115struct qed_cxt_mngr;
116struct qed_sb_sp_info;
117struct qed_ll2_info;
118struct qed_mcp_info;
119struct qed_llh_info;
120
121struct qed_rt_data {
122 u32 *init_val;
123 bool *b_valid;
124};
125
126enum qed_tunn_mode {
127 QED_MODE_L2GENEVE_TUNN,
128 QED_MODE_IPGENEVE_TUNN,
129 QED_MODE_L2GRE_TUNN,
130 QED_MODE_IPGRE_TUNN,
131 QED_MODE_VXLAN_TUNN,
132};
133
134enum qed_tunn_clss {
135 QED_TUNN_CLSS_MAC_VLAN,
136 QED_TUNN_CLSS_MAC_VNI,
137 QED_TUNN_CLSS_INNER_MAC_VLAN,
138 QED_TUNN_CLSS_INNER_MAC_VNI,
139 QED_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
140 MAX_QED_TUNN_CLSS,
141};
142
143struct qed_tunn_update_type {
144 bool b_update_mode;
145 bool b_mode_enabled;
146 enum qed_tunn_clss tun_cls;
147};
148
149struct qed_tunn_update_udp_port {
150 bool b_update_port;
151 u16 port;
152};
153
154struct qed_tunnel_info {
155 struct qed_tunn_update_type vxlan;
156 struct qed_tunn_update_type l2_geneve;
157 struct qed_tunn_update_type ip_geneve;
158 struct qed_tunn_update_type l2_gre;
159 struct qed_tunn_update_type ip_gre;
160
161 struct qed_tunn_update_udp_port vxlan_port;
162 struct qed_tunn_update_udp_port geneve_port;
163
164 bool b_update_rx_cls;
165 bool b_update_tx_cls;
166};
167
168struct qed_tunn_start_params {
169 unsigned long tunn_mode;
170 u16 vxlan_udp_port;
171 u16 geneve_udp_port;
172 u8 update_vxlan_udp_port;
173 u8 update_geneve_udp_port;
174 u8 tunn_clss_vxlan;
175 u8 tunn_clss_l2geneve;
176 u8 tunn_clss_ipgeneve;
177 u8 tunn_clss_l2gre;
178 u8 tunn_clss_ipgre;
179};
180
181struct qed_tunn_update_params {
182 unsigned long tunn_mode_update_mask;
183 unsigned long tunn_mode;
184 u16 vxlan_udp_port;
185 u16 geneve_udp_port;
186 u8 update_rx_pf_clss;
187 u8 update_tx_pf_clss;
188 u8 update_vxlan_udp_port;
189 u8 update_geneve_udp_port;
190 u8 tunn_clss_vxlan;
191 u8 tunn_clss_l2geneve;
192 u8 tunn_clss_ipgeneve;
193 u8 tunn_clss_l2gre;
194 u8 tunn_clss_ipgre;
195};
196
197
198
199
200
201enum qed_pci_personality {
202 QED_PCI_ETH,
203 QED_PCI_FCOE,
204 QED_PCI_ISCSI,
205 QED_PCI_NVMETCP,
206 QED_PCI_ETH_ROCE,
207 QED_PCI_ETH_IWARP,
208 QED_PCI_ETH_RDMA,
209 QED_PCI_DEFAULT,
210};
211
212
213struct qed_qm_iids {
214 u32 cids;
215 u32 vf_cids;
216 u32 tids;
217};
218
219
220
221
222enum qed_resources {
223 QED_SB,
224 QED_L2_QUEUE,
225 QED_VPORT,
226 QED_RSS_ENG,
227 QED_PQ,
228 QED_RL,
229 QED_MAC,
230 QED_VLAN,
231 QED_RDMA_CNQ_RAM,
232 QED_ILT,
233 QED_LL2_RAM_QUEUE,
234 QED_LL2_CTX_QUEUE,
235 QED_CMDQS_CQS,
236 QED_RDMA_STATS_QUEUE,
237 QED_BDQ,
238 QED_MAX_RESC,
239};
240
241enum QED_FEATURE {
242 QED_PF_L2_QUE,
243 QED_VF,
244 QED_RDMA_CNQ,
245 QED_NVMETCP_CQ,
246 QED_ISCSI_CQ,
247 QED_FCOE_CQ,
248 QED_VF_L2_QUE,
249 QED_MAX_FEATURES,
250};
251
252enum qed_dev_cap {
253 QED_DEV_CAP_ETH,
254 QED_DEV_CAP_FCOE,
255 QED_DEV_CAP_ISCSI,
256 QED_DEV_CAP_ROCE,
257 QED_DEV_CAP_IWARP,
258};
259
260enum qed_wol_support {
261 QED_WOL_SUPPORT_NONE,
262 QED_WOL_SUPPORT_PME,
263};
264
265enum qed_db_rec_exec {
266 DB_REC_DRY_RUN,
267 DB_REC_REAL_DEAL,
268 DB_REC_ONCE,
269};
270
271struct qed_hw_info {
272
273 enum qed_pci_personality personality;
274#define QED_IS_RDMA_PERSONALITY(dev) \
275 ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \
276 (dev)->hw_info.personality == QED_PCI_ETH_IWARP || \
277 (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
278#define QED_IS_ROCE_PERSONALITY(dev) \
279 ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \
280 (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
281#define QED_IS_IWARP_PERSONALITY(dev) \
282 ((dev)->hw_info.personality == QED_PCI_ETH_IWARP || \
283 (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
284#define QED_IS_L2_PERSONALITY(dev) \
285 ((dev)->hw_info.personality == QED_PCI_ETH || \
286 QED_IS_RDMA_PERSONALITY(dev))
287#define QED_IS_FCOE_PERSONALITY(dev) \
288 ((dev)->hw_info.personality == QED_PCI_FCOE)
289#define QED_IS_ISCSI_PERSONALITY(dev) \
290 ((dev)->hw_info.personality == QED_PCI_ISCSI)
291#define QED_IS_NVMETCP_PERSONALITY(dev) \
292 ((dev)->hw_info.personality == QED_PCI_NVMETCP)
293
294
295 u32 resc_start[QED_MAX_RESC];
296 u32 resc_num[QED_MAX_RESC];
297#define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
298#define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
299#define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
300 RESC_NUM(_p_hwfn, resc))
301
302 u32 feat_num[QED_MAX_FEATURES];
303#define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
304
305
306 u8 num_hw_tc;
307
308
309
310
311 u8 num_active_tc;
312
313 u8 offload_tc;
314 bool offload_tc_set;
315
316 bool multi_tc_roce_en;
317#define IS_QED_MULTI_TC_ROCE(p_hwfn) ((p_hwfn)->hw_info.multi_tc_roce_en)
318
319 u32 concrete_fid;
320 u16 opaque_fid;
321 u16 ovlan;
322 u32 part_num[4];
323
324 unsigned char hw_mac_addr[ETH_ALEN];
325 u64 node_wwn;
326 u64 port_wwn;
327
328 u16 num_fcoe_conns;
329
330 struct qed_igu_info *p_igu_info;
331
332 u32 hw_mode;
333 unsigned long device_capabilities;
334 u16 mtu;
335
336 enum qed_wol_support b_wol_support;
337};
338
339
340#define DMAE_MAX_RW_SIZE 0x2000
341
342struct qed_dmae_info {
343
344 struct mutex mutex;
345
346 u8 channel;
347
348 dma_addr_t completion_word_phys_addr;
349
350
351
352
353 u32 *p_completion_word;
354
355 dma_addr_t intermediate_buffer_phys_addr;
356
357
358
359
360
361 u32 *p_intermediate_buffer;
362
363 dma_addr_t dmae_cmd_phys_addr;
364 struct dmae_cmd *p_dmae_cmd;
365};
366
367struct qed_wfq_data {
368
369 u32 min_speed;
370 bool configured;
371};
372
373struct qed_qm_info {
374 struct init_qm_pq_params *qm_pq_params;
375 struct init_qm_vport_params *qm_vport_params;
376 struct init_qm_port_params *qm_port_params;
377 u16 start_pq;
378 u8 start_vport;
379 u16 pure_lb_pq;
380 u16 first_ofld_pq;
381 u16 first_llt_pq;
382 u16 pure_ack_pq;
383 u16 ooo_pq;
384 u16 first_vf_pq;
385 u16 first_mcos_pq;
386 u16 first_rl_pq;
387 u16 num_pqs;
388 u16 num_vf_pqs;
389 u8 num_vports;
390 u8 max_phys_tcs_per_port;
391 u8 ooo_tc;
392 bool pf_rl_en;
393 bool pf_wfq_en;
394 bool vport_rl_en;
395 bool vport_wfq_en;
396 u8 pf_wfq;
397 u32 pf_rl;
398 struct qed_wfq_data *wfq_data;
399 u8 num_pf_rls;
400};
401
402#define QED_OVERFLOW_BIT 1
403
404struct qed_db_recovery_info {
405 struct list_head list;
406
407
408 spinlock_t lock;
409 bool dorq_attn;
410 u32 db_recovery_counter;
411 unsigned long overflow;
412};
413
414struct storm_stats {
415 u32 address;
416 u32 len;
417};
418
419struct qed_storm_stats {
420 struct storm_stats mstats;
421 struct storm_stats pstats;
422 struct storm_stats tstats;
423 struct storm_stats ustats;
424};
425
426struct qed_fw_data {
427 struct fw_ver_info *fw_ver_info;
428 const u8 *modes_tree_buf;
429 union init_op *init_ops;
430 const u32 *arr_data;
431 const u32 *fw_overlays;
432 u32 fw_overlays_len;
433 u32 init_ops_size;
434};
435
436enum qed_mf_mode_bit {
437
438 QED_MF_OVLAN_CLSS,
439
440
441 QED_MF_LLH_MAC_CLSS,
442
443
444 QED_MF_LLH_PROTO_CLSS,
445
446
447 QED_MF_NEED_DEF_PF,
448
449
450 QED_MF_LL2_NON_UNICAST,
451
452
453 QED_MF_INTER_PF_SWITCH,
454
455
456 QED_MF_UFP_SPECIFIC,
457
458
459 QED_MF_DISABLE_ARFS,
460
461
462 QED_MF_8021Q_TAGGING,
463
464
465 QED_MF_8021AD_TAGGING,
466
467
468 QED_MF_DSCP_TO_TC_MAP,
469
470
471 QED_MF_DONT_ADD_VLAN0_TAG,
472};
473
474enum qed_ufp_mode {
475 QED_UFP_MODE_ETS,
476 QED_UFP_MODE_VNIC_BW,
477 QED_UFP_MODE_UNKNOWN
478};
479
480enum qed_ufp_pri_type {
481 QED_UFP_PRI_OS,
482 QED_UFP_PRI_VNIC,
483 QED_UFP_PRI_UNKNOWN
484};
485
486struct qed_ufp_info {
487 enum qed_ufp_pri_type pri_type;
488 enum qed_ufp_mode mode;
489 u8 tc;
490};
491
492enum BAR_ID {
493 BAR_ID_0,
494 BAR_ID_1
495};
496
497struct qed_nvm_image_info {
498 u32 num_images;
499 struct bist_nvm_image_att *image_att;
500 bool valid;
501};
502
503enum qed_hsi_def_type {
504 QED_HSI_DEF_MAX_NUM_VFS,
505 QED_HSI_DEF_MAX_NUM_L2_QUEUES,
506 QED_HSI_DEF_MAX_NUM_PORTS,
507 QED_HSI_DEF_MAX_SB_PER_PATH,
508 QED_HSI_DEF_MAX_NUM_PFS,
509 QED_HSI_DEF_MAX_NUM_VPORTS,
510 QED_HSI_DEF_NUM_ETH_RSS_ENGINE,
511 QED_HSI_DEF_MAX_QM_TX_QUEUES,
512 QED_HSI_DEF_NUM_PXP_ILT_RECORDS,
513 QED_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS,
514 QED_HSI_DEF_MAX_QM_GLOBAL_RLS,
515 QED_HSI_DEF_MAX_PBF_CMD_LINES,
516 QED_HSI_DEF_MAX_BTB_BLOCKS,
517 QED_NUM_HSI_DEFS
518};
519
520#define DRV_MODULE_VERSION \
521 __stringify(QED_MAJOR_VERSION) "." \
522 __stringify(QED_MINOR_VERSION) "." \
523 __stringify(QED_REVISION_VERSION) "." \
524 __stringify(QED_ENGINEERING_VERSION)
525
526struct qed_simd_fp_handler {
527 void *token;
528 void (*func)(void *);
529};
530
531enum qed_slowpath_wq_flag {
532 QED_SLOWPATH_MFW_TLV_REQ,
533 QED_SLOWPATH_PERIODIC_DB_REC,
534};
535
536struct qed_hwfn {
537 struct qed_dev *cdev;
538 u8 my_id;
539#define IS_LEAD_HWFN(edev) (!((edev)->my_id))
540 u8 rel_pf_id;
541 u8 abs_pf_id;
542#define QED_PATH_ID(_p_hwfn) \
543 (QED_IS_K2((_p_hwfn)->cdev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
544 u8 port_id;
545 bool b_active;
546
547 u32 dp_module;
548 u8 dp_level;
549 char name[NAME_SIZE];
550
551 bool hw_init_done;
552
553 u8 num_funcs_on_engine;
554 u8 enabled_func_idx;
555
556
557 void __iomem *regview;
558 void __iomem *doorbells;
559 u64 db_phys_addr;
560 unsigned long db_size;
561
562
563 struct qed_ptt_pool *p_ptt_pool;
564
565
566 struct qed_hw_info hw_info;
567
568
569 struct qed_rt_data rt_data;
570
571
572 struct qed_spq *p_spq;
573
574
575 struct qed_eq *p_eq;
576
577
578 struct qed_consq *p_consq;
579
580
581 struct tasklet_struct sp_dpc;
582 bool b_sp_dpc_enabled;
583
584 struct qed_ptt *p_main_ptt;
585 struct qed_ptt *p_dpc_ptt;
586
587
588
589
590 struct qed_ptt *p_ptp_ptt;
591
592 struct qed_sb_sp_info *p_sp_sb;
593 struct qed_sb_attn_info *p_sb_attn;
594
595
596 bool using_ll2;
597 struct qed_ll2_info *p_ll2_info;
598 struct qed_ooo_info *p_ooo_info;
599 struct qed_rdma_info *p_rdma_info;
600 struct qed_iscsi_info *p_iscsi_info;
601 struct qed_nvmetcp_info *p_nvmetcp_info;
602 struct qed_fcoe_info *p_fcoe_info;
603 struct qed_pf_params pf_params;
604
605 bool b_rdma_enabled_in_prs;
606 u32 rdma_prs_search_reg;
607
608 struct qed_cxt_mngr *p_cxt_mngr;
609
610
611 bool b_int_enabled;
612 bool b_int_requested;
613
614
615 bool b_drv_link_init;
616
617 struct qed_vf_iov *vf_iov_info;
618 struct qed_pf_iov *pf_iov_info;
619 struct qed_mcp_info *mcp_info;
620
621 struct qed_dcbx_info *p_dcbx_info;
622
623 struct qed_ufp_info ufp_info;
624
625 struct qed_dmae_info dmae_info;
626
627
628 struct qed_qm_info qm_info;
629 struct qed_storm_stats storm_stats;
630
631
632 void *unzip_buf;
633
634 struct dbg_tools_data dbg_info;
635 void *dbg_user_info;
636 struct virt_mem_desc dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE];
637
638
639 u16 wid_count;
640 u32 dpi_size;
641 u32 dpi_count;
642
643
644 u32 dpi_start_offset;
645
646
647 u8 dcbx_no_edpm;
648 u8 db_bar_no_edpm;
649
650
651 struct qed_l2_info *p_l2_info;
652
653
654 struct qed_db_recovery_info db_recovery_info;
655
656
657 struct qed_nvm_image_info nvm_info;
658
659 struct phys_mem_desc *fw_overlay_mem;
660 struct qed_ptt *p_arfs_ptt;
661
662 struct qed_simd_fp_handler simd_proto_handler[64];
663
664#ifdef CONFIG_QED_SRIOV
665 struct workqueue_struct *iov_wq;
666 struct delayed_work iov_task;
667 unsigned long iov_task_flags;
668#endif
669 struct z_stream_s *stream;
670 bool slowpath_wq_active;
671 struct workqueue_struct *slowpath_wq;
672 struct delayed_work slowpath_task;
673 unsigned long slowpath_task_flags;
674 u32 periodic_db_rec_count;
675};
676
677struct pci_params {
678 int pm_cap;
679
680 unsigned long mem_start;
681 unsigned long mem_end;
682 unsigned int irq;
683 u8 pf_num;
684};
685
686struct qed_int_param {
687 u32 int_mode;
688 u8 num_vectors;
689 u8 min_msix_cnt;
690};
691
692struct qed_int_params {
693 struct qed_int_param in;
694 struct qed_int_param out;
695 struct msix_entry *msix_table;
696 bool fp_initialized;
697 u8 fp_msix_base;
698 u8 fp_msix_cnt;
699 u8 rdma_msix_base;
700 u8 rdma_msix_cnt;
701};
702
703struct qed_dbg_feature {
704 struct dentry *dentry;
705 u8 *dump_buf;
706 u32 buf_size;
707 u32 dumped_dwords;
708};
709
710struct qed_dev {
711 u32 dp_module;
712 u8 dp_level;
713 char name[NAME_SIZE];
714
715 enum qed_dev_type type;
716
717#define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB)
718#define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && CHIP_REV_IS_B0(dev))
719#define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH)
720#define QED_IS_K2(dev) QED_IS_AH(dev)
721#define QED_IS_E4(dev) (QED_IS_BB(dev) || QED_IS_AH(dev))
722#define QED_IS_E5(dev) ((dev)->type == QED_DEV_TYPE_E5)
723
724 u16 vendor_id;
725
726 u16 device_id;
727#define QED_DEV_ID_MASK 0xff00
728#define QED_DEV_ID_MASK_BB 0x1600
729#define QED_DEV_ID_MASK_AH 0x8000
730
731 u16 chip_num;
732#define CHIP_NUM_MASK 0xffff
733#define CHIP_NUM_SHIFT 16
734
735 u16 chip_rev;
736#define CHIP_REV_MASK 0xf
737#define CHIP_REV_SHIFT 12
738#define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1)
739
740 u16 chip_metal;
741#define CHIP_METAL_MASK 0xff
742#define CHIP_METAL_SHIFT 4
743
744 u16 chip_bond_id;
745#define CHIP_BOND_ID_MASK 0xf
746#define CHIP_BOND_ID_SHIFT 0
747
748 u8 num_engines;
749 u8 num_ports;
750 u8 num_ports_in_engine;
751 u8 num_funcs_in_port;
752
753 u8 path_id;
754
755 unsigned long mf_bits;
756
757 int pcie_width;
758 int pcie_speed;
759
760
761 u8 mcp_rev;
762 u8 boot_mode;
763
764
765 u8 wol_config;
766 u8 wol_mac[ETH_ALEN];
767
768 u32 int_mode;
769 enum qed_coalescing_mode int_coalescing_mode;
770 u16 rx_coalesce_usecs;
771 u16 tx_coalesce_usecs;
772
773
774 void __iomem *regview;
775 void __iomem *doorbells;
776 u64 db_phys_addr;
777 unsigned long db_size;
778
779
780 u8 cache_shift;
781
782
783 const u32 *iro_arr;
784#define IRO ((const struct iro *)p_hwfn->cdev->iro_arr)
785
786
787 u8 num_hwfns;
788 struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
789
790
791 u8 l2_affin_hint;
792 u8 fir_affin;
793 u8 iwarp_affin;
794
795
796 struct qed_hw_sriov_info *p_iov_info;
797#define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info)
798 struct qed_tunnel_info tunnel;
799 bool b_is_vf;
800 u32 drv_type;
801 struct qed_eth_stats *reset_stats;
802 struct qed_fw_data *fw_data;
803
804 u32 mcp_nvm_resp;
805
806
807 bool recov_in_prog;
808
809
810 bool attn_clr_en;
811
812
813 u8 ppfid_bitmap;
814 struct qed_llh_info *p_llh_info;
815
816
817 struct qed_dev_info common_dev_info;
818 struct qede_dev *edev;
819 struct pci_dev *pdev;
820 u32 flags;
821#define QED_FLAG_STORAGE_STARTED (BIT(0))
822 int msg_enable;
823
824 struct pci_params pci_params;
825
826 struct qed_int_params int_params;
827
828 u8 protocol;
829#define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH)
830#define IS_QED_FCOE_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_FCOE)
831
832
833 union {
834 struct qed_common_cb_ops *common;
835 struct qed_eth_cb_ops *eth;
836 struct qed_fcoe_cb_ops *fcoe;
837 struct qed_iscsi_cb_ops *iscsi;
838 struct qed_nvmetcp_cb_ops *nvmetcp;
839 } protocol_ops;
840 void *ops_cookie;
841
842#ifdef CONFIG_QED_LL2
843 struct qed_cb_ll2_info *ll2;
844 u8 ll2_mac_address[ETH_ALEN];
845#endif
846 struct qed_dbg_feature dbg_features[DBG_FEATURE_NUM];
847 u8 engine_for_debug;
848 bool disable_ilt_dump;
849 bool dbg_bin_dump;
850
851 DECLARE_HASHTABLE(connections, 10);
852 const struct firmware *firmware;
853
854 bool print_dbg_data;
855
856 u32 rdma_max_sge;
857 u32 rdma_max_inline;
858 u32 rdma_max_srq_sge;
859 u16 tunn_feature_mask;
860
861 bool iwarp_cmt;
862};
863
864u32 qed_get_hsi_def_val(struct qed_dev *cdev, enum qed_hsi_def_type type);
865
866#define NUM_OF_VFS(dev) \
867 qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_VFS)
868#define NUM_OF_L2_QUEUES(dev) \
869 qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_L2_QUEUES)
870#define NUM_OF_PORTS(dev) \
871 qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_PORTS)
872#define NUM_OF_SBS(dev) \
873 qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_SB_PER_PATH)
874#define NUM_OF_ENG_PFS(dev) \
875 qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_PFS)
876#define NUM_OF_VPORTS(dev) \
877 qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_VPORTS)
878#define NUM_OF_RSS_ENGINES(dev) \
879 qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_ETH_RSS_ENGINE)
880#define NUM_OF_QM_TX_QUEUES(dev) \
881 qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_QM_TX_QUEUES)
882#define NUM_OF_PXP_ILT_RECORDS(dev) \
883 qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_PXP_ILT_RECORDS)
884#define NUM_OF_RDMA_STATISTIC_COUNTERS(dev) \
885 qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS)
886#define NUM_OF_QM_GLOBAL_RLS(dev) \
887 qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_QM_GLOBAL_RLS)
888#define NUM_OF_PBF_CMD_LINES(dev) \
889 qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_PBF_CMD_LINES)
890#define NUM_OF_BTB_BLOCKS(dev) \
891 qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_BTB_BLOCKS)
892
893
894
895
896
897
898
899
900
901
902static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
903 u32 concrete_fid)
904{
905 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
906 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
907 u8 vf_valid = GET_FIELD(concrete_fid,
908 PXP_CONCRETE_FID_VFVALID);
909 u8 sw_fid;
910
911 if (vf_valid)
912 sw_fid = vfid + MAX_NUM_PFS;
913 else
914 sw_fid = pfid;
915
916 return sw_fid;
917}
918
919#define PKT_LB_TC 9
920#define MAX_NUM_VOQS_E4 20
921
922int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate);
923void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
924 struct qed_ptt *p_ptt,
925 u32 min_pf_rate);
926
927void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
928int qed_device_num_engines(struct qed_dev *cdev);
929void qed_set_fw_mac_addr(__le16 *fw_msb,
930 __le16 *fw_mid, __le16 *fw_lsb, u8 *mac);
931
932#define QED_LEADING_HWFN(dev) (&dev->hwfns[0])
933#define QED_IS_CMT(dev) ((dev)->num_hwfns > 1)
934
935#define QED_FIR_AFFIN_HWFN(dev) (&(dev)->hwfns[dev->fir_affin])
936#define QED_IWARP_AFFIN_HWFN(dev) (&(dev)->hwfns[dev->iwarp_affin])
937#define QED_AFFIN_HWFN(dev) \
938 (QED_IS_IWARP_PERSONALITY(QED_LEADING_HWFN(dev)) ? \
939 QED_IWARP_AFFIN_HWFN(dev) : QED_FIR_AFFIN_HWFN(dev))
940#define QED_AFFIN_HWFN_IDX(dev) (IS_LEAD_HWFN(QED_AFFIN_HWFN(dev)) ? 0 : 1)
941
942
943#define PQ_FLAGS_RLS (BIT(0))
944#define PQ_FLAGS_MCOS (BIT(1))
945#define PQ_FLAGS_LB (BIT(2))
946#define PQ_FLAGS_OOO (BIT(3))
947#define PQ_FLAGS_ACK (BIT(4))
948#define PQ_FLAGS_OFLD (BIT(5))
949#define PQ_FLAGS_VFS (BIT(6))
950#define PQ_FLAGS_LLT (BIT(7))
951#define PQ_FLAGS_MTC (BIT(8))
952
953
954u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags);
955u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc);
956u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf);
957u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc);
958u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc);
959
960
961void qed_db_recovery_dp(struct qed_hwfn *p_hwfn);
962void qed_db_recovery_execute(struct qed_hwfn *p_hwfn);
963bool qed_edpm_enabled(struct qed_hwfn *p_hwfn);
964
965
966#define DP_NAME(cdev) ((cdev)->name)
967
968#define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\
969 (cdev->regview) + \
970 (offset))
971
972#define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset))
973#define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset))
974#define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset))
975
976#define DOORBELL(cdev, db_addr, val) \
977 writel((u32)val, (void __iomem *)((u8 __iomem *)\
978 (cdev->doorbells) + (db_addr)))
979
980#define MFW_PORT(_p_hwfn) ((_p_hwfn)->abs_pf_id % \
981 qed_device_num_ports((_p_hwfn)->cdev))
982int qed_device_num_ports(struct qed_dev *cdev);
983
984
985int qed_fill_dev_info(struct qed_dev *cdev,
986 struct qed_dev_info *dev_info);
987void qed_link_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt);
988void qed_bw_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt);
989u32 qed_unzip_data(struct qed_hwfn *p_hwfn,
990 u32 input_len, u8 *input_buf,
991 u32 max_size, u8 *unzip_buf);
992int qed_recovery_process(struct qed_dev *cdev);
993void qed_schedule_recovery_handler(struct qed_hwfn *p_hwfn);
994void qed_hw_error_occurred(struct qed_hwfn *p_hwfn,
995 enum qed_hw_err_type err_type);
996void qed_get_protocol_stats(struct qed_dev *cdev,
997 enum qed_mcp_protocol_type type,
998 union qed_mcp_protocol_stats *stats);
999int qed_slowpath_irq_req(struct qed_hwfn *hwfn);
1000void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn);
1001int qed_mfw_tlv_req(struct qed_hwfn *hwfn);
1002
1003int qed_mfw_fill_tlv_data(struct qed_hwfn *hwfn,
1004 enum qed_mfw_tlv_type type,
1005 union qed_mfw_tlv_data *tlv_data);
1006
1007void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc);
1008
1009void qed_periodic_db_rec_start(struct qed_hwfn *p_hwfn);
1010
1011int qed_llh_add_src_tcp_port_filter(struct qed_dev *cdev, u16 src_port);
1012int qed_llh_add_dst_tcp_port_filter(struct qed_dev *cdev, u16 dest_port);
1013void qed_llh_remove_src_tcp_port_filter(struct qed_dev *cdev, u16 src_port);
1014void qed_llh_remove_dst_tcp_port_filter(struct qed_dev *cdev, u16 src_port);
1015void qed_llh_clear_all_filters(struct qed_dev *cdev);
1016#endif
1017
