// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * drivers/net/ethernet/ibm/emac/core.c
 *
 * Driver for PowerPC 4xx on-chip ethernet controller.
 *
 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
 *                <benh@kernel.crashing.org>
 *
 * Based on the arch/ppc version of the driver:
 *
 * Copyright (c) 2004, 2005 Zultys Technologies.
 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
 *
 * Based on original work by
 *      Matt Porter <mporter@kernel.crashing.org>
 *      (c) 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
 *      Armin Kuster <akuster@mvista.com>
 *      Johnnie Peters <jpeters@mvista.com>
 */

#include <linux/module.h>
#include <linux/sched.h>
#include <linux/string.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/crc32.h>
#include <linux/ethtool.h>
#include <linux/mii.h>
#include <linux/bitops.h>
#include <linux/workqueue.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_net.h>
#include <linux/of_mdio.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include <asm/processor.h>
#include <asm/io.h>
#include <asm/dma.h>
#include <linux/uaccess.h>
#include <asm/dcr.h>
#include <asm/dcr-regs.h>

#include "core.h"

/*
 * Lack of dma_unmap_???? calls is intentional.
 *
 * API-correct usage requires additional support state information to be
 * maintained for every RX and TX buffer descriptor (BD). Unfortunately, due to
 * EMAC design (e.g. TX buffer passed from network stack can be split into
 * several BDs, dma_map_single/dma_map_page can be used to map particular BD),
 * maintaining such information will add additional overhead.
 * Current DMA API implementation for 4xx processors only ensures cache coherency
 * and dma_unmap_???? routines are empty and are likely to stay this way.
 * I decided to omit dma_unmap_??? calls because I don't want to add additional
 * complexity just for the sake of following some abstract API, when it doesn't
 * add any real benefit to the driver. I understand that this decision maybe
 * controversial, but I really tried to make code API-correct and efficient
 * at the same time and didn't come up with code I liked :(.                --ebs
 */

#define DRV_NAME        "emac"
#define DRV_VERSION     "3.54"
#define DRV_DESC        "PPC 4xx OCP EMAC driver"

MODULE_DESCRIPTION(DRV_DESC);
MODULE_AUTHOR
    ("Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>");
MODULE_LICENSE("GPL");

/* minimum number of free TX descriptors required to wake up TX process */
#define EMAC_TX_WAKEUP_THRESH           (NUM_TX_BUFF / 4)

/* If packet size is less than this number, we allocate small skb and copy packet
 * contents into it instead of just sending original big skb up
 */
#define EMAC_RX_COPY_THRESH             CONFIG_IBM_EMAC_RX_COPY_THRESHOLD

/* Since multiple EMACs share MDIO lines in various ways, we need
 * to avoid re-using the same PHY ID in cases where the arch didn't
 * setup precise phy_map entries
 *
 * XXX This is something that needs to be reworked as we can have multiple
 * EMAC "sets" (multiple ASICs containing several EMACs) though we can
 * probably require in that case to have explicit PHY IDs in the device-tree
 */
static u32 busy_phy_map;
static DEFINE_MUTEX(emac_phy_map_lock);

/* This is the wait queue used to wait on any event related to probe, that
 * is discovery of MALs, other EMACs, ZMII/RGMIIs, etc...
 */
static DECLARE_WAIT_QUEUE_HEAD(emac_probe_wait);

/* Having stable interface names is a doomed idea. However, it would be nice
 * if we didn't have completely random interface names at boot too :-) It's
 * just a matter of making everybody's life easier. Since we are doing
 * threaded probing, it's a bit harder though. The base idea here is that
 * we make up a list of all emacs in the device-tree before we register the
 * driver. Every emac will then wait for the previous one in the list to
 * initialize before itself. We should also keep that list ordered by
 * cell_index.
 * That list is only 4 entries long, meaning that additional EMACs don't
 * get ordering guarantees unless EMAC_BOOT_LIST_SIZE is increased.
 */

#define EMAC_BOOT_LIST_SIZE     4
static struct device_node *emac_boot_list[EMAC_BOOT_LIST_SIZE];

/* How long should I wait for dependent devices ? */
#define EMAC_PROBE_DEP_TIMEOUT  (HZ * 5)

/* I don't want to litter system log with timeout errors
 * when we have brain-damaged PHY.
 */
static inline void emac_report_timeout_error(struct emac_instance *dev,
                                             const char *error)
{
        if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX |
                                  EMAC_FTR_460EX_PHY_CLK_FIX |
                                  EMAC_FTR_440EP_PHY_CLK_FIX))
                DBG(dev, "%s" NL, error);
        else if (net_ratelimit())
                printk(KERN_ERR "%pOF: %s\n", dev->ofdev->dev.of_node, error);
}

/* EMAC PHY clock workaround:
 * 440EP/440GR has more sane SDR0_MFR register implementation than 440GX,
 * which allows controlling each EMAC clock
 */
static inline void emac_rx_clk_tx(struct emac_instance *dev)
{
#ifdef CONFIG_PPC_DCR_NATIVE
        if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
                dcri_clrset(SDR0, SDR0_MFR,
                            0, SDR0_MFR_ECS >> dev->cell_index);
#endif
}

static inline void emac_rx_clk_default(struct emac_instance *dev)
{
#ifdef CONFIG_PPC_DCR_NATIVE
        if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
                dcri_clrset(SDR0, SDR0_MFR,
                            SDR0_MFR_ECS >> dev->cell_index, 0);
#endif
}

/* PHY polling intervals */
#define PHY_POLL_LINK_ON        HZ
#define PHY_POLL_LINK_OFF       (HZ / 5)

/* Graceful stop timeouts in us.
 * We should allow up to 1 frame time (full-duplex, ignoring collisions)
 */
#define STOP_TIMEOUT_10         1230
#define STOP_TIMEOUT_100        124
#define STOP_TIMEOUT_1000       13
#define STOP_TIMEOUT_1000_JUMBO 73

static unsigned char default_mcast_addr[] = {
        0x01, 0x80, 0xC2, 0x00, 0x00, 0x01
};

/* Please, keep in sync with struct ibm_emac_stats/ibm_emac_error_stats */
static const char emac_stats_keys[EMAC_ETHTOOL_STATS_COUNT][ETH_GSTRING_LEN] = {
        "rx_packets", "rx_bytes", "tx_packets", "tx_bytes", "rx_packets_csum",
        "tx_packets_csum", "tx_undo", "rx_dropped_stack", "rx_dropped_oom",
        "rx_dropped_error", "rx_dropped_resize", "rx_dropped_mtu",
        "rx_stopped", "rx_bd_errors", "rx_bd_overrun", "rx_bd_bad_packet",
        "rx_bd_runt_packet", "rx_bd_short_event", "rx_bd_alignment_error",
        "rx_bd_bad_fcs", "rx_bd_packet_too_long", "rx_bd_out_of_range",
        "rx_bd_in_range", "rx_parity", "rx_fifo_overrun", "rx_overrun",
        "rx_bad_packet", "rx_runt_packet", "rx_short_event",
        "rx_alignment_error", "rx_bad_fcs", "rx_packet_too_long",
        "rx_out_of_range", "rx_in_range", "tx_dropped", "tx_bd_errors",
        "tx_bd_bad_fcs", "tx_bd_carrier_loss", "tx_bd_excessive_deferral",
        "tx_bd_excessive_collisions", "tx_bd_late_collision",
        "tx_bd_multple_collisions", "tx_bd_single_collision",
        "tx_bd_underrun", "tx_bd_sqe", "tx_parity", "tx_underrun", "tx_sqe",
        "tx_errors"
};

static irqreturn_t emac_irq(int irq, void *dev_instance);
static void emac_clean_tx_ring(struct emac_instance *dev);
static void __emac_set_multicast_list(struct emac_instance *dev);

static inline int emac_phy_supports_gige(int phy_mode)
{
        return  phy_interface_mode_is_rgmii(phy_mode) ||
                phy_mode == PHY_INTERFACE_MODE_GMII ||
                phy_mode == PHY_INTERFACE_MODE_SGMII ||
                phy_mode == PHY_INTERFACE_MODE_TBI ||
                phy_mode == PHY_INTERFACE_MODE_RTBI;
}

static inline int emac_phy_gpcs(int phy_mode)
{
        return  phy_mode == PHY_INTERFACE_MODE_SGMII ||
                phy_mode == PHY_INTERFACE_MODE_TBI ||
                phy_mode == PHY_INTERFACE_MODE_RTBI;
}

static inline void emac_tx_enable(struct emac_instance *dev)
{
        struct emac_regs __iomem *p = dev->emacp;
        u32 r;

        DBG(dev, "tx_enable" NL);

        r = in_be32(&p->mr0);
        if (!(r & EMAC_MR0_TXE))
                out_be32(&p->mr0, r | EMAC_MR0_TXE);
}

static void emac_tx_disable(struct emac_instance *dev)
{
        struct emac_regs __iomem *p = dev->emacp;
        u32 r;

        DBG(dev, "tx_disable" NL);

        r = in_be32(&p->mr0);
        if (r & EMAC_MR0_TXE) {
                int n = dev->stop_timeout;
                out_be32(&p->mr0, r & ~EMAC_MR0_TXE);
                while (!(in_be32(&p->mr0) & EMAC_MR0_TXI) && n) {
                        udelay(1);
                        --n;
                }
                if (unlikely(!n))
                        emac_report_timeout_error(dev, "TX disable timeout");
        }
}

static void emac_rx_enable(struct emac_instance *dev)
{
        struct emac_regs __iomem *p = dev->emacp;
        u32 r;

        if (unlikely(test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags)))
                goto out;

        DBG(dev, "rx_enable" NL);

        r = in_be32(&p->mr0);
        if (!(r & EMAC_MR0_RXE)) {
                if (unlikely(!(r & EMAC_MR0_RXI))) {
                        /* Wait if previous async disable is still in progress */
                        int n = dev->stop_timeout;
                        while (!(r = in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
                                udelay(1);
                                --n;
                        }
                        if (unlikely(!n))
                                emac_report_timeout_error(dev,
                                                          "RX disable timeout");
                }
                out_be32(&p->mr0, r | EMAC_MR0_RXE);
        }
 out:
        ;
}

static void emac_rx_disable(struct emac_instance *dev)
{
        struct emac_regs __iomem *p = dev->emacp;
        u32 r;

        DBG(dev, "rx_disable" NL);

        r = in_be32(&p->mr0);
        if (r & EMAC_MR0_RXE) {
                int n = dev->stop_timeout;
                out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
                while (!(in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
                        udelay(1);
                        --n;
                }
                if (unlikely(!n))
                        emac_report_timeout_error(dev, "RX disable timeout");
        }
}

static inline void emac_netif_stop(struct emac_instance *dev)
{
        netif_tx_lock_bh(dev->ndev);
        netif_addr_lock(dev->ndev);
        dev->no_mcast = 1;
        netif_addr_unlock(dev->ndev);
        netif_tx_unlock_bh(dev->ndev);
        netif_trans_update(dev->ndev);  /* prevent tx timeout */
        mal_poll_disable(dev->mal, &dev->commac);
        netif_tx_disable(dev->ndev);
}

static inline void emac_netif_start(struct emac_instance *dev)
{
        netif_tx_lock_bh(dev->ndev);
        netif_addr_lock(dev->ndev);
        dev->no_mcast = 0;
        if (dev->mcast_pending && netif_running(dev->ndev))
                __emac_set_multicast_list(dev);
        netif_addr_unlock(dev->ndev);
        netif_tx_unlock_bh(dev->ndev);

        netif_wake_queue(dev->ndev);

        /* NOTE: unconditional netif_wake_queue is only appropriate
         * so long as all callers are assured to have free tx slots
         * (taken from tg3... though the case where that is wrong is
         *  not terribly harmful)
         */
        mal_poll_enable(dev->mal, &dev->commac);
}

static inline void emac_rx_disable_async(struct emac_instance *dev)
{
        struct emac_regs __iomem *p = dev->emacp;
        u32 r;

        DBG(dev, "rx_disable_async" NL);

        r = in_be32(&p->mr0);
        if (r & EMAC_MR0_RXE)
                out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
}

static int emac_reset(struct emac_instance *dev)
{
        struct emac_regs __iomem *p = dev->emacp;
        int n = 20;
        bool __maybe_unused try_internal_clock = false;

        DBG(dev, "reset" NL);

        if (!dev->reset_failed) {
                /* 40x erratum suggests stopping RX channel before reset,
                 * we stop TX as well
                 */
                emac_rx_disable(dev);
                emac_tx_disable(dev);
        }

#ifdef CONFIG_PPC_DCR_NATIVE
do_retry:
        /*
         * PPC460EX/GT Embedded Processor Advanced User's Manual
         * section 28.10.1 Mode Register 0 (EMACx_MR0) states:
         * Note: The PHY must provide a TX Clk in order to perform a soft reset
         * of the EMAC. If none is present, select the internal clock
         * (SDR0_ETH_CFG[EMACx_PHY_CLK] = 1).
         * After a soft reset, select the external clock.
         *
         * The AR8035-A PHY Meraki MR24 does not provide a TX Clk if the
         * ethernet cable is not attached. This causes the reset to timeout
         * and the PHY detection code in emac_init_phy() is unable to
         * communicate and detect the AR8035-A PHY. As a result, the emac
         * driver bails out early and the user has no ethernet.
         * In order to stay compatible with existing configurations, the
         * driver will temporarily switch to the internal clock, after
         * the first reset fails.
         */
        if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) {
                if (try_internal_clock || (dev->phy_address == 0xffffffff &&
                                           dev->phy_map == 0xffffffff)) {
                        /* No PHY: select internal loop clock before reset */
                        dcri_clrset(SDR0, SDR0_ETH_CFG,
                                    0, SDR0_ETH_CFG_ECS << dev->cell_index);
                } else {
                        /* PHY present: select external clock before reset */
                        dcri_clrset(SDR0, SDR0_ETH_CFG,
                                    SDR0_ETH_CFG_ECS << dev->cell_index, 0);
                }
        }
#endif

        out_be32(&p->mr0, EMAC_MR0_SRST);
        while ((in_be32(&p->mr0) & EMAC_MR0_SRST) && n)
                --n;

#ifdef CONFIG_PPC_DCR_NATIVE
        if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) {
                if (!n && !try_internal_clock) {
                        /* first attempt has timed out. */
                        n = 20;
                        try_internal_clock = true;
                        goto do_retry;
                }

                if (try_internal_clock || (dev->phy_address == 0xffffffff &&
                                           dev->phy_map == 0xffffffff)) {
                        /* No PHY: restore external clock source after reset */
                        dcri_clrset(SDR0, SDR0_ETH_CFG,
                                    SDR0_ETH_CFG_ECS << dev->cell_index, 0);
                }
        }
#endif

        if (n) {
                dev->reset_failed = 0;
                return 0;
        } else {
                emac_report_timeout_error(dev, "reset timeout");
                dev->reset_failed = 1;
                return -ETIMEDOUT;
        }
}

static void emac_hash_mc(struct emac_instance *dev)
{
        const int regs = EMAC_XAHT_REGS(dev);
        u32 *gaht_base = emac_gaht_base(dev);
        u32 gaht_temp[EMAC_XAHT_MAX_REGS];
        struct netdev_hw_addr *ha;
        int i;

        DBG(dev, "hash_mc %d" NL, netdev_mc_count(dev->ndev));

        memset(gaht_temp, 0, sizeof (gaht_temp));

        netdev_for_each_mc_addr(ha, dev->ndev) {
                int slot, reg, mask;
                DBG2(dev, "mc %pM" NL, ha->addr);

                slot = EMAC_XAHT_CRC_TO_SLOT(dev,
                                             ether_crc(ETH_ALEN, ha->addr));
                reg = EMAC_XAHT_SLOT_TO_REG(dev, slot);
                mask = EMAC_XAHT_SLOT_TO_MASK(dev, slot);

                gaht_temp[reg] |= mask;
        }

        for (i = 0; i < regs; i++)
                out_be32(gaht_base + i, gaht_temp[i]);
}

static inline u32 emac_iff2rmr(struct net_device *ndev)
{
        struct emac_instance *dev = netdev_priv(ndev);
        u32 r;

        r = EMAC_RMR_SP | EMAC_RMR_SFCS | EMAC_RMR_IAE | EMAC_RMR_BAE;

        if (emac_has_feature(dev, EMAC_FTR_EMAC4))
            r |= EMAC4_RMR_BASE;
        else
            r |= EMAC_RMR_BASE;

        if (ndev->flags & IFF_PROMISC)
                r |= EMAC_RMR_PME;
        else if (ndev->flags & IFF_ALLMULTI ||
                         (netdev_mc_count(ndev) > EMAC_XAHT_SLOTS(dev)))
                r |= EMAC_RMR_PMME;
        else if (!netdev_mc_empty(ndev))
                r |= EMAC_RMR_MAE;

        if (emac_has_feature(dev, EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE)) {
                r &= ~EMAC4_RMR_MJS_MASK;
                r |= EMAC4_RMR_MJS(ndev->mtu);
        }

        return r;
}

static u32 __emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
{
        u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC_MR1_TR0_MULT;

        DBG2(dev, "__emac_calc_base_mr1" NL);

        switch(tx_size) {
        case 2048:
                ret |= EMAC_MR1_TFS_2K;
                break;
        default:
                printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n",
                       dev->ndev->name, tx_size);
        }

        switch(rx_size) {
        case 16384:
                ret |= EMAC_MR1_RFS_16K;
                break;
        case 4096:
                ret |= EMAC_MR1_RFS_4K;
                break;
        default:
                printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
                       dev->ndev->name, rx_size);
        }

        return ret;
}

static u32 __emac4_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
{
        u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC4_MR1_TR |
                EMAC4_MR1_OBCI(dev->opb_bus_freq / 1000000);

        DBG2(dev, "__emac4_calc_base_mr1" NL);

        switch(tx_size) {
        case 16384:
                ret |= EMAC4_MR1_TFS_16K;
                break;
        case 8192:
                ret |= EMAC4_MR1_TFS_8K;
                break;
        case 4096:
                ret |= EMAC4_MR1_TFS_4K;
                break;
        case 2048:
                ret |= EMAC4_MR1_TFS_2K;
                break;
        default:
                printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n",
                       dev->ndev->name, tx_size);
        }

        switch(rx_size) {
        case 16384:
                ret |= EMAC4_MR1_RFS_16K;
                break;
        case 8192:
                ret |= EMAC4_MR1_RFS_8K;
                break;
        case 4096:
                ret |= EMAC4_MR1_RFS_4K;
                break;
        case 2048:
                ret |= EMAC4_MR1_RFS_2K;
                break;
        default:
                printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
                       dev->ndev->name, rx_size);
        }

        return ret;
}

static u32 emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
{
        return emac_has_feature(dev, EMAC_FTR_EMAC4) ?
                __emac4_calc_base_mr1(dev, tx_size, rx_size) :
                __emac_calc_base_mr1(dev, tx_size, rx_size);
}

static inline u32 emac_calc_trtr(struct emac_instance *dev, unsigned int size)
{
        if (emac_has_feature(dev, EMAC_FTR_EMAC4))
                return ((size >> 6) - 1) << EMAC_TRTR_SHIFT_EMAC4;
        else
                return ((size >> 6) - 1) << EMAC_TRTR_SHIFT;
}

static inline u32 emac_calc_rwmr(struct emac_instance *dev,
                                 unsigned int low, unsigned int high)
{
        if (emac_has_feature(dev, EMAC_FTR_EMAC4))
                return (low << 22) | ( (high & 0x3ff) << 6);
        else
                return (low << 23) | ( (high & 0x1ff) << 7);
}

static int emac_configure(struct emac_instance *dev)
{
        struct emac_regs __iomem *p = dev->emacp;
        struct net_device *ndev = dev->ndev;
        int tx_size, rx_size, link = netif_carrier_ok(dev->ndev);
        u32 r, mr1 = 0;

        DBG(dev, "configure" NL);

        if (!link) {
                out_be32(&p->mr1, in_be32(&p->mr1)
                         | EMAC_MR1_FDE | EMAC_MR1_ILE);
                udelay(100);
        } else if (emac_reset(dev) < 0)
                return -ETIMEDOUT;

        if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
                tah_reset(dev->tah_dev);

        DBG(dev, " link = %d duplex = %d, pause = %d, asym_pause = %d\n",
            link, dev->phy.duplex, dev->phy.pause, dev->phy.asym_pause);

        /* Default fifo sizes */
        tx_size = dev->tx_fifo_size;
        rx_size = dev->rx_fifo_size;

        /* No link, force loopback */
        if (!link)
                mr1 = EMAC_MR1_FDE | EMAC_MR1_ILE;

        /* Check for full duplex */
        else if (dev->phy.duplex == DUPLEX_FULL)
                mr1 |= EMAC_MR1_FDE | EMAC_MR1_MWSW_001;

        /* Adjust fifo sizes, mr1 and timeouts based on link speed */
        dev->stop_timeout = STOP_TIMEOUT_10;
        switch (dev->phy.speed) {
        case SPEED_1000:
                if (emac_phy_gpcs(dev->phy.mode)) {
                        mr1 |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_MF_IPPA(
                                (dev->phy.gpcs_address != 0xffffffff) ?
                                 dev->phy.gpcs_address : dev->phy.address);

                        /* Put some arbitrary OUI, Manuf & Rev IDs so we can
                         * identify this GPCS PHY later.
                         */
                        out_be32(&p->u1.emac4.ipcr, 0xdeadbeef);
                } else
                        mr1 |= EMAC_MR1_MF_1000;

                /* Extended fifo sizes */
                tx_size = dev->tx_fifo_size_gige;
                rx_size = dev->rx_fifo_size_gige;

                if (dev->ndev->mtu > ETH_DATA_LEN) {
                        if (emac_has_feature(dev, EMAC_FTR_EMAC4))
                                mr1 |= EMAC4_MR1_JPSM;
                        else
                                mr1 |= EMAC_MR1_JPSM;
                        dev->stop_timeout = STOP_TIMEOUT_1000_JUMBO;
                } else
                        dev->stop_timeout = STOP_TIMEOUT_1000;
                break;
        case SPEED_100:
                mr1 |= EMAC_MR1_MF_100;
                dev->stop_timeout = STOP_TIMEOUT_100;
                break;
        default: /* make gcc happy */
                break;
        }

        if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
                rgmii_set_speed(dev->rgmii_dev, dev->rgmii_port,
                                dev->phy.speed);
        if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
                zmii_set_speed(dev->zmii_dev, dev->zmii_port, dev->phy.speed);

        /* on 40x erratum forces us to NOT use integrated flow control,
         * let's hope it works on 44x ;)
         */
        if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x) &&
            dev->phy.duplex == DUPLEX_FULL) {
                if (dev->phy.pause)
                        mr1 |= EMAC_MR1_EIFC | EMAC_MR1_APP;
                else if (dev->phy.asym_pause)
                        mr1 |= EMAC_MR1_APP;
        }

        /* Add base settings & fifo sizes & program MR1 */
        mr1 |= emac_calc_base_mr1(dev, tx_size, rx_size);
        out_be32(&p->mr1, mr1);

        /* Set individual MAC address */
        out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]);
        out_be32(&p->ialr, (ndev->dev_addr[2] << 24) |
                 (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) |
                 ndev->dev_addr[5]);

        /* VLAN Tag Protocol ID */
        out_be32(&p->vtpid, 0x8100);

        /* Receive mode register */
        r = emac_iff2rmr(ndev);
        if (r & EMAC_RMR_MAE)
                emac_hash_mc(dev);
        out_be32(&p->rmr, r);

        /* FIFOs thresholds */
        if (emac_has_feature(dev, EMAC_FTR_EMAC4))
                r = EMAC4_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1,
                               tx_size / 2 / dev->fifo_entry_size);
        else
                r = EMAC_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1,
                              tx_size / 2 / dev->fifo_entry_size);
        out_be32(&p->tmr1, r);
        out_be32(&p->trtr, emac_calc_trtr(dev, tx_size / 2));

        /* PAUSE frame is sent when RX FIFO reaches its high-water mark,
           there should be still enough space in FIFO to allow the our link
           partner time to process this frame and also time to send PAUSE
           frame itself.

           Here is the worst case scenario for the RX FIFO "headroom"
           (from "The Switch Book") (100Mbps, without preamble, inter-frame gap):

           1) One maximum-length frame on TX                    1522 bytes
           2) One PAUSE frame time                                64 bytes
           3) PAUSE frame decode time allowance                   64 bytes
           4) One maximum-length frame on RX                    1522 bytes
           5) Round-trip propagation delay of the link (100Mb)    15 bytes
           ----------
           3187 bytes

           I chose to set high-water mark to RX_FIFO_SIZE / 4 (1024 bytes)
           low-water mark  to RX_FIFO_SIZE / 8 (512 bytes)
         */
        r = emac_calc_rwmr(dev, rx_size / 8 / dev->fifo_entry_size,
                           rx_size / 4 / dev->fifo_entry_size);
        out_be32(&p->rwmr, r);

        /* Set PAUSE timer to the maximum */
        out_be32(&p->ptr, 0xffff);

        /* IRQ sources */
        r = EMAC_ISR_OVR | EMAC_ISR_BP | EMAC_ISR_SE |
                EMAC_ISR_ALE | EMAC_ISR_BFCS | EMAC_ISR_PTLE | EMAC_ISR_ORE |
                EMAC_ISR_IRE | EMAC_ISR_TE;
        if (emac_has_feature(dev, EMAC_FTR_EMAC4))
            r |= EMAC4_ISR_TXPE | EMAC4_ISR_RXPE /* | EMAC4_ISR_TXUE |
                                                  EMAC4_ISR_RXOE | */;
        out_be32(&p->iser,  r);

        /* We need to take GPCS PHY out of isolate mode after EMAC reset */
        if (emac_phy_gpcs(dev->phy.mode)) {
                if (dev->phy.gpcs_address != 0xffffffff)
                        emac_mii_reset_gpcs(&dev->phy);
                else
                        emac_mii_reset_phy(&dev->phy);
        }

        return 0;
}

static void emac_reinitialize(struct emac_instance *dev)
{
        DBG(dev, "reinitialize" NL);

        emac_netif_stop(dev);
        if (!emac_configure(dev)) {
                emac_tx_enable(dev);
                emac_rx_enable(dev);
        }
        emac_netif_start(dev);
}

static void emac_full_tx_reset(struct emac_instance *dev)
{
        DBG(dev, "full_tx_reset" NL);

        emac_tx_disable(dev);
        mal_disable_tx_channel(dev->mal, dev->mal_tx_chan);
        emac_clean_tx_ring(dev);
        dev->tx_cnt = dev->tx_slot = dev->ack_slot = 0;

        emac_configure(dev);

        mal_enable_tx_channel(dev->mal, dev->mal_tx_chan);
        emac_tx_enable(dev);
        emac_rx_enable(dev);
}

static void emac_reset_work(struct work_struct *work)
{
        struct emac_instance *dev = container_of(work, struct emac_instance, reset_work);

        DBG(dev, "reset_work" NL);

        mutex_lock(&dev->link_lock);
        if (dev->opened) {
                emac_netif_stop(dev);
                emac_full_tx_reset(dev);
                emac_netif_start(dev);
        }
        mutex_unlock(&dev->link_lock);
}

static void emac_tx_timeout(struct net_device *ndev, unsigned int txqueue)
{
        struct emac_instance *dev = netdev_priv(ndev);

        DBG(dev, "tx_timeout" NL);

        schedule_work(&dev->reset_work);
}


static inline int emac_phy_done(struct emac_instance *dev, u32 stacr)
{
        int done = !!(stacr & EMAC_STACR_OC);

        if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
                done = !done;

        return done;
};

static int __emac_mdio_read(struct emac_instance *dev, u8 id, u8 reg)
{
        struct emac_regs __iomem *p = dev->emacp;
        u32 r = 0;
        int n, err = -ETIMEDOUT;

        mutex_lock(&dev->mdio_lock);

        DBG2(dev, "mdio_read(%02x,%02x)" NL, id, reg);

        /* Enable proper MDIO port */
        if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
                zmii_get_mdio(dev->zmii_dev, dev->zmii_port);
        if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
                rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port);

        /* Wait for management interface to become idle */
        n = 20;
        while (!emac_phy_done(dev, in_be32(&p->stacr))) {
                udelay(1);
                if (!--n) {
                        DBG2(dev, " -> timeout wait idle\n");
                        goto bail;
                }
        }

        /* Issue read command */
        if (emac_has_feature(dev, EMAC_FTR_EMAC4))
                r = EMAC4_STACR_BASE(dev->opb_bus_freq);
        else
                r = EMAC_STACR_BASE(dev->opb_bus_freq);
        if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
                r |= EMAC_STACR_OC;
        if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR))
                r |= EMACX_STACR_STAC_READ;
        else
                r |= EMAC_STACR_STAC_READ;
        r |= (reg & EMAC_STACR_PRA_MASK)
                | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT);
        out_be32(&p->stacr, r);

        /* Wait for read to complete */
        n = 200;
        while (!emac_phy_done(dev, (r = in_be32(&p->stacr)))) {
                udelay(1);
                if (!--n) {
                        DBG2(dev, " -> timeout wait complete\n");
                        goto bail;
                }
        }

        if (unlikely(r & EMAC_STACR_PHYE)) {
                DBG(dev, "mdio_read(%02x, %02x) failed" NL, id, reg);
                err = -EREMOTEIO;
                goto bail;
        }

        r = ((r >> EMAC_STACR_PHYD_SHIFT) & EMAC_STACR_PHYD_MASK);

        DBG2(dev, "mdio_read -> %04x" NL, r);
        err = 0;
 bail:
        if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
                rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port);
        if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
                zmii_put_mdio(dev->zmii_dev, dev->zmii_port);
        mutex_unlock(&dev->mdio_lock);

        return err == 0 ? r : err;
}

static void __emac_mdio_write(struct emac_instance *dev, u8 id, u8 reg,
                              u16 val)
{
        struct emac_regs __iomem *p = dev->emacp;
        u32 r = 0;
        int n;

        mutex_lock(&dev->mdio_lock);

        DBG2(dev, "mdio_write(%02x,%02x,%04x)" NL, id, reg, val);

        /* Enable proper MDIO port */
        if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
                zmii_get_mdio(dev->zmii_dev, dev->zmii_port);
        if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
                rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port);

        /* Wait for management interface to be idle */
        n = 20;
        while (!emac_phy_done(dev, in_be32(&p->stacr))) {
                udelay(1);
                if (!--n) {
                        DBG2(dev, " -> timeout wait idle\n");
                        goto bail;
                }
        }

        /* Issue write command */
        if (emac_has_feature(dev, EMAC_FTR_EMAC4))
                r = EMAC4_STACR_BASE(dev->opb_bus_freq);
        else
                r = EMAC_STACR_BASE(dev->opb_bus_freq);
        if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
                r |= EMAC_STACR_OC;
        if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR))
                r |= EMACX_STACR_STAC_WRITE;
        else
                r |= EMAC_STACR_STAC_WRITE;
        r |= (reg & EMAC_STACR_PRA_MASK) |
                ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) |
                (val << EMAC_STACR_PHYD_SHIFT);
        out_be32(&p->stacr, r);

        /* Wait for write to complete */
        n = 200;
        while (!emac_phy_done(dev, in_be32(&p->stacr))) {
                udelay(1);
                if (!--n) {
                        DBG2(dev, " -> timeout wait complete\n");
                        goto bail;
                }
        }
 bail:
        if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
                rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port);
        if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
                zmii_put_mdio(dev->zmii_dev, dev->zmii_port);
        mutex_unlock(&dev->mdio_lock);
}

static int emac_mdio_read(struct net_device *ndev, int id, int reg)
{
        struct emac_instance *dev = netdev_priv(ndev);
        int res;

        res = __emac_mdio_read((dev->mdio_instance &&
                                dev->phy.gpcs_address != id) ?
                                dev->mdio_instance : dev,
                               (u8) id, (u8) reg);
        return res;
}

static void emac_mdio_write(struct net_device *ndev, int id, int reg, int val)
{
        struct emac_instance *dev = netdev_priv(ndev);

        __emac_mdio_write((dev->mdio_instance &&
                           dev->phy.gpcs_address != id) ?
                           dev->mdio_instance : dev,
                          (u8) id, (u8) reg, (u16) val);
}

/* Tx lock BH */
static void __emac_set_multicast_list(struct emac_instance *dev)
{
        struct emac_regs __iomem *p = dev->emacp;
        u32 rmr = emac_iff2rmr(dev->ndev);

        DBG(dev, "__multicast %08x" NL, rmr);

        /* I decided to relax register access rules here to avoid
         * full EMAC reset.
         *
         * There is a real problem with EMAC4 core if we use MWSW_001 bit
         * in MR1 register and do a full EMAC reset.
         * One TX BD status update is delayed and, after EMAC reset, it
         * never happens, resulting in TX hung (it'll be recovered by TX
         * timeout handler eventually, but this is just gross).
         * So we either have to do full TX reset or try to cheat here :)
         *
         * The only required change is to RX mode register, so I *think* all
         * we need is just to stop RX channel. This seems to work on all
         * tested SoCs.                                                --ebs
         *
         * If we need the full reset, we might just trigger the workqueue
         * and do it async... a bit nasty but should work --BenH
         */
        dev->mcast_pending = 0;
        emac_rx_disable(dev);
        if (rmr & EMAC_RMR_MAE)
                emac_hash_mc(dev);
        out_be32(&p->rmr, rmr);
        emac_rx_enable(dev);
}

/* Tx lock BH */
static void emac_set_multicast_list(struct net_device *ndev)
{
        struct emac_instance *dev = netdev_priv(ndev);

        DBG(dev, "multicast" NL);

        BUG_ON(!netif_running(dev->ndev));

        if (dev->no_mcast) {
                dev->mcast_pending = 1;
                return;
        }

        mutex_lock(&dev->link_lock);

        __emac_set_multicast_list(dev);
        mutex_unlock(&dev->link_lock);
}

static int emac_set_mac_address(struct net_device *ndev, void *sa)
{
        struct emac_instance *dev = netdev_priv(ndev);
        struct sockaddr *addr = sa;
        struct emac_regs __iomem *p = dev->emacp;

        if (!is_valid_ether_addr(addr->sa_data))
               return -EADDRNOTAVAIL;

        mutex_lock(&dev->link_lock);

        memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);

        emac_rx_disable(dev);
        emac_tx_disable(dev);
        out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]);
        out_be32(&p->ialr, (ndev->dev_addr[2] << 24) |
                (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) |
                ndev->dev_addr[5]);
        emac_tx_enable(dev);
        emac_rx_enable(dev);

        mutex_unlock(&dev->link_lock);

        return 0;
}

static int emac_resize_rx_ring(struct emac_instance *dev, int new_mtu)
{
        int rx_sync_size = emac_rx_sync_size(new_mtu);
        int rx_skb_size = emac_rx_skb_size(new_mtu);
        int i, ret = 0;
        int mr1_jumbo_bit_change = 0;

        mutex_lock(&dev->link_lock);
        emac_netif_stop(dev);
        emac_rx_disable(dev);
        mal_disable_rx_channel(dev->mal, dev->mal_rx_chan);

        if (dev->rx_sg_skb) {
                ++dev->estats.rx_dropped_resize;
                dev_kfree_skb(dev->rx_sg_skb);
                dev->rx_sg_skb = NULL;
        }

        /* Make a first pass over RX ring and mark BDs ready, dropping
         * non-processed packets on the way. We need this as a separate pass
         * to simplify error recovery in the case of allocation failure later.
         */
        for (i = 0; i < NUM_RX_BUFF; ++i) {
                if (dev->rx_desc[i].ctrl & MAL_RX_CTRL_FIRST)
                        ++dev->estats.rx_dropped_resize;

                dev->rx_desc[i].data_len = 0;
                dev->rx_desc[i].ctrl = MAL_RX_CTRL_EMPTY |
                    (i == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
        }

        /* Reallocate RX ring only if bigger skb buffers are required */
        if (rx_skb_size <= dev->rx_skb_size)
                goto skip;

        /* Second pass, allocate new skbs */
        for (i = 0; i < NUM_RX_BUFF; ++i) {
                struct sk_buff *skb;

                skb = netdev_alloc_skb_ip_align(dev->ndev, rx_skb_size);
                if (!skb) {
                        ret = -ENOMEM;
                        goto oom;
                }

                BUG_ON(!dev->rx_skb[i]);
                dev_kfree_skb(dev->rx_skb[i]);

                dev->rx_desc[i].data_ptr =
                    dma_map_single(&dev->ofdev->dev, skb->data - NET_IP_ALIGN,
                                   rx_sync_size, DMA_FROM_DEVICE)
                                   + NET_IP_ALIGN;
                dev->rx_skb[i] = skb;
        }
 skip:
        /* Check if we need to change "Jumbo" bit in MR1 */
        if (emac_has_feature(dev, EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE)) {
                mr1_jumbo_bit_change = (new_mtu > ETH_DATA_LEN) ||
                                (dev->ndev->mtu > ETH_DATA_LEN);
        } else {
                mr1_jumbo_bit_change = (new_mtu > ETH_DATA_LEN) ^
                                (dev->ndev->mtu > ETH_DATA_LEN);
        }

        if (mr1_jumbo_bit_change) {
                /* This is to prevent starting RX channel in emac_rx_enable() */
                set_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);

                dev->ndev->mtu = new_mtu;
                emac_full_tx_reset(dev);
        }

        mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(new_mtu));
 oom:
        /* Restart RX */
        clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
        dev->rx_slot = 0;
        mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
        emac_rx_enable(dev);
        emac_netif_start(dev);
        mutex_unlock(&dev->link_lock);

        return ret;
}

/* Process ctx, rtnl_lock semaphore */
static int emac_change_mtu(struct net_device *ndev, int new_mtu)
{
        struct emac_instance *dev = netdev_priv(ndev);
        int ret = 0;

        DBG(dev, "change_mtu(%d)" NL, new_mtu);

        if (netif_running(ndev)) {
                /* Check if we really need to reinitialize RX ring */
                if (emac_rx_skb_size(ndev->mtu) != emac_rx_skb_size(new_mtu))
                        ret = emac_resize_rx_ring(dev, new_mtu);
        }

        if (!ret) {
                ndev->mtu = new_mtu;
                dev->rx_skb_size = emac_rx_skb_size(new_mtu);
                dev->rx_sync_size = emac_rx_sync_size(new_mtu);
        }

        return ret;
}

static void emac_clean_tx_ring(struct emac_instance *dev)
{
        int i;

        for (i = 0; i < NUM_TX_BUFF; ++i) {
                if (dev->tx_skb[i]) {
                        dev_kfree_skb(dev->tx_skb[i]);
                        dev->tx_skb[i] = NULL;
                        if (dev->tx_desc[i].ctrl & MAL_TX_CTRL_READY)
                                ++dev->estats.tx_dropped;
                }
                dev->tx_desc[i].ctrl = 0;
                dev->tx_desc[i].data_ptr = 0;
        }
}

static void emac_clean_rx_ring(struct emac_instance *dev)
{
        int i;

        for (i = 0; i < NUM_RX_BUFF; ++i)
                if (dev->rx_skb[i]) {
                        dev->rx_desc[i].ctrl = 0;
                        dev_kfree_skb(dev->rx_skb[i]);
                        dev->rx_skb[i] = NULL;
                        dev->rx_desc[i].data_ptr = 0;
                }

        if (dev->rx_sg_skb) {
                dev_kfree_skb(dev->rx_sg_skb);
                dev->rx_sg_skb = NULL;
        }
}

static int
__emac_prepare_rx_skb(struct sk_buff *skb, struct emac_instance *dev, int slot)
{
        if (unlikely(!skb))
                return -ENOMEM;

        dev->rx_skb[slot] = skb;
        dev->rx_desc[slot].data_len = 0;

        dev->rx_desc[slot].data_ptr =
            dma_map_single(&dev->ofdev->dev, skb->data - NET_IP_ALIGN,
                           dev->rx_sync_size, DMA_FROM_DEVICE) + NET_IP_ALIGN;
        wmb();
        dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
            (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);

        return 0;
}

static int
emac_alloc_rx_skb(struct emac_instance *dev, int slot)
{
        struct sk_buff *skb;

        skb = __netdev_alloc_skb_ip_align(dev->ndev, dev->rx_skb_size,
                                          GFP_KERNEL);

        return __emac_prepare_rx_skb(skb, dev, slot);
}

static int
emac_alloc_rx_skb_napi(struct emac_instance *dev, int slot)
{
        struct sk_buff *skb;

        skb = napi_alloc_skb(&dev->mal->napi, dev->rx_skb_size);

        return __emac_prepare_rx_skb(skb, dev, slot);
}

static void emac_print_link_status(struct emac_instance *dev)
{
        if (netif_carrier_ok(dev->ndev))
                printk(KERN_INFO "%s: link is up, %d %s%s\n",
                       dev->ndev->name, dev->phy.speed,
                       dev->phy.duplex == DUPLEX_FULL ? "FDX" : "HDX",
                       dev->phy.pause ? ", pause enabled" :
                       dev->phy.asym_pause ? ", asymmetric pause enabled" : "");
        else
                printk(KERN_INFO "%s: link is down\n", dev->ndev->name);
}

/* Process ctx, rtnl_lock semaphore */
static int emac_open(struct net_device *ndev)
{
        struct emac_instance *dev = netdev_priv(ndev);
        int err, i;

        DBG(dev, "open" NL);

        /* Setup error IRQ handler */
        err = request_irq(dev->emac_irq, emac_irq, 0, "EMAC", dev);
        if (err) {
                printk(KERN_ERR "%s: failed to request IRQ %d\n",
                       ndev->name, dev->emac_irq);
                return err;
        }

        /* Allocate RX ring */
        for (i = 0; i < NUM_RX_BUFF; ++i)
                if (emac_alloc_rx_skb(dev, i)) {
                        printk(KERN_ERR "%s: failed to allocate RX ring\n",
                               ndev->name);
                        goto oom;
                }

        dev->tx_cnt = dev->tx_slot = dev->ack_slot = dev->rx_slot = 0;
        clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
        dev->rx_sg_skb = NULL;

        mutex_lock(&dev->link_lock);
        dev->opened = 1;

        /* Start PHY polling now.
         */
        if (dev->phy.address >= 0) {
                int link_poll_interval;
                if (dev->phy.def->ops->poll_link(&dev->phy)) {
                        dev->phy.def->ops->read_link(&dev->phy);
                        emac_rx_clk_default(dev);
                        netif_carrier_on(dev->ndev);
                        link_poll_interval = PHY_POLL_LINK_ON;
                } else {
                        emac_rx_clk_tx(dev);
                        netif_carrier_off(dev->ndev);
                        link_poll_interval = PHY_POLL_LINK_OFF;
                }
                dev->link_polling = 1;
                wmb();
                schedule_delayed_work(&dev->link_work, link_poll_interval);
                emac_print_link_status(dev);
        } else
                netif_carrier_on(dev->ndev);

        /* Required for Pause packet support in EMAC */
        dev_mc_add_global(ndev, default_mcast_addr);

        emac_configure(dev);
        mal_poll_add(dev->mal, &dev->commac);
        mal_enable_tx_channel(dev->mal, dev->mal_tx_chan);
        mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(ndev->mtu));
        mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
        emac_tx_enable(dev);
        emac_rx_enable(dev);
        emac_netif_start(dev);

        mutex_unlock(&dev->link_lock);

        return 0;
 oom:
        emac_clean_rx_ring(dev);
        free_irq(dev->emac_irq, dev);

        return -ENOMEM;
}

/* BHs disabled */
#if 0
static int emac_link_differs(struct emac_instance *dev)
{
        u32 r = in_be32(&dev->emacp->mr1);

        int duplex = r & EMAC_MR1_FDE ? DUPLEX_FULL : DUPLEX_HALF;
        int speed, pause, asym_pause;

        if (r & EMAC_MR1_MF_1000)
                speed = SPEED_1000;
        else if (r & EMAC_MR1_MF_100)
                speed = SPEED_100;
        else
                speed = SPEED_10;

        switch (r & (EMAC_MR1_EIFC | EMAC_MR1_APP)) {
        case (EMAC_MR1_EIFC | EMAC_MR1_APP):
                pause = 1;
                asym_pause = 0;
                break;
        case EMAC_MR1_APP:
                pause = 0;
                asym_pause = 1;
                break;
        default:
                pause = asym_pause = 0;
        }
        return speed != dev->phy.speed || duplex != dev->phy.duplex ||
            pause != dev->phy.pause || asym_pause != dev->phy.asym_pause;
}
#endif

static void emac_link_timer(struct work_struct *work)
{
        struct emac_instance *dev =
                container_of(to_delayed_work(work),
                             struct emac_instance, link_work);
        int link_poll_interval;

        mutex_lock(&dev->link_lock);
        DBG2(dev, "link timer" NL);

        if (!dev->opened)
                goto bail;

        if (dev->phy.def->ops->poll_link(&dev->phy)) {
                if (!netif_carrier_ok(dev->ndev)) {
                        emac_rx_clk_default(dev);
                        /* Get new link parameters */
                        dev->phy.def->ops->read_link(&dev->phy);

                        netif_carrier_on(dev->ndev);
                        emac_netif_stop(dev);
                        emac_full_tx_reset(dev);
                        emac_netif_start(dev);
                        emac_print_link_status(dev);
                }
                link_poll_interval = PHY_POLL_LINK_ON;
        } else {
                if (netif_carrier_ok(dev->ndev)) {
                        emac_rx_clk_tx(dev);
                        netif_carrier_off(dev->ndev);
                        netif_tx_disable(dev->ndev);
                        emac_reinitialize(dev);
                        emac_print_link_status(dev);
                }
                link_poll_interval = PHY_POLL_LINK_OFF;
        }
        schedule_delayed_work(&dev->link_work, link_poll_interval);
 bail:
        mutex_unlock(&dev->link_lock);
}

static void emac_force_link_update(struct emac_instance *dev)
{
        netif_carrier_off(dev->ndev);
        smp_rmb();
        if (dev->link_polling) {
                cancel_delayed_work_sync(&dev->link_work);
                if (dev->link_polling)
                        schedule_delayed_work(&dev->link_work,  PHY_POLL_LINK_OFF);
        }
}

/* Process ctx, rtnl_lock semaphore */
static int emac_close(struct net_device *ndev)
{
        struct emac_instance *dev = netdev_priv(ndev);

        DBG(dev, "close" NL);

        if (dev->phy.address >= 0) {
                dev->link_polling = 0;
                cancel_delayed_work_sync(&dev->link_work);
        }
        mutex_lock(&dev->link_lock);
        emac_netif_stop(dev);
        dev->opened = 0;
        mutex_unlock(&dev->link_lock);

        emac_rx_disable(dev);
        emac_tx_disable(dev);
        mal_disable_rx_channel(dev->mal, dev->mal_rx_chan);
        mal_disable_tx_channel(dev->mal, dev->mal_tx_chan);
        mal_poll_del(dev->mal, &dev->commac);

        emac_clean_tx_ring(dev);
        emac_clean_rx_ring(dev);

        free_irq(dev->emac_irq, dev);

        netif_carrier_off(ndev);

        return 0;
}

static inline u16 emac_tx_csum(struct emac_instance *dev,
                               struct sk_buff *skb)
{
        if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) &&
                (skb->ip_summed == CHECKSUM_PARTIAL)) {
                ++dev->stats.tx_packets_csum;
                return EMAC_TX_CTRL_TAH_CSUM;
        }
        return 0;
}

static inline netdev_tx_t emac_xmit_finish(struct emac_instance *dev, int len)
{
        struct emac_regs __iomem *p = dev->emacp;
        struct net_device *ndev = dev->ndev;

        /* Send the packet out. If the if makes a significant perf
         * difference, then we can store the TMR0 value in "dev"
         * instead
         */
        if (emac_has_feature(dev, EMAC_FTR_EMAC4))
                out_be32(&p->tmr0, EMAC4_TMR0_XMIT);
        else
                out_be32(&p->tmr0, EMAC_TMR0_XMIT);

        if (unlikely(++dev->tx_cnt == NUM_TX_BUFF)) {
                netif_stop_queue(ndev);
                DBG2(dev, "stopped TX queue" NL);
        }

        netif_trans_update(ndev);
        ++dev->stats.tx_packets;
        dev->stats.tx_bytes += len;

        return NETDEV_TX_OK;
}

/* Tx lock BH */
static netdev_tx_t emac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
{
        struct emac_instance *dev = netdev_priv(ndev);
        unsigned int len = skb->len;
        int slot;

        u16 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
            MAL_TX_CTRL_LAST | emac_tx_csum(dev, skb);

        slot = dev->tx_slot++;
        if (dev->tx_slot == NUM_TX_BUFF) {
                dev->tx_slot = 0;
                ctrl |= MAL_TX_CTRL_WRAP;
        }

        DBG2(dev, "xmit(%u) %d" NL, len, slot);

        dev->tx_skb[slot] = skb;
        dev->tx_desc[slot].data_ptr = dma_map_single(&dev->ofdev->dev,
                                                     skb->data, len,
                                                     DMA_TO_DEVICE);
        dev->tx_desc[slot].data_len = (u16) len;
        wmb();
        dev->tx_desc[slot].ctrl = ctrl;

        return emac_xmit_finish(dev, len);
}

static inline int emac_xmit_split(struct emac_instance *dev, int slot,
                                  u32 pd, int len, int last, u16 base_ctrl)
{
        while (1) {
                u16 ctrl = base_ctrl;
                int chunk = min(len, MAL_MAX_TX_SIZE);
                len -= chunk;

                slot = (slot + 1) % NUM_TX_BUFF;

                if (last && !len)
                        ctrl |= MAL_TX_CTRL_LAST;
                if (slot == NUM_TX_BUFF - 1)
                        ctrl |= MAL_TX_CTRL_WRAP;

                dev->tx_skb[slot] = NULL;
                dev->tx_desc[slot].data_ptr = pd;
                dev->tx_desc[slot].data_len = (u16) chunk;
                dev->tx_desc[slot].ctrl = ctrl;
                ++dev->tx_cnt;

                if (!len)
                        break;

                pd += chunk;
        }
        return slot;
}

/* Tx lock BH disabled (SG version for TAH equipped EMACs) */
static netdev_tx_t
emac_start_xmit_sg(struct sk_buff *skb, struct net_device *ndev)
{
        struct emac_instance *dev = netdev_priv(ndev);
        int nr_frags = skb_shinfo(skb)->nr_frags;
        int len = skb->len, chunk;
        int slot, i;
        u16 ctrl;
        u32 pd;

        /* This is common "fast" path */
        if (likely(!nr_frags && len <= MAL_MAX_TX_SIZE))
                return emac_start_xmit(skb, ndev);

        len -= skb->data_len;

        /* Note, this is only an *estimation*, we can still run out of empty
         * slots because of the additional fragmentation into
         * MAL_MAX_TX_SIZE-sized chunks
         */
        if (unlikely(dev->tx_cnt + nr_frags + mal_tx_chunks(len) > NUM_TX_BUFF))
                goto stop_queue;

        ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
            emac_tx_csum(dev, skb);
        slot = dev->tx_slot;

        /* skb data */
        dev->tx_skb[slot] = NULL;
        chunk = min(len, MAL_MAX_TX_SIZE);
        dev->tx_desc[slot].data_ptr = pd =
            dma_map_single(&dev->ofdev->dev, skb->data, len, DMA_TO_DEVICE);
        dev->tx_desc[slot].data_len = (u16) chunk;
        len -= chunk;
        if (unlikely(len))
                slot = emac_xmit_split(dev, slot, pd + chunk, len, !nr_frags,
                                       ctrl);
        /* skb fragments */
        for (i = 0; i < nr_frags; ++i) {
                skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
                len = skb_frag_size(frag);

                if (unlikely(dev->tx_cnt + mal_tx_chunks(len) >= NUM_TX_BUFF))
                        goto undo_frame;

                pd = skb_frag_dma_map(&dev->ofdev->dev, frag, 0, len,
                                      DMA_TO_DEVICE);

                slot = emac_xmit_split(dev, slot, pd, len, i == nr_frags - 1,
                                       ctrl);
        }

        DBG2(dev, "xmit_sg(%u) %d - %d" NL, skb->len, dev->tx_slot, slot);

        /* Attach skb to the last slot so we don't release it too early */
        dev->tx_skb[slot] = skb;

        /* Send the packet out */
        if (dev->tx_slot == NUM_TX_BUFF - 1)
                ctrl |= MAL_TX_CTRL_WRAP;
        wmb();
        dev->tx_desc[dev->tx_slot].ctrl = ctrl;
        dev->tx_slot = (slot + 1) % NUM_TX_BUFF;

        return emac_xmit_finish(dev, skb->len);

 undo_frame:
        /* Well, too bad. Our previous estimation was overly optimistic.
         * Undo everything.
         */
        while (slot != dev->tx_slot) {
                dev->tx_desc[slot].ctrl = 0;
                --dev->tx_cnt;
                if (--slot < 0)
                        slot = NUM_TX_BUFF - 1;
        }
        ++dev->estats.tx_undo;

 stop_queue:
        netif_stop_queue(ndev);
        DBG2(dev, "stopped TX queue" NL);
        return NETDEV_TX_BUSY;
}

/* Tx lock BHs */
static void emac_parse_tx_error(struct emac_instance *dev, u16 ctrl)
{
        struct emac_error_stats *st = &dev->estats;

        DBG(dev, "BD TX error %04x" NL, ctrl);

        ++st->tx_bd_errors;
        if (ctrl & EMAC_TX_ST_BFCS)
                ++st->tx_bd_bad_fcs;
        if (ctrl & EMAC_TX_ST_LCS)
                ++st->tx_bd_carrier_loss;
        if (ctrl & EMAC_TX_ST_ED)
                ++st->tx_bd_excessive_deferral;
        if (ctrl & EMAC_TX_ST_EC)
                ++st->tx_bd_excessive_collisions;
        if (ctrl & EMAC_TX_ST_LC)
                ++st->tx_bd_late_collision;
        if (ctrl & EMAC_TX_ST_MC)
                ++st->tx_bd_multple_collisions;
        if (ctrl & EMAC_TX_ST_SC)
                ++st->tx_bd_single_collision;
        if (ctrl & EMAC_TX_ST_UR)
                ++st->tx_bd_underrun;
        if (ctrl & EMAC_TX_ST_SQE)
                ++st->tx_bd_sqe;
}

static void emac_poll_tx(void *param)
{
        struct emac_instance *dev = param;
        u32 bad_mask;

        DBG2(dev, "poll_tx, %d %d" NL, dev->tx_cnt, dev->ack_slot);

        if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
                bad_mask = EMAC_IS_BAD_TX_TAH;
        else
                bad_mask = EMAC_IS_BAD_TX;

        netif_tx_lock_bh(dev->ndev);
        if (dev->tx_cnt) {
                u16 ctrl;
                int slot = dev->ack_slot, n = 0;
        again:
                ctrl = dev->tx_desc[slot].ctrl;
                if (!(ctrl & MAL_TX_CTRL_READY)) {
                        struct sk_buff *skb = dev->tx_skb[slot];
                        ++n;

                        if (skb) {
                                dev_kfree_skb(skb);
                                dev->tx_skb[slot] = NULL;
                        }
                        slot = (slot + 1) % NUM_TX_BUFF;

                        if (unlikely(ctrl & bad_mask))
                                emac_parse_tx_error(dev, ctrl);

                        if (--dev->tx_cnt)
                                goto again;
                }
                if (n) {
                        dev->ack_slot = slot;
                        if (netif_queue_stopped(dev->ndev) &&
                            dev->tx_cnt < EMAC_TX_WAKEUP_THRESH)
                                netif_wake_queue(dev->ndev);

                        DBG2(dev, "tx %d pkts" NL, n);
                }
        }
        netif_tx_unlock_bh(dev->ndev);
}

static inline void emac_recycle_rx_skb(struct emac_instance *dev, int slot,
                                       int len)
{
        struct sk_buff *skb = dev->rx_skb[slot];

        DBG2(dev, "recycle %d %d" NL, slot, len);

        if (len)
                dma_map_single(&dev->ofdev->dev, skb->data - NET_IP_ALIGN,
                               SKB_DATA_ALIGN(len + NET_IP_ALIGN),
                               DMA_FROM_DEVICE);

        dev->rx_desc[slot].data_len = 0;
        wmb();
        dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
            (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
}

static void emac_parse_rx_error(struct emac_instance *dev, u16 ctrl)
{
        struct emac_error_stats *st = &dev->estats;

        DBG(dev, "BD RX error %04x" NL, ctrl);

        ++st->rx_bd_errors;
        if (ctrl & EMAC_RX_ST_OE)
                ++st->rx_bd_overrun;
        if (ctrl & EMAC_RX_ST_BP)
                ++st->rx_bd_bad_packet;
        if (ctrl & EMAC_RX_ST_RP)
                ++st->rx_bd_runt_packet;
        if (ctrl & EMAC_RX_ST_SE)
                ++st->rx_bd_short_event;
        if (ctrl & EMAC_RX_ST_AE)
                ++st->rx_bd_alignment_error;
        if (ctrl & EMAC_RX_ST_BFCS)
                ++st->rx_bd_bad_fcs;
        if (ctrl & EMAC_RX_ST_PTL)
                ++st->rx_bd_packet_too_long;
        if (ctrl & EMAC_RX_ST_ORE)
                ++st->rx_bd_out_of_range;
        if (ctrl & EMAC_RX_ST_IRE)
                ++st->rx_bd_in_range;
}

static inline void emac_rx_csum(struct emac_instance *dev,
                                struct sk_buff *skb, u16 ctrl)
{
#ifdef CONFIG_IBM_EMAC_TAH
        if (!ctrl && dev->tah_dev) {
                skb->ip_summed = CHECKSUM_UNNECESSARY;
                ++dev->stats.rx_packets_csum;
        }
#endif
}

static inline int emac_rx_sg_append(struct emac_instance *dev, int slot)
{
        if (likely(dev->rx_sg_skb != NULL)) {
                int len = dev->rx_desc[slot].data_len;
                int tot_len = dev->rx_sg_skb->len + len;

                if (unlikely(tot_len + NET_IP_ALIGN > dev->rx_skb_size)) {
                        ++dev->estats.rx_dropped_mtu;
                        dev_kfree_skb(dev->rx_sg_skb);
                        dev->rx_sg_skb = NULL;
                } else {
                        memcpy(skb_tail_pointer(dev->rx_sg_skb),
                                         dev->rx_skb[slot]->data, len);
                        skb_put(dev->rx_sg_skb, len);
                        emac_recycle_rx_skb(dev, slot, len);
                        return 0;
                }
        }
        emac_recycle_rx_skb(dev, slot, 0);
        return -1;
}

/* NAPI poll context */
static int emac_poll_rx(void *param, int budget)
{
        struct emac_instance *dev = param;
        int slot = dev->rx_slot, received = 0;

        DBG2(dev, "poll_rx(%d)" NL, budget);

 again:
        while (budget > 0) {
                int len;
                struct sk_buff *skb;
                u16 ctrl = dev->rx_desc[slot].ctrl;

                if (ctrl & MAL_RX_CTRL_EMPTY)
                        break;

                skb = dev->rx_skb[slot];
                mb();
                len = dev->rx_desc[slot].data_len;

                if (unlikely(!MAL_IS_SINGLE_RX(ctrl)))
                        goto sg;

                ctrl &= EMAC_BAD_RX_MASK;
                if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
                        emac_parse_rx_error(dev, ctrl);
                        ++dev->estats.rx_dropped_error;
                        emac_recycle_rx_skb(dev, slot, 0);
                        len = 0;
                        goto next;
                }

                if (len < ETH_HLEN) {
                        ++dev->estats.rx_dropped_stack;
                        emac_recycle_rx_skb(dev, slot, len);
                        goto next;
                }

                if (len && len < EMAC_RX_COPY_THRESH) {
                        struct sk_buff *copy_skb;

                        copy_skb = napi_alloc_skb(&dev->mal->napi, len);
                        if (unlikely(!copy_skb))
                                goto oom;

                        memcpy(copy_skb->data - NET_IP_ALIGN,
                               skb->data - NET_IP_ALIGN,
                               len + NET_IP_ALIGN);
                        emac_recycle_rx_skb(dev, slot, len);
                        skb = copy_skb;
                } else if (unlikely(emac_alloc_rx_skb_napi(dev, slot)))
                        goto oom;

                skb_put(skb, len);
        push_packet:
                skb->protocol = eth_type_trans(skb, dev->ndev);
                emac_rx_csum(dev, skb, ctrl);

                if (unlikely(netif_receive_skb(skb) == NET_RX_DROP))
                        ++dev->estats.rx_dropped_stack;
        next:
                ++dev->stats.rx_packets;
        skip:
                dev->stats.rx_bytes += len;
                slot = (slot + 1) % NUM_RX_BUFF;
                --budget;
                ++received;
                continue;
        sg:
                if (ctrl & MAL_RX_CTRL_FIRST) {
                        BUG_ON(dev->rx_sg_skb);
                        if (unlikely(emac_alloc_rx_skb_napi(dev, slot))) {
                                DBG(dev, "rx OOM %d" NL, slot);
                                ++dev->estats.rx_dropped_oom;
                                emac_recycle_rx_skb(dev, slot, 0);
                        } else {
                                dev->rx_sg_skb = skb;
                                skb_put(skb, len);
                        }
                } else if (!emac_rx_sg_append(dev, slot) &&
                           (ctrl & MAL_RX_CTRL_LAST)) {

                        skb = dev->rx_sg_skb;
                        dev->rx_sg_skb = NULL;

                        ctrl &= EMAC_BAD_RX_MASK;
                        if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
                                emac_parse_rx_error(dev, ctrl);
                                ++dev->estats.rx_dropped_error;
                                dev_kfree_skb(skb);
                                len = 0;
                        } else
                                goto push_packet;
                }
                goto skip;
        oom:
                DBG(dev, "rx OOM %d" NL, slot);
                /* Drop the packet and recycle skb */
                ++dev->estats.rx_dropped_oom;
                emac_recycle_rx_skb(dev, slot, 0);
                goto next;
        }

        if (received) {
                DBG2(dev, "rx %d BDs" NL, received);
                dev->rx_slot = slot;
        }

        if (unlikely(budget && test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags))) {
                mb();
                if (!(dev->rx_desc[slot].ctrl & MAL_RX_CTRL_EMPTY)) {
                        DBG2(dev, "rx restart" NL);
                        received = 0;
                        goto again;
                }

                if (dev->rx_sg_skb) {
                        DBG2(dev, "dropping partial rx packet" NL);
                        ++dev->estats.rx_dropped_error;
                        dev_kfree_skb(dev->rx_sg_skb);
                        dev->rx_sg_skb = NULL;
                }

                clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
                mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
                emac_rx_enable(dev);
                dev->rx_slot = 0;
        }
        return received;
}

/* NAPI poll context */
static int emac_peek_rx(void *param)
{
        struct emac_instance *dev = param;

        return !(dev->rx_desc[dev->rx_slot].ctrl & MAL_RX_CTRL_EMPTY);
}

/* NAPI poll context */
static int emac_peek_rx_sg(void *param)
{
        struct emac_instance *dev = param;

        int slot = dev->rx_slot;
        while (1) {
                u16 ctrl = dev->rx_desc[slot].ctrl;
                if (ctrl & MAL_RX_CTRL_EMPTY)
                        return 0;
                else if (ctrl & MAL_RX_CTRL_LAST)
                        return 1;

                slot = (slot + 1) % NUM_RX_BUFF;

                /* I'm just being paranoid here :) */
                if (unlikely(slot == dev->rx_slot))
                        return 0;
        }
}

/* Hard IRQ */
static void emac_rxde(void *param)
{
        struct emac_instance *dev = param;

        ++dev->estats.rx_stopped;
        emac_rx_disable_async(dev);
}

/* Hard IRQ */
static irqreturn_t emac_irq(int irq, void *dev_instance)
{
        struct emac_instance *dev = dev_instance;
        struct emac_regs __iomem *p = dev->emacp;
        struct emac_error_stats *st = &dev->estats;
        u32 isr;

        spin_lock(&dev->lock);

        isr = in_be32(&p->isr);
        out_be32(&p->isr, isr);

        DBG(dev, "isr = %08x" NL, isr);

        if (isr & EMAC4_ISR_TXPE)
                ++st->tx_parity;
        if (isr & EMAC4_ISR_RXPE)
                ++st->rx_parity;
        if (isr & EMAC4_ISR_TXUE)
                ++st->tx_underrun;
        if (isr & EMAC4_ISR_RXOE)
                ++st->rx_fifo_overrun;
        if (isr & EMAC_ISR_OVR)
                ++st->rx_overrun;
        if (isr & EMAC_ISR_BP)
                ++st->rx_bad_packet;
        if (isr & EMAC_ISR_RP)
                ++st->rx_runt_packet;
        if (isr & EMAC_ISR_SE)
                ++st->rx_short_event;
        if (isr & EMAC_ISR_ALE)
                ++st->rx_alignment_error;
        if (isr & EMAC_ISR_BFCS)
                ++st->rx_bad_fcs;
        if (isr & EMAC_ISR_PTLE)
                ++st->rx_packet_too_long;
        if (isr & EMAC_ISR_ORE)
                ++st->rx_out_of_range;
        if (isr & EMAC_ISR_IRE)
                ++st->rx_in_range;
        if (isr & EMAC_ISR_SQE)
                ++st->tx_sqe;
        if (isr & EMAC_ISR_TE)
                ++st->tx_errors;

        spin_unlock(&dev->lock);

        return IRQ_HANDLED;
}

static struct net_device_stats *emac_stats(struct net_device *ndev)
{
        struct emac_instance *dev = netdev_priv(ndev);
        struct emac_stats *st = &dev->stats;
        struct emac_error_stats *est = &dev->estats;
        struct net_device_stats *nst = &ndev->stats;
        unsigned long flags;

        DBG2(dev, "stats" NL);

        /* Compute "legacy" statistics */
        spin_lock_irqsave(&dev->lock, flags);
        nst->rx_packets = (unsigned long)st->rx_packets;
        nst->rx_bytes = (unsigned long)st->rx_bytes;
        nst->tx_packets = (unsigned long)st->tx_packets;
        nst->tx_bytes = (unsigned long)st->tx_bytes;
        nst->rx_dropped = (unsigned long)(est->rx_dropped_oom +
                                          est->rx_dropped_error +
                                          est->rx_dropped_resize +
                                          est->rx_dropped_mtu);
        nst->tx_dropped = (unsigned long)est->tx_dropped;

        nst->rx_errors = (unsigned long)est->rx_bd_errors;
        nst->rx_fifo_errors = (unsigned long)(est->rx_bd_overrun +
                                              est->rx_fifo_overrun +
                                              est->rx_overrun);
        nst->rx_frame_errors = (unsigned long)(est->rx_bd_alignment_error +
                                               est->rx_alignment_error);
        nst->rx_crc_errors = (unsigned long)(est->rx_bd_bad_fcs +
                                             est->rx_bad_fcs);
        nst->rx_length_errors = (unsigned long)(est->rx_bd_runt_packet +