1/********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2016 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 **********************************************************************/ 19 20/*! \file octeon_mem_ops.h 21 * \brief Host Driver: Routines used to read/write Octeon memory. 22 */ 23 24#ifndef __OCTEON_MEM_OPS_H__ 25#define __OCTEON_MEM_OPS_H__ 26 27/** Read a 64-bit value from a BAR1 mapped core memory address. 28 * @param oct - pointer to the octeon device. 29 * @param core_addr - the address to read from. 30 * 31 * The range_idx gives the BAR1 index register for the range of address 32 * in which core_addr is mapped. 33 * 34 * @return 64-bit value read from Core memory 35 */ 36u64 octeon_read_device_mem64(struct octeon_device *oct, u64 core_addr); 37 38/** Read a 32-bit value from a BAR1 mapped core memory address. 39 * @param oct - pointer to the octeon device. 40 * @param core_addr - the address to read from. 41 * 42 * @return 32-bit value read from Core memory 43 */ 44u32 octeon_read_device_mem32(struct octeon_device *oct, u64 core_addr); 45 46/** Write a 32-bit value to a BAR1 mapped core memory address. 47 * @param oct - pointer to the octeon device. 48 * @param core_addr - the address to write to. 49 * @param val - 32-bit value to write. 50 */ 51void 52octeon_write_device_mem32(struct octeon_device *oct, 53 u64 core_addr, 54 u32 val); 55 56/** Read multiple bytes from Octeon memory. 57 */ 58void 59octeon_pci_read_core_mem(struct octeon_device *oct, 60 u64 coreaddr, 61 u8 *buf, 62 u32 len); 63 64/** Write multiple bytes into Octeon memory. 65 */ 66void 67octeon_pci_write_core_mem(struct octeon_device *oct, 68 u64 coreaddr, 69 const u8 *buf, 70 u32 len); 71 72#endif 73