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6#include <linux/io.h>
7#include <linux/clk.h>
8#include <linux/clkdev.h>
9#include <linux/delay.h>
10#include <linux/list.h>
11#include <linux/module.h>
12#include <linux/platform_device.h>
13#include <linux/pm_domain.h>
14#include <linux/pm_runtime.h>
15#include <linux/reset.h>
16#include <linux/of_address.h>
17#include <linux/of_platform.h>
18#include <linux/slab.h>
19#include <linux/sys_soc.h>
20#include <linux/iopoll.h>
21
22#include <linux/platform_data/ti-sysc.h>
23
24#include <dt-bindings/bus/ti-sysc.h>
25
26#define DIS_ISP BIT(2)
27#define DIS_IVA BIT(1)
28#define DIS_SGX BIT(0)
29
30#define SOC_FLAG(match, flag) { .machine = match, .data = (void *)(flag), }
31
32#define MAX_MODULE_SOFTRESET_WAIT 10000
33
34enum sysc_soc {
35 SOC_UNKNOWN,
36 SOC_2420,
37 SOC_2430,
38 SOC_3430,
39 SOC_3630,
40 SOC_4430,
41 SOC_4460,
42 SOC_4470,
43 SOC_5430,
44 SOC_AM3,
45 SOC_AM4,
46 SOC_DRA7,
47};
48
49struct sysc_address {
50 unsigned long base;
51 struct list_head node;
52};
53
54struct sysc_soc_info {
55 unsigned long general_purpose:1;
56 enum sysc_soc soc;
57 struct mutex list_lock;
58 struct list_head disabled_modules;
59};
60
61enum sysc_clocks {
62 SYSC_FCK,
63 SYSC_ICK,
64 SYSC_OPTFCK0,
65 SYSC_OPTFCK1,
66 SYSC_OPTFCK2,
67 SYSC_OPTFCK3,
68 SYSC_OPTFCK4,
69 SYSC_OPTFCK5,
70 SYSC_OPTFCK6,
71 SYSC_OPTFCK7,
72 SYSC_MAX_CLOCKS,
73};
74
75static struct sysc_soc_info *sysc_soc;
76static const char * const reg_names[] = { "rev", "sysc", "syss", };
77static const char * const clock_names[SYSC_MAX_CLOCKS] = {
78 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
79 "opt5", "opt6", "opt7",
80};
81
82#define SYSC_IDLEMODE_MASK 3
83#define SYSC_CLOCKACTIVITY_MASK 3
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116
117struct sysc {
118 struct device *dev;
119 u64 module_pa;
120 u32 module_size;
121 void __iomem *module_va;
122 int offsets[SYSC_MAX_REGS];
123 struct ti_sysc_module_data *mdata;
124 struct clk **clocks;
125 const char **clock_roles;
126 int nr_clocks;
127 struct reset_control *rsts;
128 const char *legacy_mode;
129 const struct sysc_capabilities *cap;
130 struct sysc_config cfg;
131 struct ti_sysc_cookie cookie;
132 const char *name;
133 u32 revision;
134 unsigned int reserved:1;
135 unsigned int enabled:1;
136 unsigned int needs_resume:1;
137 unsigned int child_needs_resume:1;
138 struct delayed_work idle_work;
139 void (*pre_reset_quirk)(struct sysc *sysc);
140 void (*post_reset_quirk)(struct sysc *sysc);
141 void (*reset_done_quirk)(struct sysc *sysc);
142 void (*module_enable_quirk)(struct sysc *sysc);
143 void (*module_disable_quirk)(struct sysc *sysc);
144 void (*module_unlock_quirk)(struct sysc *sysc);
145 void (*module_lock_quirk)(struct sysc *sysc);
146};
147
148static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
149 bool is_child);
150
151static void sysc_write(struct sysc *ddata, int offset, u32 value)
152{
153 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
154 writew_relaxed(value & 0xffff, ddata->module_va + offset);
155
156
157 if (ddata->offsets[SYSC_REVISION] >= 0 &&
158 offset == ddata->offsets[SYSC_REVISION]) {
159 u16 hi = value >> 16;
160
161 writew_relaxed(hi, ddata->module_va + offset + 4);
162 }
163
164 return;
165 }
166
167 writel_relaxed(value, ddata->module_va + offset);
168}
169
170static u32 sysc_read(struct sysc *ddata, int offset)
171{
172 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
173 u32 val;
174
175 val = readw_relaxed(ddata->module_va + offset);
176
177
178 if (ddata->offsets[SYSC_REVISION] >= 0 &&
179 offset == ddata->offsets[SYSC_REVISION]) {
180 u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
181
182 val |= tmp << 16;
183 }
184
185 return val;
186 }
187
188 return readl_relaxed(ddata->module_va + offset);
189}
190
191static bool sysc_opt_clks_needed(struct sysc *ddata)
192{
193 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
194}
195
196static u32 sysc_read_revision(struct sysc *ddata)
197{
198 int offset = ddata->offsets[SYSC_REVISION];
199
200 if (offset < 0)
201 return 0;
202
203 return sysc_read(ddata, offset);
204}
205
206static u32 sysc_read_sysconfig(struct sysc *ddata)
207{
208 int offset = ddata->offsets[SYSC_SYSCONFIG];
209
210 if (offset < 0)
211 return 0;
212
213 return sysc_read(ddata, offset);
214}
215
216static u32 sysc_read_sysstatus(struct sysc *ddata)
217{
218 int offset = ddata->offsets[SYSC_SYSSTATUS];
219
220 if (offset < 0)
221 return 0;
222
223 return sysc_read(ddata, offset);
224}
225
226
227static int sysc_wait_softreset(struct sysc *ddata)
228{
229 u32 sysc_mask, syss_done, rstval;
230 int syss_offset, error = 0;
231
232 if (ddata->cap->regbits->srst_shift < 0)
233 return 0;
234
235 syss_offset = ddata->offsets[SYSC_SYSSTATUS];
236 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
237
238 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
239 syss_done = 0;
240 else
241 syss_done = ddata->cfg.syss_mask;
242
243 if (syss_offset >= 0) {
244 error = readx_poll_timeout_atomic(sysc_read_sysstatus, ddata,
245 rstval, (rstval & ddata->cfg.syss_mask) ==
246 syss_done, 100, MAX_MODULE_SOFTRESET_WAIT);
247
248 } else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) {
249 error = readx_poll_timeout_atomic(sysc_read_sysconfig, ddata,
250 rstval, !(rstval & sysc_mask),
251 100, MAX_MODULE_SOFTRESET_WAIT);
252 }
253
254 return error;
255}
256
257static int sysc_add_named_clock_from_child(struct sysc *ddata,
258 const char *name,
259 const char *optfck_name)
260{
261 struct device_node *np = ddata->dev->of_node;
262 struct device_node *child;
263 struct clk_lookup *cl;
264 struct clk *clock;
265 const char *n;
266
267 if (name)
268 n = name;
269 else
270 n = optfck_name;
271
272
273 clock = of_clk_get_by_name(np, n);
274 if (!IS_ERR(clock)) {
275 clk_put(clock);
276
277 return 0;
278 }
279
280 child = of_get_next_available_child(np, NULL);
281 if (!child)
282 return -ENODEV;
283
284 clock = devm_get_clk_from_child(ddata->dev, child, name);
285 if (IS_ERR(clock))
286 return PTR_ERR(clock);
287
288
289
290
291
292
293 cl = kzalloc(sizeof(*cl), GFP_KERNEL);
294 if (!cl)
295 return -ENOMEM;
296
297 cl->con_id = n;
298 cl->dev_id = dev_name(ddata->dev);
299 cl->clk = clock;
300 clkdev_add(cl);
301
302 clk_put(clock);
303
304 return 0;
305}
306
307static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name)
308{
309 const char *optfck_name;
310 int error, index;
311
312 if (ddata->nr_clocks < SYSC_OPTFCK0)
313 index = SYSC_OPTFCK0;
314 else
315 index = ddata->nr_clocks;
316
317 if (name)
318 optfck_name = name;
319 else
320 optfck_name = clock_names[index];
321
322 error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
323 if (error)
324 return error;
325
326 ddata->clock_roles[index] = optfck_name;
327 ddata->nr_clocks++;
328
329 return 0;
330}
331
332static int sysc_get_one_clock(struct sysc *ddata, const char *name)
333{
334 int error, i, index = -ENODEV;
335
336 if (!strncmp(clock_names[SYSC_FCK], name, 3))
337 index = SYSC_FCK;
338 else if (!strncmp(clock_names[SYSC_ICK], name, 3))
339 index = SYSC_ICK;
340
341 if (index < 0) {
342 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
343 if (!ddata->clocks[i]) {
344 index = i;
345 break;
346 }
347 }
348 }
349
350 if (index < 0) {
351 dev_err(ddata->dev, "clock %s not added\n", name);
352 return index;
353 }
354
355 ddata->clocks[index] = devm_clk_get(ddata->dev, name);
356 if (IS_ERR(ddata->clocks[index])) {
357 dev_err(ddata->dev, "clock get error for %s: %li\n",
358 name, PTR_ERR(ddata->clocks[index]));
359
360 return PTR_ERR(ddata->clocks[index]);
361 }
362
363 error = clk_prepare(ddata->clocks[index]);
364 if (error) {
365 dev_err(ddata->dev, "clock prepare error for %s: %i\n",
366 name, error);
367
368 return error;
369 }
370
371 return 0;
372}
373
374static int sysc_get_clocks(struct sysc *ddata)
375{
376 struct device_node *np = ddata->dev->of_node;
377 struct property *prop;
378 const char *name;
379 int nr_fck = 0, nr_ick = 0, i, error = 0;
380
381 ddata->clock_roles = devm_kcalloc(ddata->dev,
382 SYSC_MAX_CLOCKS,
383 sizeof(*ddata->clock_roles),
384 GFP_KERNEL);
385 if (!ddata->clock_roles)
386 return -ENOMEM;
387
388 of_property_for_each_string(np, "clock-names", prop, name) {
389 if (!strncmp(clock_names[SYSC_FCK], name, 3))
390 nr_fck++;
391 if (!strncmp(clock_names[SYSC_ICK], name, 3))
392 nr_ick++;
393 ddata->clock_roles[ddata->nr_clocks] = name;
394 ddata->nr_clocks++;
395 }
396
397 if (ddata->nr_clocks < 1)
398 return 0;
399
400 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
401 error = sysc_init_ext_opt_clock(ddata, NULL);
402 if (error)
403 return error;
404 }
405
406 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
407 dev_err(ddata->dev, "too many clocks for %pOF\n", np);
408
409 return -EINVAL;
410 }
411
412 if (nr_fck > 1 || nr_ick > 1) {
413 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
414
415 return -EINVAL;
416 }
417
418
419 if (!nr_fck)
420 ddata->nr_clocks++;
421 if (!nr_ick)
422 ddata->nr_clocks++;
423
424 ddata->clocks = devm_kcalloc(ddata->dev,
425 ddata->nr_clocks, sizeof(*ddata->clocks),
426 GFP_KERNEL);
427 if (!ddata->clocks)
428 return -ENOMEM;
429
430 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
431 const char *name = ddata->clock_roles[i];
432
433 if (!name)
434 continue;
435
436 error = sysc_get_one_clock(ddata, name);
437 if (error)
438 return error;
439 }
440
441 return 0;
442}
443
444static int sysc_enable_main_clocks(struct sysc *ddata)
445{
446 struct clk *clock;
447 int i, error;
448
449 if (!ddata->clocks)
450 return 0;
451
452 for (i = 0; i < SYSC_OPTFCK0; i++) {
453 clock = ddata->clocks[i];
454
455
456 if (IS_ERR_OR_NULL(clock))
457 continue;
458
459 error = clk_enable(clock);
460 if (error)
461 goto err_disable;
462 }
463
464 return 0;
465
466err_disable:
467 for (i--; i >= 0; i--) {
468 clock = ddata->clocks[i];
469
470
471 if (IS_ERR_OR_NULL(clock))
472 continue;
473
474 clk_disable(clock);
475 }
476
477 return error;
478}
479
480static void sysc_disable_main_clocks(struct sysc *ddata)
481{
482 struct clk *clock;
483 int i;
484
485 if (!ddata->clocks)
486 return;
487
488 for (i = 0; i < SYSC_OPTFCK0; i++) {
489 clock = ddata->clocks[i];
490 if (IS_ERR_OR_NULL(clock))
491 continue;
492
493 clk_disable(clock);
494 }
495}
496
497static int sysc_enable_opt_clocks(struct sysc *ddata)
498{
499 struct clk *clock;
500 int i, error;
501
502 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
503 return 0;
504
505 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
506 clock = ddata->clocks[i];
507
508
509 if (IS_ERR_OR_NULL(clock))
510 return 0;
511
512 error = clk_enable(clock);
513 if (error)
514 goto err_disable;
515 }
516
517 return 0;
518
519err_disable:
520 for (i--; i >= 0; i--) {
521 clock = ddata->clocks[i];
522 if (IS_ERR_OR_NULL(clock))
523 continue;
524
525 clk_disable(clock);
526 }
527
528 return error;
529}
530
531static void sysc_disable_opt_clocks(struct sysc *ddata)
532{
533 struct clk *clock;
534 int i;
535
536 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
537 return;
538
539 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
540 clock = ddata->clocks[i];
541
542
543 if (IS_ERR_OR_NULL(clock))
544 return;
545
546 clk_disable(clock);
547 }
548}
549
550static void sysc_clkdm_deny_idle(struct sysc *ddata)
551{
552 struct ti_sysc_platform_data *pdata;
553
554 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
555 return;
556
557 pdata = dev_get_platdata(ddata->dev);
558 if (pdata && pdata->clkdm_deny_idle)
559 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie);
560}
561
562static void sysc_clkdm_allow_idle(struct sysc *ddata)
563{
564 struct ti_sysc_platform_data *pdata;
565
566 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
567 return;
568
569 pdata = dev_get_platdata(ddata->dev);
570 if (pdata && pdata->clkdm_allow_idle)
571 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie);
572}
573
574
575
576
577
578
579
580static int sysc_init_resets(struct sysc *ddata)
581{
582 ddata->rsts =
583 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl");
584
585 return PTR_ERR_OR_ZERO(ddata->rsts);
586}
587
588
589
590
591
592
593
594
595
596
597static int sysc_parse_and_check_child_range(struct sysc *ddata)
598{
599 struct device_node *np = ddata->dev->of_node;
600 const __be32 *ranges;
601 u32 nr_addr, nr_size;
602 int len, error;
603
604 ranges = of_get_property(np, "ranges", &len);
605 if (!ranges) {
606 dev_err(ddata->dev, "missing ranges for %pOF\n", np);
607
608 return -ENOENT;
609 }
610
611 len /= sizeof(*ranges);
612
613 if (len < 3) {
614 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np);
615
616 return -EINVAL;
617 }
618
619 error = of_property_read_u32(np, "#address-cells", &nr_addr);
620 if (error)
621 return -ENOENT;
622
623 error = of_property_read_u32(np, "#size-cells", &nr_size);
624 if (error)
625 return -ENOENT;
626
627 if (nr_addr != 1 || nr_size != 1) {
628 dev_err(ddata->dev, "invalid ranges for %pOF\n", np);
629
630 return -EINVAL;
631 }
632
633 ranges++;
634 ddata->module_pa = of_translate_address(np, ranges++);
635 ddata->module_size = be32_to_cpup(ranges);
636
637 return 0;
638}
639
640
641static struct resource early_bus_ranges[] = {
642
643 { .start = 0x44c00000, .end = 0x44c00000 + 0x300000, },
644
645 { .start = 0x4a000000, .end = 0x4a000000 + 0x300000, },
646
647 { .start = 0x4a300000, .end = 0x4a300000 + 0x30000, },
648
649 { .start = 0x4ae00000, .end = 0x4ae00000 + 0x30000, },
650};
651
652static atomic_t sysc_defer = ATOMIC_INIT(10);
653
654
655
656
657
658
659
660
661
662static int sysc_defer_non_critical(struct sysc *ddata)
663{
664 struct resource *res;
665 int i;
666
667 if (!atomic_read(&sysc_defer))
668 return 0;
669
670 for (i = 0; i < ARRAY_SIZE(early_bus_ranges); i++) {
671 res = &early_bus_ranges[i];
672 if (ddata->module_pa >= res->start &&
673 ddata->module_pa <= res->end) {
674 atomic_set(&sysc_defer, 0);
675
676 return 0;
677 }
678 }
679
680 atomic_dec_if_positive(&sysc_defer);
681
682 return -EPROBE_DEFER;
683}
684
685static struct device_node *stdout_path;
686
687static void sysc_init_stdout_path(struct sysc *ddata)
688{
689 struct device_node *np = NULL;
690 const char *uart;
691
692 if (IS_ERR(stdout_path))
693 return;
694
695 if (stdout_path)
696 return;
697
698 np = of_find_node_by_path("/chosen");
699 if (!np)
700 goto err;
701
702 uart = of_get_property(np, "stdout-path", NULL);
703 if (!uart)
704 goto err;
705
706 np = of_find_node_by_path(uart);
707 if (!np)
708 goto err;
709
710 stdout_path = np;
711
712 return;
713
714err:
715 stdout_path = ERR_PTR(-ENODEV);
716}
717
718static void sysc_check_quirk_stdout(struct sysc *ddata,
719 struct device_node *np)
720{
721 sysc_init_stdout_path(ddata);
722 if (np != stdout_path)
723 return;
724
725 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
726 SYSC_QUIRK_NO_RESET_ON_INIT;
727}
728
729
730
731
732
733
734
735
736
737
738static void sysc_check_one_child(struct sysc *ddata,
739 struct device_node *np)
740{
741 const char *name;
742
743 name = of_get_property(np, "ti,hwmods", NULL);
744 if (name && !of_device_is_compatible(np, "ti,sysc"))
745 dev_warn(ddata->dev, "really a child ti,hwmods property?");
746
747 sysc_check_quirk_stdout(ddata, np);
748 sysc_parse_dts_quirks(ddata, np, true);
749}
750
751static void sysc_check_children(struct sysc *ddata)
752{
753 struct device_node *child;
754
755 for_each_child_of_node(ddata->dev->of_node, child)
756 sysc_check_one_child(ddata, child);
757}
758
759
760
761
762
763
764
765static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
766{
767 if (resource_size(res) == 8)
768 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
769}
770
771
772
773
774
775
776static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
777{
778 struct resource *res;
779 const char *name;
780
781 switch (reg) {
782 case SYSC_REVISION:
783 case SYSC_SYSCONFIG:
784 case SYSC_SYSSTATUS:
785 name = reg_names[reg];
786 break;
787 default:
788 return -EINVAL;
789 }
790
791 res = platform_get_resource_byname(to_platform_device(ddata->dev),
792 IORESOURCE_MEM, name);
793 if (!res) {
794 ddata->offsets[reg] = -ENODEV;
795
796 return 0;
797 }
798
799 ddata->offsets[reg] = res->start - ddata->module_pa;
800 if (reg == SYSC_REVISION)
801 sysc_check_quirk_16bit(ddata, res);
802
803 return 0;
804}
805
806static int sysc_parse_registers(struct sysc *ddata)
807{
808 int i, error;
809
810 for (i = 0; i < SYSC_MAX_REGS; i++) {
811 error = sysc_parse_one(ddata, i);
812 if (error)
813 return error;
814 }
815
816 return 0;
817}
818
819
820
821
822
823static int sysc_check_registers(struct sysc *ddata)
824{
825 int i, j, nr_regs = 0, nr_matches = 0;
826
827 for (i = 0; i < SYSC_MAX_REGS; i++) {
828 if (ddata->offsets[i] < 0)
829 continue;
830
831 if (ddata->offsets[i] > (ddata->module_size - 4)) {
832 dev_err(ddata->dev, "register outside module range");
833
834 return -EINVAL;
835 }
836
837 for (j = 0; j < SYSC_MAX_REGS; j++) {
838 if (ddata->offsets[j] < 0)
839 continue;
840
841 if (ddata->offsets[i] == ddata->offsets[j])
842 nr_matches++;
843 }
844 nr_regs++;
845 }
846
847 if (nr_matches > nr_regs) {
848 dev_err(ddata->dev, "overlapping registers: (%i/%i)",
849 nr_regs, nr_matches);
850
851 return -EINVAL;
852 }
853
854 return 0;
855}
856
857
858
859
860
861
862
863
864
865
866
867
868static int sysc_ioremap(struct sysc *ddata)
869{
870 int size;
871
872 if (ddata->offsets[SYSC_REVISION] < 0 &&
873 ddata->offsets[SYSC_SYSCONFIG] < 0 &&
874 ddata->offsets[SYSC_SYSSTATUS] < 0) {
875 size = ddata->module_size;
876 } else {
877 size = max3(ddata->offsets[SYSC_REVISION],
878 ddata->offsets[SYSC_SYSCONFIG],
879 ddata->offsets[SYSC_SYSSTATUS]);
880
881 if (size < SZ_1K)
882 size = SZ_1K;
883
884 if ((size + sizeof(u32)) > ddata->module_size)
885 size = ddata->module_size;
886 }
887
888 ddata->module_va = devm_ioremap(ddata->dev,
889 ddata->module_pa,
890 size + sizeof(u32));
891 if (!ddata->module_va)
892 return -EIO;
893
894 return 0;
895}
896
897
898
899
900
901static int sysc_map_and_check_registers(struct sysc *ddata)
902{
903 struct device_node *np = ddata->dev->of_node;
904 int error;
905
906 error = sysc_parse_and_check_child_range(ddata);
907 if (error)
908 return error;
909
910 error = sysc_defer_non_critical(ddata);
911 if (error)
912 return error;
913
914 sysc_check_children(ddata);
915
916 if (!of_get_property(np, "reg", NULL))
917 return 0;
918
919 error = sysc_parse_registers(ddata);
920 if (error)
921 return error;
922
923 error = sysc_ioremap(ddata);
924 if (error)
925 return error;
926
927 error = sysc_check_registers(ddata);
928 if (error)
929 return error;
930
931 return 0;
932}
933
934
935
936
937
938
939static int sysc_show_rev(char *bufp, struct sysc *ddata)
940{
941 int len;
942
943 if (ddata->offsets[SYSC_REVISION] < 0)
944 return sprintf(bufp, ":NA");
945
946 len = sprintf(bufp, ":%08x", ddata->revision);
947
948 return len;
949}
950
951static int sysc_show_reg(struct sysc *ddata,
952 char *bufp, enum sysc_registers reg)
953{
954 if (ddata->offsets[reg] < 0)
955 return sprintf(bufp, ":NA");
956
957 return sprintf(bufp, ":%x", ddata->offsets[reg]);
958}
959
960static int sysc_show_name(char *bufp, struct sysc *ddata)
961{
962 if (!ddata->name)
963 return 0;
964
965 return sprintf(bufp, ":%s", ddata->name);
966}
967
968
969
970
971
972static void sysc_show_registers(struct sysc *ddata)
973{
974 char buf[128];
975 char *bufp = buf;
976 int i;
977
978 for (i = 0; i < SYSC_MAX_REGS; i++)
979 bufp += sysc_show_reg(ddata, bufp, i);
980
981 bufp += sysc_show_rev(bufp, ddata);
982 bufp += sysc_show_name(bufp, ddata);
983
984 dev_dbg(ddata->dev, "%llx:%x%s\n",
985 ddata->module_pa, ddata->module_size,
986 buf);
987}
988
989
990
991
992
993
994static void sysc_write_sysconfig(struct sysc *ddata, u32 value)
995{
996 if (ddata->module_unlock_quirk)
997 ddata->module_unlock_quirk(ddata);
998
999 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value);
1000
1001 if (ddata->module_lock_quirk)
1002 ddata->module_lock_quirk(ddata);
1003}
1004
1005#define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1)
1006#define SYSC_CLOCACT_ICK 2
1007
1008
1009static int sysc_enable_module(struct device *dev)
1010{
1011 struct sysc *ddata;
1012 const struct sysc_regbits *regbits;
1013 u32 reg, idlemodes, best_mode;
1014 int error;
1015
1016 ddata = dev_get_drvdata(dev);
1017
1018
1019
1020
1021
1022 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) {
1023 error = sysc_enable_opt_clocks(ddata);
1024 if (error) {
1025 dev_err(ddata->dev,
1026 "Optional clocks failed for enable: %i\n",
1027 error);
1028 return error;
1029 }
1030 }
1031
1032
1033
1034
1035 if (!(ddata->cfg.quirks & SYSC_MODULE_QUIRK_ENA_RESETDONE)) {
1036 error = sysc_wait_softreset(ddata);
1037 if (error)
1038 dev_warn(ddata->dev, "OCP softreset timed out\n");
1039 }
1040 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET)
1041 sysc_disable_opt_clocks(ddata);
1042
1043
1044
1045
1046
1047
1048 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
1049 return 0;
1050
1051 regbits = ddata->cap->regbits;
1052 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1053
1054
1055
1056
1057
1058
1059 if (regbits->clkact_shift >= 0 &&
1060 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT))
1061 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift;
1062
1063
1064 idlemodes = ddata->cfg.sidlemodes;
1065 if (!idlemodes || regbits->sidle_shift < 0)
1066 goto set_midle;
1067
1068 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE |
1069 SYSC_QUIRK_SWSUP_SIDLE_ACT)) {
1070 best_mode = SYSC_IDLE_NO;
1071 } else {
1072 best_mode = fls(ddata->cfg.sidlemodes) - 1;
1073 if (best_mode > SYSC_IDLE_MASK) {
1074 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1075 return -EINVAL;
1076 }
1077
1078
1079 if (regbits->enwkup_shift >= 0 &&
1080 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
1081 reg |= BIT(regbits->enwkup_shift);
1082 }
1083
1084 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1085 reg |= best_mode << regbits->sidle_shift;
1086 sysc_write_sysconfig(ddata, reg);
1087
1088set_midle:
1089
1090 idlemodes = ddata->cfg.midlemodes;
1091 if (!idlemodes || regbits->midle_shift < 0)
1092 goto set_autoidle;
1093
1094 best_mode = fls(ddata->cfg.midlemodes) - 1;
1095 if (best_mode > SYSC_IDLE_MASK) {
1096 dev_err(dev, "%s: invalid midlemode\n", __func__);
1097 return -EINVAL;
1098 }
1099
1100 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
1101 best_mode = SYSC_IDLE_NO;
1102
1103 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1104 reg |= best_mode << regbits->midle_shift;
1105 sysc_write_sysconfig(ddata, reg);
1106
1107set_autoidle:
1108
1109 if (regbits->autoidle_shift >= 0 &&
1110 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
1111 reg |= 1 << regbits->autoidle_shift;
1112 sysc_write_sysconfig(ddata, reg);
1113 }
1114
1115
1116 sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1117
1118 if (ddata->module_enable_quirk)
1119 ddata->module_enable_quirk(ddata);
1120
1121 return 0;
1122}
1123
1124static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
1125{
1126 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
1127 *best_mode = SYSC_IDLE_SMART_WKUP;
1128 else if (idlemodes & BIT(SYSC_IDLE_SMART))
1129 *best_mode = SYSC_IDLE_SMART;
1130 else if (idlemodes & BIT(SYSC_IDLE_FORCE))
1131 *best_mode = SYSC_IDLE_FORCE;
1132 else
1133 return -EINVAL;
1134
1135 return 0;
1136}
1137
1138
1139static int sysc_disable_module(struct device *dev)
1140{
1141 struct sysc *ddata;
1142 const struct sysc_regbits *regbits;
1143 u32 reg, idlemodes, best_mode;
1144 int ret;
1145
1146 ddata = dev_get_drvdata(dev);
1147 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
1148 return 0;
1149
1150 if (ddata->module_disable_quirk)
1151 ddata->module_disable_quirk(ddata);
1152
1153 regbits = ddata->cap->regbits;
1154 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1155
1156
1157 idlemodes = ddata->cfg.midlemodes;
1158 if (!idlemodes || regbits->midle_shift < 0)
1159 goto set_sidle;
1160
1161 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1162 if (ret) {
1163 dev_err(dev, "%s: invalid midlemode\n", __func__);
1164 return ret;
1165 }
1166
1167 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) ||
1168 ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY))
1169 best_mode = SYSC_IDLE_FORCE;
1170
1171 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1172 reg |= best_mode << regbits->midle_shift;
1173 sysc_write_sysconfig(ddata, reg);
1174
1175set_sidle:
1176
1177 idlemodes = ddata->cfg.sidlemodes;
1178 if (!idlemodes || regbits->sidle_shift < 0)
1179 return 0;
1180
1181 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) {
1182 best_mode = SYSC_IDLE_FORCE;
1183 } else {
1184 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1185 if (ret) {
1186 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1187 return ret;
1188 }
1189 }
1190
1191 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1192 reg |= best_mode << regbits->sidle_shift;
1193 if (regbits->autoidle_shift >= 0 &&
1194 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
1195 reg |= 1 << regbits->autoidle_shift;
1196 sysc_write_sysconfig(ddata, reg);
1197
1198
1199 sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1200
1201 return 0;
1202}
1203
1204static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
1205 struct sysc *ddata)
1206{
1207 struct ti_sysc_platform_data *pdata;
1208 int error;
1209
1210 pdata = dev_get_platdata(ddata->dev);
1211 if (!pdata)
1212 return 0;
1213
1214 if (!pdata->idle_module)
1215 return -ENODEV;
1216
1217 error = pdata->idle_module(dev, &ddata->cookie);
1218 if (error)
1219 dev_err(dev, "%s: could not idle: %i\n",
1220 __func__, error);
1221
1222 reset_control_assert(ddata->rsts);
1223
1224 return 0;
1225}
1226
1227static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
1228 struct sysc *ddata)
1229{
1230 struct ti_sysc_platform_data *pdata;
1231 int error;
1232
1233 pdata = dev_get_platdata(ddata->dev);
1234 if (!pdata)
1235 return 0;
1236
1237 if (!pdata->enable_module)
1238 return -ENODEV;
1239
1240 error = pdata->enable_module(dev, &ddata->cookie);
1241 if (error)
1242 dev_err(dev, "%s: could not enable: %i\n",
1243 __func__, error);
1244
1245 reset_control_deassert(ddata->rsts);
1246
1247 return 0;
1248}
1249
1250static int __maybe_unused sysc_runtime_suspend(struct device *dev)
1251{
1252 struct sysc *ddata;
1253 int error = 0;
1254
1255 ddata = dev_get_drvdata(dev);
1256
1257 if (!ddata->enabled)
1258 return 0;
1259
1260 sysc_clkdm_deny_idle(ddata);
1261
1262 if (ddata->legacy_mode) {
1263 error = sysc_runtime_suspend_legacy(dev, ddata);
1264 if (error)
1265 goto err_allow_idle;
1266 } else {
1267 error = sysc_disable_module(dev);
1268 if (error)
1269 goto err_allow_idle;
1270 }
1271
1272 sysc_disable_main_clocks(ddata);
1273
1274 if (sysc_opt_clks_needed(ddata))
1275 sysc_disable_opt_clocks(ddata);
1276
1277 ddata->enabled = false;
1278
1279err_allow_idle:
1280 sysc_clkdm_allow_idle(ddata);
1281
1282 reset_control_assert(ddata->rsts);
1283
1284 return error;
1285}
1286
1287static int __maybe_unused sysc_runtime_resume(struct device *dev)
1288{
1289 struct sysc *ddata;
1290 int error = 0;
1291
1292 ddata = dev_get_drvdata(dev);
1293
1294 if (ddata->enabled)
1295 return 0;
1296
1297
1298 sysc_clkdm_deny_idle(ddata);
1299
1300 if (sysc_opt_clks_needed(ddata)) {
1301 error = sysc_enable_opt_clocks(ddata);
1302 if (error)
1303 goto err_allow_idle;
1304 }
1305
1306 error = sysc_enable_main_clocks(ddata);
1307 if (error)
1308 goto err_opt_clocks;
1309
1310 reset_control_deassert(ddata->rsts);
1311
1312 if (ddata->legacy_mode) {
1313 error = sysc_runtime_resume_legacy(dev, ddata);
1314 if (error)
1315 goto err_main_clocks;
1316 } else {
1317 error = sysc_enable_module(dev);
1318 if (error)
1319 goto err_main_clocks;
1320 }
1321
1322 ddata->enabled = true;
1323
1324 sysc_clkdm_allow_idle(ddata);
1325
1326 return 0;
1327
1328err_main_clocks:
1329 sysc_disable_main_clocks(ddata);
1330err_opt_clocks:
1331 if (sysc_opt_clks_needed(ddata))
1332 sysc_disable_opt_clocks(ddata);
1333err_allow_idle:
1334 sysc_clkdm_allow_idle(ddata);
1335
1336 return error;
1337}
1338
1339static int sysc_reinit_module(struct sysc *ddata, bool leave_enabled)
1340{
1341 struct device *dev = ddata->dev;
1342 int error;
1343
1344
1345 if (ddata->enabled) {
1346 error = sysc_runtime_suspend(dev);
1347 if (error)
1348 dev_warn(dev, "reinit suspend failed: %i\n", error);
1349 }
1350
1351
1352 error = sysc_runtime_resume(dev);
1353 if (error)
1354 dev_warn(dev, "reinit resume failed: %i\n", error);
1355
1356 if (leave_enabled)
1357 return error;
1358
1359
1360 error = sysc_runtime_suspend(dev);
1361 if (error)
1362 dev_warn(dev, "reinit suspend failed: %i\n", error);
1363
1364 return error;
1365}
1366
1367static int __maybe_unused sysc_noirq_suspend(struct device *dev)
1368{
1369 struct sysc *ddata;
1370
1371 ddata = dev_get_drvdata(dev);
1372
1373 if (ddata->cfg.quirks &
1374 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
1375 return 0;
1376
1377 if (!ddata->enabled)
1378 return 0;
1379
1380 ddata->needs_resume = 1;
1381
1382 return sysc_runtime_suspend(dev);
1383}
1384
1385static int __maybe_unused sysc_noirq_resume(struct device *dev)
1386{
1387 struct sysc *ddata;
1388 int error = 0;
1389
1390 ddata = dev_get_drvdata(dev);
1391
1392 if (ddata->cfg.quirks &
1393 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
1394 return 0;
1395
1396 if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_RESUME) {
1397 error = sysc_reinit_module(ddata, ddata->needs_resume);
1398 if (error)
1399 dev_warn(dev, "noirq_resume failed: %i\n", error);
1400 } else if (ddata->needs_resume) {
1401 error = sysc_runtime_resume(dev);
1402 if (error)
1403 dev_warn(dev, "noirq_resume failed: %i\n", error);
1404 }
1405
1406 ddata->needs_resume = 0;
1407
1408 return error;
1409}
1410
1411static const struct dev_pm_ops sysc_pm_ops = {
1412 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
1413 SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
1414 sysc_runtime_resume,
1415 NULL)
1416};
1417
1418
1419struct sysc_revision_quirk {
1420 const char *name;
1421 u32 base;
1422 int rev_offset;
1423 int sysc_offset;
1424 int syss_offset;
1425 u32 revision;
1426 u32 revision_mask;
1427 u32 quirks;
1428};
1429
1430#define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \
1431 optrev_val, optrevmask, optquirkmask) \
1432 { \
1433 .name = (optname), \
1434 .base = (optbase), \
1435 .rev_offset = (optrev), \
1436 .sysc_offset = (optsysc), \
1437 .syss_offset = (optsyss), \
1438 .revision = (optrev_val), \
1439 .revision_mask = (optrevmask), \
1440 .quirks = (optquirkmask), \
1441 }
1442
1443static const struct sysc_revision_quirk sysc_revision_quirks[] = {
1444
1445 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
1446 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET),
1447 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
1448 SYSC_QUIRK_LEGACY_IDLE),
1449 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff,
1450 SYSC_QUIRK_LEGACY_IDLE),
1451 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff,
1452 SYSC_QUIRK_LEGACY_IDLE),
1453 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff,
1454 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1455 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
1456 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1457
1458 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
1459 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1460 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
1461 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1462
1463
1464 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff,
1465 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
1466 SYSC_QUIRK_SWSUP_SIDLE),
1467
1468
1469 SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff,
1470 SYSC_MODULE_QUIRK_AESS),
1471 SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
1472 SYSC_QUIRK_CLKDM_NOAUTO),
1473 SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
1474 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1475 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff,
1476 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1477 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff,
1478 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1479 SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
1480 SYSC_QUIRK_CLKDM_NOAUTO),
1481 SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
1482 SYSC_QUIRK_CLKDM_NOAUTO),
1483 SYSC_QUIRK("gpmc", 0, 0, 0x10, 0x14, 0x00000060, 0xffffffff,
1484 SYSC_QUIRK_GPMC_DEBUG),
1485 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff,
1486 SYSC_QUIRK_OPT_CLKS_NEEDED),
1487 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
1488 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1489 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
1490 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1491 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff,
1492 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1493 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff,
1494 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1495 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff,
1496 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1497 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0,
1498 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1499 SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0),
1500 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff,
1501 SYSC_MODULE_QUIRK_SGX),
1502 SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff,
1503 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1504 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0,
1505 SYSC_MODULE_QUIRK_RTC_UNLOCK),
1506 SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff,
1507 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1508 SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff,
1509 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1510 SYSC_QUIRK("sata", 0, 0xfc, 0x1100, -ENODEV, 0x5e412000, 0xffffffff,
1511 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1512 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff,
1513 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1514 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff,
1515 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1516 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
1517 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1518 SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff,
1519 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY |
1520 SYSC_QUIRK_REINIT_ON_RESUME),
1521 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1522 SYSC_MODULE_QUIRK_WDT),
1523
1524 SYSC_QUIRK("pruss", 0, 0x26000, 0x26004, -ENODEV, 0x47000000, 0xff000000,
1525 SYSC_MODULE_QUIRK_PRUSS),
1526
1527 SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1528 SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE),
1529
1530#ifdef DEBUG
1531 SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0),
1532 SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0),
1533 SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0),
1534 SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1535 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
1536 0xffff00f0, 0),
1537 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0),
1538 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0),
1539 SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1540 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1541 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0),
1542 SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0),
1543 SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1544 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1545 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1546 SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1547 SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0),
1548 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1549 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1550 SYSC_QUIRK("elm", 0x48080000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0),
1551 SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x40441403, 0xffff0fff, 0),
1552 SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x50440500, 0xffffffff, 0),
1553 SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0),
1554 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0),
1555 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0),
1556 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0),
1557 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
1558 SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0),
1559 SYSC_QUIRK("keypad", 0x4a31c000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0),
1560 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff, 0),
1561 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0),
1562 SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0),
1563 SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0),
1564 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
1565 SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0),
1566 SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0),
1567 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
1568 SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0),
1569 SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0),
1570 SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0),
1571 SYSC_QUIRK("pcie", 0x51000000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0),
1572 SYSC_QUIRK("pcie", 0x51800000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0),
1573 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0),
1574 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0),
1575 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0),
1576 SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1577 SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1578 SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1579 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0),
1580 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0),
1581 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0),
1582 SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0),
1583 SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0),
1584 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
1585 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
1586 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0),
1587 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0),
1588 SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0),
1589 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0),
1590 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000013, 0xffffffff, 0),
1591 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 0),
1592
1593 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff, 0),
1594 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff, 0),
1595 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000040, 0xffffffff, 0),
1596 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000011, 0xffffffff, 0),
1597 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0),
1598 SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0),
1599 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
1600 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
1601 SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0),
1602 SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0),
1603#endif
1604};
1605
1606
1607
1608
1609
1610static void sysc_init_early_quirks(struct sysc *ddata)
1611{
1612 const struct sysc_revision_quirk *q;
1613 int i;
1614
1615 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1616 q = &sysc_revision_quirks[i];
1617
1618 if (!q->base)
1619 continue;
1620
1621 if (q->base != ddata->module_pa)
1622 continue;
1623
1624 if (q->rev_offset != ddata->offsets[SYSC_REVISION])
1625 continue;
1626
1627 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1628 continue;
1629
1630 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1631 continue;
1632
1633 ddata->name = q->name;
1634 ddata->cfg.quirks |= q->quirks;
1635 }
1636}
1637
1638
1639static void sysc_init_revision_quirks(struct sysc *ddata)
1640{
1641 const struct sysc_revision_quirk *q;
1642 int i;
1643
1644 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1645 q = &sysc_revision_quirks[i];
1646
1647 if (q->base && q->base != ddata->module_pa)
1648 continue;
1649
1650 if (q->rev_offset != ddata->offsets[SYSC_REVISION])
1651 continue;
1652
1653 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1654 continue;
1655
1656 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1657 continue;
1658
1659 if (q->revision == ddata->revision ||
1660 (q->revision & q->revision_mask) ==
1661 (ddata->revision & q->revision_mask)) {
1662 ddata->name = q->name;
1663 ddata->cfg.quirks |= q->quirks;
1664 }
1665 }
1666}
1667
1668
1669
1670
1671
1672
1673static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset,
1674 bool disable)
1675{
1676 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
1677 const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1);
1678 int manager_count;
1679 bool framedonetv_irq = true;
1680 u32 val, irq_mask = 0;
1681
1682 switch (sysc_soc->soc) {
1683 case SOC_2420 ... SOC_3630:
1684 manager_count = 2;
1685 framedonetv_irq = false;
1686 break;
1687 case SOC_4430 ... SOC_4470:
1688 manager_count = 3;
1689 break;
1690 case SOC_5430:
1691 case SOC_DRA7:
1692 manager_count = 4;
1693 break;
1694 case SOC_AM4:
1695 manager_count = 1;
1696 framedonetv_irq = false;
1697 break;
1698 case SOC_UNKNOWN:
1699 default:
1700 return 0;
1701 }
1702
1703
1704 devm_iounmap(ddata->dev, ddata->module_va);
1705 ddata->module_va = devm_ioremap(ddata->dev,
1706 ddata->module_pa,
1707 ddata->module_size);
1708 if (!ddata->module_va)
1709 return -EIO;
1710
1711
1712 val = sysc_read(ddata, dispc_offset + 0x40);
1713 lcd_en = val & lcd_en_mask;
1714 digit_en = val & digit_en_mask;
1715 if (lcd_en)
1716 irq_mask |= BIT(0);
1717 if (digit_en) {
1718 if (framedonetv_irq)
1719 irq_mask |= BIT(24);
1720 else
1721 irq_mask |= BIT(2) | BIT(3);
1722 }
1723 if (disable & (lcd_en | digit_en))
1724 sysc_write(ddata, dispc_offset + 0x40,
1725 val & ~(lcd_en_mask | digit_en_mask));
1726
1727 if (manager_count <= 2)
1728 return irq_mask;
1729
1730
1731 val = sysc_read(ddata, dispc_offset + 0x238);
1732 lcd2_en = val & lcd_en_mask;
1733 if (lcd2_en)
1734 irq_mask |= BIT(22);
1735 if (disable && lcd2_en)
1736 sysc_write(ddata, dispc_offset + 0x238,
1737 val & ~lcd_en_mask);
1738
1739 if (manager_count <= 3)
1740 return irq_mask;
1741
1742
1743 val = sysc_read(ddata, dispc_offset + 0x848);
1744 lcd3_en = val & lcd_en_mask;
1745 if (lcd3_en)
1746 irq_mask |= BIT(30);
1747 if (disable && lcd3_en)
1748 sysc_write(ddata, dispc_offset + 0x848,
1749 val & ~lcd_en_mask);
1750
1751 return irq_mask;
1752}
1753
1754
1755static void sysc_pre_reset_quirk_dss(struct sysc *ddata)
1756{
1757 const int dispc_offset = 0x1000;
1758 int error;
1759 u32 irq_mask, val;
1760
1761
1762 irq_mask = sysc_quirk_dispc(ddata, dispc_offset, false);
1763 if (!irq_mask)
1764 return;
1765
1766
1767 sysc_write(ddata, dispc_offset + 0x18, irq_mask);
1768
1769
1770 val = sysc_quirk_dispc(ddata, dispc_offset, true);
1771
1772
1773 error = readl_poll_timeout(ddata->module_va + dispc_offset + 0x18,
1774 val, val != irq_mask, 100, 50);
1775 if (error)
1776 dev_warn(ddata->dev, "%s: timed out %08x !+ %08x\n",
1777 __func__, val, irq_mask);
1778
1779 if (sysc_soc->soc == SOC_3430) {
1780
1781 sysc_write(ddata, 0x44, 0);
1782
1783
1784 sysc_write(ddata, 0x48, 0);
1785 }
1786
1787
1788 sysc_write(ddata, 0x40, 0);
1789}
1790
1791
1792static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata)
1793{
1794 int offset = 0x0c;
1795 u16 val;
1796
1797 val = sysc_read(ddata, offset);
1798 val |= BIT(5);
1799 sysc_write(ddata, offset, val);
1800}
1801
1802
1803static void sysc_module_enable_quirk_aess(struct sysc *ddata)
1804{
1805 int offset = 0x7c;
1806
1807 sysc_write(ddata, offset, 1);
1808}
1809
1810
1811static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable)
1812{
1813 int offset;
1814 u16 val;
1815
1816
1817 if ((ddata->revision & 0xffffff00) == 0x001f0000)
1818 offset = 0x24;
1819 else
1820 offset = 0xa4;
1821
1822
1823 val = sysc_read(ddata, offset);
1824 if (enable)
1825 val |= BIT(15);
1826 else
1827 val &= ~BIT(15);
1828 sysc_write(ddata, offset, val);
1829}
1830
1831static void sysc_pre_reset_quirk_i2c(struct sysc *ddata)
1832{
1833 sysc_clk_quirk_i2c(ddata, false);
1834}
1835
1836static void sysc_post_reset_quirk_i2c(struct sysc *ddata)
1837{
1838 sysc_clk_quirk_i2c(ddata, true);
1839}
1840
1841
1842static void sysc_quirk_rtc(struct sysc *ddata, bool lock)
1843{
1844 u32 val, kick0_val = 0, kick1_val = 0;
1845 unsigned long flags;
1846 int error;
1847
1848 if (!lock) {
1849 kick0_val = 0x83e70b13;
1850 kick1_val = 0x95a4f1e0;
1851 }
1852
1853 local_irq_save(flags);
1854
1855 error = readl_poll_timeout_atomic(ddata->module_va + 0x44, val,
1856 !(val & BIT(0)), 100, 50);
1857 if (error)
1858 dev_warn(ddata->dev, "rtc busy timeout\n");
1859
1860 sysc_write(ddata, 0x6c, kick0_val);
1861 sysc_write(ddata, 0x70, kick1_val);
1862 local_irq_restore(flags);
1863}
1864
1865static void sysc_module_unlock_quirk_rtc(struct sysc *ddata)
1866{
1867 sysc_quirk_rtc(ddata, false);
1868}
1869
1870static void sysc_module_lock_quirk_rtc(struct sysc *ddata)
1871{
1872 sysc_quirk_rtc(ddata, true);
1873}
1874
1875
1876static void sysc_module_enable_quirk_sgx(struct sysc *ddata)
1877{
1878 int offset = 0xff08;
1879 u32 val = BIT(31);
1880
1881 sysc_write(ddata, offset, val);
1882}
1883
1884
1885static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
1886{
1887 int wps, spr, error;
1888 u32 val;
1889
1890 wps = 0x34;
1891 spr = 0x48;
1892
1893 sysc_write(ddata, spr, 0xaaaa);
1894 error = readl_poll_timeout(ddata->module_va + wps, val,
1895 !(val & 0x10), 100,
1896 MAX_MODULE_SOFTRESET_WAIT);
1897 if (error)
1898 dev_warn(ddata->dev, "wdt disable step1 failed\n");
1899
1900 sysc_write(ddata, spr, 0x5555);
1901 error = readl_poll_timeout(ddata->module_va + wps, val,
1902 !(val & 0x10), 100,
1903 MAX_MODULE_SOFTRESET_WAIT);
1904 if (error)
1905 dev_warn(ddata->dev, "wdt disable step2 failed\n");
1906}
1907
1908
1909static void sysc_module_disable_quirk_pruss(struct sysc *ddata)
1910{
1911 u32 reg;
1912
1913 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1914 reg |= SYSC_PRUSS_STANDBY_INIT;
1915 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
1916}
1917
1918static void sysc_init_module_quirks(struct sysc *ddata)
1919{
1920 if (ddata->legacy_mode || !ddata->name)
1921 return;
1922
1923 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
1924 ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w;
1925
1926 return;
1927 }
1928
1929#ifdef CONFIG_OMAP_GPMC_DEBUG
1930 if (ddata->cfg.quirks & SYSC_QUIRK_GPMC_DEBUG) {
1931 ddata->cfg.quirks |= SYSC_QUIRK_NO_RESET_ON_INIT;
1932
1933 return;
1934 }
1935#endif
1936
1937 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) {
1938 ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c;
1939 ddata->post_reset_quirk = sysc_post_reset_quirk_i2c;
1940
1941 return;
1942 }
1943
1944 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS)
1945 ddata->module_enable_quirk = sysc_module_enable_quirk_aess;
1946
1947 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_DSS_RESET)
1948 ddata->pre_reset_quirk = sysc_pre_reset_quirk_dss;
1949
1950 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) {
1951 ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc;
1952 ddata->module_lock_quirk = sysc_module_lock_quirk_rtc;
1953
1954 return;
1955 }
1956
1957 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
1958 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
1959
1960 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) {
1961 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
1962 ddata->module_disable_quirk = sysc_reset_done_quirk_wdt;
1963 }
1964
1965 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS)
1966 ddata->module_disable_quirk = sysc_module_disable_quirk_pruss;
1967}
1968
1969static int sysc_clockdomain_init(struct sysc *ddata)
1970{
1971 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1972 struct clk *fck = NULL, *ick = NULL;
1973 int error;
1974
1975 if (!pdata || !pdata->init_clockdomain)
1976 return 0;
1977
1978 switch (ddata->nr_clocks) {
1979 case 2:
1980 ick = ddata->clocks[SYSC_ICK];
1981 fallthrough;
1982 case 1:
1983 fck = ddata->clocks[SYSC_FCK];
1984 break;
1985 case 0:
1986 return 0;
1987 }
1988
1989 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie);
1990 if (!error || error == -ENODEV)
1991 return 0;
1992
1993 return error;
1994}
1995
1996
1997
1998
1999
2000
2001static int sysc_legacy_init(struct sysc *ddata)
2002{
2003 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2004 int error;
2005
2006 if (!pdata || !pdata->init_module)
2007 return 0;
2008
2009 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
2010 if (error == -EEXIST)
2011 error = 0;
2012
2013 return error;
2014}
2015
2016
2017
2018
2019
2020static int sysc_reset(struct sysc *ddata)
2021{
2022 int sysc_offset, sysc_val, error;
2023 u32 sysc_mask;
2024
2025 sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
2026
2027 if (ddata->legacy_mode ||
2028 ddata->cap->regbits->srst_shift < 0 ||
2029 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
2030 return 0;
2031
2032 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
2033
2034 if (ddata->pre_reset_quirk)
2035 ddata->pre_reset_quirk(ddata);
2036
2037 if (sysc_offset >= 0) {
2038 sysc_val = sysc_read_sysconfig(ddata);
2039 sysc_val |= sysc_mask;
2040 sysc_write(ddata, sysc_offset, sysc_val);
2041 }
2042
2043 if (ddata->cfg.srst_udelay)
2044 usleep_range(ddata->cfg.srst_udelay,
2045 ddata->cfg.srst_udelay * 2);
2046
2047 if (ddata->post_reset_quirk)
2048 ddata->post_reset_quirk(ddata);
2049
2050 error = sysc_wait_softreset(ddata);
2051 if (error)
2052 dev_warn(ddata->dev, "OCP softreset timed out\n");
2053
2054 if (ddata->reset_done_quirk)
2055 ddata->reset_done_quirk(ddata);
2056
2057 return error;
2058}
2059
2060
2061
2062
2063
2064
2065
2066static int sysc_init_module(struct sysc *ddata)
2067{
2068 bool rstctrl_deasserted = false;
2069 int error = 0;
2070
2071 error = sysc_clockdomain_init(ddata);
2072 if (error)
2073 return error;
2074
2075 sysc_clkdm_deny_idle(ddata);
2076
2077
2078
2079
2080
2081 error = sysc_enable_opt_clocks(ddata);
2082 if (error)
2083 return error;
2084
2085 error = sysc_enable_main_clocks(ddata);
2086 if (error)
2087 goto err_opt_clocks;
2088
2089 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) {
2090 error = reset_control_deassert(ddata->rsts);
2091 if (error)
2092 goto err_main_clocks;
2093 rstctrl_deasserted = true;
2094 }
2095
2096 ddata->revision = sysc_read_revision(ddata);
2097 sysc_init_revision_quirks(ddata);
2098 sysc_init_module_quirks(ddata);
2099
2100 if (ddata->legacy_mode) {
2101 error = sysc_legacy_init(ddata);
2102 if (error)
2103 goto err_main_clocks;
2104 }
2105
2106 if (!ddata->legacy_mode) {
2107 error = sysc_enable_module(ddata->dev);
2108 if (error)
2109 goto err_main_clocks;
2110 }
2111
2112 error = sysc_reset(ddata);
2113 if (error)
2114 dev_err(ddata->dev, "Reset failed with %d\n", error);
2115
2116 if (error && !ddata->legacy_mode)
2117 sysc_disable_module(ddata->dev);
2118
2119err_main_clocks:
2120 if (error)
2121 sysc_disable_main_clocks(ddata);
2122err_opt_clocks:
2123
2124 if (error) {
2125 sysc_disable_opt_clocks(ddata);
2126 sysc_clkdm_allow_idle(ddata);
2127 }
2128
2129 if (error && rstctrl_deasserted &&
2130 !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
2131 reset_control_assert(ddata->rsts);
2132
2133 return error;
2134}
2135
2136static int sysc_init_sysc_mask(struct sysc *ddata)
2137{
2138 struct device_node *np = ddata->dev->of_node;
2139 int error;
2140 u32 val;
2141
2142 error = of_property_read_u32(np, "ti,sysc-mask", &val);
2143 if (error)
2144 return 0;
2145
2146 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
2147
2148 return 0;
2149}
2150
2151static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
2152 const char *name)
2153{
2154 struct device_node *np = ddata->dev->of_node;
2155 struct property *prop;
2156 const __be32 *p;
2157 u32 val;
2158
2159 of_property_for_each_u32(np, name, prop, p, val) {
2160 if (val >= SYSC_NR_IDLEMODES) {
2161 dev_err(ddata->dev, "invalid idlemode: %i\n", val);
2162 return -EINVAL;
2163 }
2164 *idlemodes |= (1 << val);
2165 }
2166
2167 return 0;
2168}
2169
2170static int sysc_init_idlemodes(struct sysc *ddata)
2171{
2172 int error;
2173
2174 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
2175 "ti,sysc-midle");
2176 if (error)
2177 return error;
2178
2179 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
2180 "ti,sysc-sidle");
2181 if (error)
2182 return error;
2183
2184 return 0;
2185}
2186
2187
2188
2189
2190
2191
2192
2193
2194static int sysc_init_syss_mask(struct sysc *ddata)
2195{
2196 struct device_node *np = ddata->dev->of_node;
2197 int error;
2198 u32 val;
2199
2200 error = of_property_read_u32(np, "ti,syss-mask", &val);
2201 if (error) {
2202 if ((ddata->cap->type == TI_SYSC_OMAP4 ||
2203 ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
2204 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
2205 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
2206
2207 return 0;
2208 }
2209
2210 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
2211 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
2212
2213 ddata->cfg.syss_mask = val;
2214
2215 return 0;
2216}
2217
2218
2219
2220
2221
2222static int sysc_child_add_named_clock(struct sysc *ddata,
2223 struct device *child,
2224 const char *name)
2225{
2226 struct clk *clk;
2227 struct clk_lookup *l;
2228 int error = 0;
2229
2230 if (!name)
2231 return 0;
2232
2233 clk = clk_get(child, name);
2234 if (!IS_ERR(clk)) {
2235 error = -EEXIST;
2236 goto put_clk;
2237 }
2238
2239 clk = clk_get(ddata->dev, name);
2240 if (IS_ERR(clk))
2241 return -ENODEV;
2242
2243 l = clkdev_create(clk, name, dev_name(child));
2244 if (!l)
2245 error = -ENOMEM;
2246put_clk:
2247 clk_put(clk);
2248
2249 return error;
2250}
2251
2252static int sysc_child_add_clocks(struct sysc *ddata,
2253 struct device *child)
2254{
2255 int i, error;
2256
2257 for (i = 0; i < ddata->nr_clocks; i++) {
2258 error = sysc_child_add_named_clock(ddata,
2259 child,
2260 ddata->clock_roles[i]);
2261 if (error && error != -EEXIST) {
2262 dev_err(ddata->dev, "could not add child clock %s: %i\n",
2263 ddata->clock_roles[i], error);
2264
2265 return error;
2266 }
2267 }
2268
2269 return 0;
2270}
2271
2272static struct device_type sysc_device_type = {
2273};
2274
2275static struct sysc *sysc_child_to_parent(struct device *dev)
2276{
2277 struct device *parent = dev->parent;
2278
2279 if (!parent || parent->type != &sysc_device_type)
2280 return NULL;
2281
2282 return dev_get_drvdata(parent);
2283}
2284
2285static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
2286{
2287 struct sysc *ddata;
2288 int error;
2289
2290 ddata = sysc_child_to_parent(dev);
2291
2292 error = pm_generic_runtime_suspend(dev);
2293 if (error)
2294 return error;
2295
2296 if (!ddata->enabled)
2297 return 0;
2298
2299 return sysc_runtime_suspend(ddata->dev);
2300}
2301
2302static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
2303{
2304 struct sysc *ddata;
2305 int error;
2306
2307 ddata = sysc_child_to_parent(dev);
2308
2309 if (!ddata->enabled) {
2310 error = sysc_runtime_resume(ddata->dev);
2311 if (error < 0)
2312 dev_err(ddata->dev,
2313 "%s error: %i\n", __func__, error);
2314 }
2315
2316 return pm_generic_runtime_resume(dev);
2317}
2318
2319#ifdef CONFIG_PM_SLEEP
2320static int sysc_child_suspend_noirq(struct device *dev)
2321{
2322 struct sysc *ddata;
2323 int error;
2324
2325 ddata = sysc_child_to_parent(dev);
2326
2327 dev_dbg(ddata->dev, "%s %s\n", __func__,
2328 ddata->name ? ddata->name : "");
2329
2330 error = pm_generic_suspend_noirq(dev);
2331 if (error) {
2332 dev_err(dev, "%s error at %i: %i\n",
2333 __func__, __LINE__, error);
2334
2335 return error;
2336 }
2337
2338 if (!pm_runtime_status_suspended(dev)) {
2339 error = pm_generic_runtime_suspend(dev);
2340 if (error) {
2341 dev_dbg(dev, "%s busy at %i: %i\n",
2342 __func__, __LINE__, error);
2343
2344 return 0;
2345 }
2346
2347 error = sysc_runtime_suspend(ddata->dev);
2348 if (error) {
2349 dev_err(dev, "%s error at %i: %i\n",
2350 __func__, __LINE__, error);
2351
2352 return error;
2353 }
2354
2355 ddata->child_needs_resume = true;
2356 }
2357
2358 return 0;
2359}
2360
2361static int sysc_child_resume_noirq(struct device *dev)
2362{
2363 struct sysc *ddata;
2364 int error;
2365
2366 ddata = sysc_child_to_parent(dev);
2367
2368 dev_dbg(ddata->dev, "%s %s\n", __func__,
2369 ddata->name ? ddata->name : "");
2370
2371 if (ddata->child_needs_resume) {
2372 ddata->child_needs_resume = false;
2373
2374 error = sysc_runtime_resume(ddata->dev);
2375 if (error)
2376 dev_err(ddata->dev,
2377 "%s runtime resume error: %i\n",
2378 __func__, error);
2379
2380 error = pm_generic_runtime_resume(dev);
2381 if (error)
2382 dev_err(ddata->dev,
2383 "%s generic runtime resume: %i\n",
2384 __func__, error);
2385 }
2386
2387 return pm_generic_resume_noirq(dev);
2388}
2389#endif
2390
2391static struct dev_pm_domain sysc_child_pm_domain = {
2392 .ops = {
2393 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
2394 sysc_child_runtime_resume,
2395 NULL)
2396 USE_PLATFORM_PM_SLEEP_OPS
2397 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq,
2398 sysc_child_resume_noirq)
2399 }
2400};
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child)
2416{
2417 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
2418 dev_pm_domain_set(child, &sysc_child_pm_domain);
2419}
2420
2421static int sysc_notifier_call(struct notifier_block *nb,
2422 unsigned long event, void *device)
2423{
2424 struct device *dev = device;
2425 struct sysc *ddata;
2426 int error;
2427
2428 ddata = sysc_child_to_parent(dev);
2429 if (!ddata)
2430 return NOTIFY_DONE;
2431
2432 switch (event) {
2433 case BUS_NOTIFY_ADD_DEVICE:
2434 error = sysc_child_add_clocks(ddata, dev);
2435 if (error)
2436 return error;
2437 sysc_legacy_idle_quirk(ddata, dev);
2438 break;
2439 default:
2440 break;
2441 }
2442
2443 return NOTIFY_DONE;
2444}
2445
2446static struct notifier_block sysc_nb = {
2447 .notifier_call = sysc_notifier_call,
2448};
2449
2450
2451struct sysc_dts_quirk {
2452 const char *name;
2453 u32 mask;
2454};
2455
2456static const struct sysc_dts_quirk sysc_dts_quirks[] = {
2457 { .name = "ti,no-idle-on-init",
2458 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
2459 { .name = "ti,no-reset-on-init",
2460 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
2461 { .name = "ti,no-idle",
2462 .mask = SYSC_QUIRK_NO_IDLE, },
2463};
2464
2465static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
2466 bool is_child)
2467{
2468 const struct property *prop;
2469 int i, len;
2470
2471 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
2472 const char *name = sysc_dts_quirks[i].name;
2473
2474 prop = of_get_property(np, name, &len);
2475 if (!prop)
2476 continue;
2477
2478 ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
2479 if (is_child) {
2480 dev_warn(ddata->dev,
2481 "dts flag should be at module level for %s\n",
2482 name);
2483 }
2484 }
2485}
2486
2487static int sysc_init_dts_quirks(struct sysc *ddata)
2488{
2489 struct device_node *np = ddata->dev->of_node;
2490 int error;
2491 u32 val;
2492
2493 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
2494
2495 sysc_parse_dts_quirks(ddata, np, false);
2496 error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
2497 if (!error) {
2498 if (val > 255) {
2499 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
2500 val);
2501 }
2502
2503 ddata->cfg.srst_udelay = (u8)val;
2504 }
2505
2506 return 0;
2507}
2508
2509static void sysc_unprepare(struct sysc *ddata)
2510{
2511 int i;
2512
2513 if (!ddata->clocks)
2514 return;
2515
2516 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
2517 if (!IS_ERR_OR_NULL(ddata->clocks[i]))
2518 clk_unprepare(ddata->clocks[i]);
2519 }
2520}
2521
2522
2523
2524
2525static const struct sysc_regbits sysc_regbits_omap2 = {
2526 .dmadisable_shift = -ENODEV,
2527 .midle_shift = 12,
2528 .sidle_shift = 3,
2529 .clkact_shift = 8,
2530 .emufree_shift = 5,
2531 .enwkup_shift = 2,
2532 .srst_shift = 1,
2533 .autoidle_shift = 0,
2534};
2535
2536static const struct sysc_capabilities sysc_omap2 = {
2537 .type = TI_SYSC_OMAP2,
2538 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2539 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2540 SYSC_OMAP2_AUTOIDLE,
2541 .regbits = &sysc_regbits_omap2,
2542};
2543
2544
2545static const struct sysc_capabilities sysc_omap2_timer = {
2546 .type = TI_SYSC_OMAP2_TIMER,
2547 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2548 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2549 SYSC_OMAP2_AUTOIDLE,
2550 .regbits = &sysc_regbits_omap2,
2551 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
2552};
2553
2554
2555
2556
2557
2558static const struct sysc_regbits sysc_regbits_omap3_sham = {
2559 .dmadisable_shift = -ENODEV,
2560 .midle_shift = -ENODEV,
2561 .sidle_shift = 4,
2562 .clkact_shift = -ENODEV,
2563 .enwkup_shift = -ENODEV,
2564 .srst_shift = 1,
2565 .autoidle_shift = 0,
2566 .emufree_shift = -ENODEV,
2567};
2568
2569static const struct sysc_capabilities sysc_omap3_sham = {
2570 .type = TI_SYSC_OMAP3_SHAM,
2571 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2572 .regbits = &sysc_regbits_omap3_sham,
2573};
2574
2575
2576
2577
2578
2579static const struct sysc_regbits sysc_regbits_omap3_aes = {
2580 .dmadisable_shift = -ENODEV,
2581 .midle_shift = -ENODEV,
2582 .sidle_shift = 6,
2583 .clkact_shift = -ENODEV,
2584 .enwkup_shift = -ENODEV,
2585 .srst_shift = 1,
2586 .autoidle_shift = 0,
2587 .emufree_shift = -ENODEV,
2588};
2589
2590static const struct sysc_capabilities sysc_omap3_aes = {
2591 .type = TI_SYSC_OMAP3_AES,
2592 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2593 .regbits = &sysc_regbits_omap3_aes,
2594};
2595
2596
2597
2598
2599static const struct sysc_regbits sysc_regbits_omap4 = {
2600 .dmadisable_shift = 16,
2601 .midle_shift = 4,
2602 .sidle_shift = 2,
2603 .clkact_shift = -ENODEV,
2604 .enwkup_shift = -ENODEV,
2605 .emufree_shift = 1,
2606 .srst_shift = 0,
2607 .autoidle_shift = -ENODEV,
2608};
2609
2610static const struct sysc_capabilities sysc_omap4 = {
2611 .type = TI_SYSC_OMAP4,
2612 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2613 SYSC_OMAP4_SOFTRESET,
2614 .regbits = &sysc_regbits_omap4,
2615};
2616
2617static const struct sysc_capabilities sysc_omap4_timer = {
2618 .type = TI_SYSC_OMAP4_TIMER,
2619 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2620 SYSC_OMAP4_SOFTRESET,
2621 .regbits = &sysc_regbits_omap4,
2622};
2623
2624
2625
2626
2627static const struct sysc_regbits sysc_regbits_omap4_simple = {
2628 .dmadisable_shift = -ENODEV,
2629 .midle_shift = 2,
2630 .sidle_shift = 0,
2631 .clkact_shift = -ENODEV,
2632 .enwkup_shift = -ENODEV,
2633 .srst_shift = -ENODEV,
2634 .emufree_shift = -ENODEV,
2635 .autoidle_shift = -ENODEV,
2636};
2637
2638static const struct sysc_capabilities sysc_omap4_simple = {
2639 .type = TI_SYSC_OMAP4_SIMPLE,
2640 .regbits = &sysc_regbits_omap4_simple,
2641};
2642
2643
2644
2645
2646static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
2647 .dmadisable_shift = -ENODEV,
2648 .midle_shift = -ENODEV,
2649 .sidle_shift = -ENODEV,
2650 .clkact_shift = 20,
2651 .enwkup_shift = -ENODEV,
2652 .srst_shift = -ENODEV,
2653 .emufree_shift = -ENODEV,
2654 .autoidle_shift = -ENODEV,
2655};
2656
2657static const struct sysc_capabilities sysc_34xx_sr = {
2658 .type = TI_SYSC_OMAP34XX_SR,
2659 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
2660 .regbits = &sysc_regbits_omap34xx_sr,
2661 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED |
2662 SYSC_QUIRK_LEGACY_IDLE,
2663};
2664
2665
2666
2667
2668static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
2669 .dmadisable_shift = -ENODEV,
2670 .midle_shift = -ENODEV,
2671 .sidle_shift = 24,
2672 .clkact_shift = -ENODEV,
2673 .enwkup_shift = 26,
2674 .srst_shift = -ENODEV,
2675 .emufree_shift = -ENODEV,
2676 .autoidle_shift = -ENODEV,
2677};
2678
2679static const struct sysc_capabilities sysc_36xx_sr = {
2680 .type = TI_SYSC_OMAP36XX_SR,
2681 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
2682 .regbits = &sysc_regbits_omap36xx_sr,
2683 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE,
2684};
2685
2686static const struct sysc_capabilities sysc_omap4_sr = {
2687 .type = TI_SYSC_OMAP4_SR,
2688 .regbits = &sysc_regbits_omap36xx_sr,
2689 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE,
2690};
2691
2692
2693
2694
2695static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
2696 .dmadisable_shift = -ENODEV,
2697 .midle_shift = -ENODEV,
2698 .sidle_shift = 0,
2699 .clkact_shift = -ENODEV,
2700 .enwkup_shift = -ENODEV,
2701 .srst_shift = -ENODEV,
2702 .emufree_shift = -ENODEV,
2703 .autoidle_shift = -ENODEV,
2704};
2705
2706static const struct sysc_capabilities sysc_omap4_mcasp = {
2707 .type = TI_SYSC_OMAP4_MCASP,
2708 .regbits = &sysc_regbits_omap4_mcasp,
2709 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2710};
2711
2712
2713
2714
2715static const struct sysc_capabilities sysc_dra7_mcasp = {
2716 .type = TI_SYSC_OMAP4_SIMPLE,
2717 .regbits = &sysc_regbits_omap4_simple,
2718 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2719};
2720
2721
2722
2723
2724static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
2725 .dmadisable_shift = -ENODEV,
2726 .midle_shift = -ENODEV,
2727 .sidle_shift = 24,
2728 .clkact_shift = -ENODEV,
2729 .enwkup_shift = 26,
2730 .srst_shift = -ENODEV,
2731 .emufree_shift = -ENODEV,
2732 .autoidle_shift = -ENODEV,
2733};
2734
2735static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
2736 .type = TI_SYSC_OMAP4_USB_HOST_FS,
2737 .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
2738 .regbits = &sysc_regbits_omap4_usb_host_fs,
2739};
2740
2741static const struct sysc_regbits sysc_regbits_dra7_mcan = {
2742 .dmadisable_shift = -ENODEV,
2743 .midle_shift = -ENODEV,
2744 .sidle_shift = -ENODEV,
2745 .clkact_shift = -ENODEV,
2746 .enwkup_shift = 4,
2747 .srst_shift = 0,
2748 .emufree_shift = -ENODEV,
2749 .autoidle_shift = -ENODEV,
2750};
2751
2752static const struct sysc_capabilities sysc_dra7_mcan = {
2753 .type = TI_SYSC_DRA7_MCAN,
2754 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
2755 .regbits = &sysc_regbits_dra7_mcan,
2756 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED,
2757};
2758
2759
2760
2761
2762static const struct sysc_capabilities sysc_pruss = {
2763 .type = TI_SYSC_PRUSS,
2764 .sysc_mask = SYSC_PRUSS_STANDBY_INIT | SYSC_PRUSS_SUB_MWAIT,
2765 .regbits = &sysc_regbits_omap4_simple,
2766 .mod_quirks = SYSC_MODULE_QUIRK_PRUSS,
2767};
2768
2769static int sysc_init_pdata(struct sysc *ddata)
2770{
2771 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2772 struct ti_sysc_module_data *mdata;
2773
2774 if (!pdata)
2775 return 0;
2776
2777 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
2778 if (!mdata)
2779 return -ENOMEM;
2780
2781 if (ddata->legacy_mode) {
2782 mdata->name = ddata->legacy_mode;
2783 mdata->module_pa = ddata->module_pa;
2784 mdata->module_size = ddata->module_size;
2785 mdata->offsets = ddata->offsets;
2786 mdata->nr_offsets = SYSC_MAX_REGS;
2787 mdata->cap = ddata->cap;
2788 mdata->cfg = &ddata->cfg;
2789 }
2790
2791 ddata->mdata = mdata;
2792
2793 return 0;
2794}
2795
2796static int sysc_init_match(struct sysc *ddata)
2797{
2798 const struct sysc_capabilities *cap;
2799
2800 cap = of_device_get_match_data(ddata->dev);
2801 if (!cap)
2802 return -EINVAL;
2803
2804 ddata->cap = cap;
2805 if (ddata->cap)
2806 ddata->cfg.quirks |= ddata->cap->mod_quirks;
2807
2808 return 0;
2809}
2810
2811static void ti_sysc_idle(struct work_struct *work)
2812{
2813 struct sysc *ddata;
2814
2815 ddata = container_of(work, struct sysc, idle_work.work);
2816
2817
2818
2819
2820
2821
2822
2823 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
2824 SYSC_QUIRK_NO_IDLE_ON_INIT)) {
2825 sysc_disable_main_clocks(ddata);
2826 sysc_disable_opt_clocks(ddata);
2827 sysc_clkdm_allow_idle(ddata);
2828 }
2829
2830
2831 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)
2832 return;
2833
2834
2835
2836
2837
2838 if (pm_runtime_active(ddata->dev))
2839 pm_runtime_put_sync(ddata->dev);
2840}
2841
2842
2843
2844
2845
2846static const struct soc_device_attribute sysc_soc_match[] = {
2847 SOC_FLAG("OMAP242*", SOC_2420),
2848 SOC_FLAG("OMAP243*", SOC_2430),
2849 SOC_FLAG("OMAP3[45]*", SOC_3430),
2850 SOC_FLAG("OMAP3[67]*", SOC_3630),
2851 SOC_FLAG("OMAP443*", SOC_4430),
2852 SOC_FLAG("OMAP446*", SOC_4460),
2853 SOC_FLAG("OMAP447*", SOC_4470),
2854 SOC_FLAG("OMAP54*", SOC_5430),
2855 SOC_FLAG("AM433", SOC_AM3),
2856 SOC_FLAG("AM43*", SOC_AM4),
2857 SOC_FLAG("DRA7*", SOC_DRA7),
2858
2859 { },
2860};
2861
2862
2863
2864
2865
2866static const struct soc_device_attribute sysc_soc_feat_match[] = {
2867
2868 SOC_FLAG("AM3505", DIS_SGX),
2869 SOC_FLAG("OMAP3525", DIS_SGX),
2870 SOC_FLAG("OMAP3515", DIS_IVA | DIS_SGX),
2871 SOC_FLAG("OMAP3503", DIS_ISP | DIS_IVA | DIS_SGX),
2872
2873
2874 SOC_FLAG("AM3703", DIS_IVA | DIS_SGX),
2875 SOC_FLAG("DM3725", DIS_SGX),
2876 SOC_FLAG("OMAP3611", DIS_ISP | DIS_IVA | DIS_SGX),
2877 SOC_FLAG("OMAP3615/AM3715", DIS_IVA),
2878 SOC_FLAG("OMAP3621", DIS_ISP),
2879
2880 { },
2881};
2882
2883static int sysc_add_disabled(unsigned long base)
2884{
2885 struct sysc_address *disabled_module;
2886
2887 disabled_module = kzalloc(sizeof(*disabled_module), GFP_KERNEL);
2888 if (!disabled_module)
2889 return -ENOMEM;
2890
2891 disabled_module->base = base;
2892
2893 mutex_lock(&sysc_soc->list_lock);
2894 list_add(&disabled_module->node, &sysc_soc->disabled_modules);
2895 mutex_unlock(&sysc_soc->list_lock);
2896
2897 return 0;
2898}
2899
2900
2901
2902
2903
2904
2905
2906static int sysc_init_soc(struct sysc *ddata)
2907{
2908 const struct soc_device_attribute *match;
2909 struct ti_sysc_platform_data *pdata;
2910 unsigned long features = 0;
2911 struct device_node *np;
2912
2913 if (sysc_soc)
2914 return 0;
2915
2916 sysc_soc = kzalloc(sizeof(*sysc_soc), GFP_KERNEL);
2917 if (!sysc_soc)
2918 return -ENOMEM;
2919
2920 mutex_init(&sysc_soc->list_lock);
2921 INIT_LIST_HEAD(&sysc_soc->disabled_modules);
2922 sysc_soc->general_purpose = true;
2923
2924 pdata = dev_get_platdata(ddata->dev);
2925 if (pdata && pdata->soc_type_gp)
2926 sysc_soc->general_purpose = pdata->soc_type_gp();
2927
2928 match = soc_device_match(sysc_soc_match);
2929 if (match && match->data)
2930 sysc_soc->soc = (int)match->data;
2931
2932
2933
2934
2935
2936 switch (sysc_soc->soc) {
2937 case SOC_AM3:
2938 case SOC_AM4:
2939 case SOC_4430 ... SOC_4470:
2940 case SOC_5430:
2941 case SOC_DRA7:
2942 np = of_find_node_by_path("/ocp");
2943 WARN_ONCE(np && of_device_is_compatible(np, "simple-bus"),
2944 "ti-sysc: Incomplete old dtb, please update\n");
2945 break;
2946 default:
2947 break;
2948 }
2949
2950
2951 if (!sysc_soc->general_purpose) {
2952 switch (sysc_soc->soc) {
2953 case SOC_3430 ... SOC_3630:
2954 sysc_add_disabled(0x48304000);
2955 break;
2956 case SOC_AM3:
2957 sysc_add_disabled(0x48310000);
2958 default:
2959 break;
2960 }
2961 }
2962
2963 match = soc_device_match(sysc_soc_feat_match);
2964 if (!match)
2965 return 0;
2966
2967 if (match->data)
2968 features = (unsigned long)match->data;
2969
2970
2971
2972
2973
2974
2975 if (features & DIS_ISP)
2976 sysc_add_disabled(0x480bd400);
2977 if (features & DIS_IVA)
2978 sysc_add_disabled(0x5d000000);
2979 if (features & DIS_SGX)
2980 sysc_add_disabled(0x50000000);
2981
2982 return 0;
2983}
2984
2985static void sysc_cleanup_soc(void)
2986{
2987 struct sysc_address *disabled_module;
2988 struct list_head *pos, *tmp;
2989
2990 if (!sysc_soc)
2991 return;
2992
2993 mutex_lock(&sysc_soc->list_lock);
2994 list_for_each_safe(pos, tmp, &sysc_soc->disabled_modules) {
2995 disabled_module = list_entry(pos, struct sysc_address, node);
2996 list_del(pos);
2997 kfree(disabled_module);
2998 }
2999 mutex_unlock(&sysc_soc->list_lock);
3000}
3001
3002static int sysc_check_disabled_devices(struct sysc *ddata)
3003{
3004 struct sysc_address *disabled_module;
3005 struct list_head *pos;
3006 int error = 0;
3007
3008 mutex_lock(&sysc_soc->list_lock);
3009 list_for_each(pos, &sysc_soc->disabled_modules) {
3010 disabled_module = list_entry(pos, struct sysc_address, node);
3011 if (ddata->module_pa == disabled_module->base) {
3012 dev_dbg(ddata->dev, "module disabled for this SoC\n");
3013 error = -ENODEV;
3014 break;
3015 }
3016 }
3017 mutex_unlock(&sysc_soc->list_lock);
3018
3019 return error;
3020}
3021
3022
3023
3024
3025
3026
3027static int sysc_check_active_timer(struct sysc *ddata)
3028{
3029 if (ddata->cap->type != TI_SYSC_OMAP2_TIMER &&
3030 ddata->cap->type != TI_SYSC_OMAP4_TIMER)
3031 return 0;
3032
3033 if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) &&
3034 (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE))
3035 return -ENXIO;
3036
3037 return 0;
3038}
3039
3040static const struct of_device_id sysc_match_table[] = {
3041 { .compatible = "simple-bus", },
3042 { },
3043};
3044
3045static int sysc_probe(struct platform_device *pdev)
3046{
3047 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
3048 struct sysc *ddata;
3049 int error;
3050
3051 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
3052 if (!ddata)
3053 return -ENOMEM;
3054
3055 ddata->offsets[SYSC_REVISION] = -ENODEV;
3056 ddata->offsets[SYSC_SYSCONFIG] = -ENODEV;
3057 ddata->offsets[SYSC_SYSSTATUS] = -ENODEV;
3058 ddata->dev = &pdev->dev;
3059 platform_set_drvdata(pdev, ddata);
3060
3061 error = sysc_init_soc(ddata);
3062 if (error)
3063 return error;
3064
3065 error = sysc_init_match(ddata);
3066 if (error)
3067 return error;
3068
3069 error = sysc_init_dts_quirks(ddata);
3070 if (error)
3071 return error;
3072
3073 error = sysc_map_and_check_registers(ddata);
3074 if (error)
3075 return error;
3076
3077 error = sysc_init_sysc_mask(ddata);
3078 if (error)
3079 return error;
3080
3081 error = sysc_init_idlemodes(ddata);
3082 if (error)
3083 return error;
3084
3085 error = sysc_init_syss_mask(ddata);
3086 if (error)
3087 return error;
3088
3089 error = sysc_init_pdata(ddata);
3090 if (error)
3091 return error;
3092
3093 sysc_init_early_quirks(ddata);
3094
3095 error = sysc_check_disabled_devices(ddata);
3096 if (error)
3097 return error;
3098
3099 error = sysc_check_active_timer(ddata);
3100 if (error == -ENXIO)
3101 ddata->reserved = true;
3102 else if (error)
3103 return error;
3104
3105 error = sysc_get_clocks(ddata);
3106 if (error)
3107 return error;
3108
3109 error = sysc_init_resets(ddata);
3110 if (error)
3111 goto unprepare;
3112
3113 error = sysc_init_module(ddata);
3114 if (error)
3115 goto unprepare;
3116
3117 pm_runtime_enable(ddata->dev);
3118 error = pm_runtime_get_sync(ddata->dev);
3119 if (error < 0) {
3120 pm_runtime_put_noidle(ddata->dev);
3121 pm_runtime_disable(ddata->dev);
3122 goto unprepare;
3123 }
3124
3125
3126 if (!(ddata->cfg.quirks &
3127 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) {
3128 sysc_disable_main_clocks(ddata);
3129 sysc_disable_opt_clocks(ddata);
3130 sysc_clkdm_allow_idle(ddata);
3131 }
3132
3133 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
3134 reset_control_assert(ddata->rsts);
3135
3136 sysc_show_registers(ddata);
3137
3138 ddata->dev->type = &sysc_device_type;
3139
3140 if (!ddata->reserved) {
3141 error = of_platform_populate(ddata->dev->of_node,
3142 sysc_match_table,
3143 pdata ? pdata->auxdata : NULL,
3144 ddata->dev);
3145 if (error)
3146 goto err;
3147 }
3148
3149 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
3150
3151
3152 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
3153 SYSC_QUIRK_NO_IDLE_ON_INIT |
3154 SYSC_QUIRK_NO_RESET_ON_INIT)) {
3155 schedule_delayed_work(&ddata->idle_work, 3000);
3156 } else {
3157 pm_runtime_put(&pdev->dev);
3158 }
3159
3160 return 0;
3161
3162err:
3163 pm_runtime_put_sync(&pdev->dev);
3164 pm_runtime_disable(&pdev->dev);
3165unprepare:
3166 sysc_unprepare(ddata);
3167
3168 return error;
3169}
3170
3171static int sysc_remove(struct platform_device *pdev)
3172{
3173 struct sysc *ddata = platform_get_drvdata(pdev);
3174 int error;
3175
3176 cancel_delayed_work_sync(&ddata->idle_work);
3177
3178 error = pm_runtime_get_sync(ddata->dev);
3179 if (error < 0) {
3180 pm_runtime_put_noidle(ddata->dev);
3181 pm_runtime_disable(ddata->dev);
3182 goto unprepare;
3183 }
3184
3185 of_platform_depopulate(&pdev->dev);
3186
3187 pm_runtime_put_sync(&pdev->dev);
3188 pm_runtime_disable(&pdev->dev);
3189
3190 if (!reset_control_status(ddata->rsts))
3191 reset_control_assert(ddata->rsts);
3192
3193unprepare:
3194 sysc_unprepare(ddata);
3195
3196 return 0;
3197}
3198
3199static const struct of_device_id sysc_match[] = {
3200 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
3201 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
3202 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
3203 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
3204 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
3205 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
3206 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
3207 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
3208 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
3209 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
3210 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
3211 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
3212 { .compatible = "ti,sysc-usb-host-fs",
3213 .data = &sysc_omap4_usb_host_fs, },
3214 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
3215 { .compatible = "ti,sysc-pruss", .data = &sysc_pruss, },
3216 { },
3217};
3218MODULE_DEVICE_TABLE(of, sysc_match);
3219
3220static struct platform_driver sysc_driver = {
3221 .probe = sysc_probe,
3222 .remove = sysc_remove,
3223 .driver = {
3224 .name = "ti-sysc",
3225 .of_match_table = sysc_match,
3226 .pm = &sysc_pm_ops,
3227 },
3228};
3229
3230static int __init sysc_init(void)
3231{
3232 bus_register_notifier(&platform_bus_type, &sysc_nb);
3233
3234 return platform_driver_register(&sysc_driver);
3235}
3236module_init(sysc_init);
3237
3238static void __exit sysc_exit(void)
3239{
3240 bus_unregister_notifier(&platform_bus_type, &sysc_nb);
3241 platform_driver_unregister(&sysc_driver);
3242 sysc_cleanup_soc();
3243}
3244module_exit(sysc_exit);
3245
3246MODULE_DESCRIPTION("TI sysc interconnect target driver");
3247MODULE_LICENSE("GPL v2");
3248