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11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/bug.h>
14
15#include <asm/mipsregs.h>
16#include <asm/mach-ralink/ralink_regs.h>
17#include <asm/mach-ralink/mt7620.h>
18
19#include "common.h"
20
21
22#define PMU0_CFG 0x88
23#define PMU_SW_SET BIT(28)
24#define A_DCDC_EN BIT(24)
25#define A_SSC_PERI BIT(19)
26#define A_SSC_GEN BIT(18)
27#define A_SSC_M 0x3
28#define A_SSC_S 16
29#define A_DLY_M 0x7
30#define A_DLY_S 8
31#define A_VTUNE_M 0xff
32
33
34#define PMU1_CFG 0x8C
35#define DIG_SW_SEL BIT(25)
36
37
38#define CLKCFG_FDIV_MASK 0x1f00
39#define CLKCFG_FDIV_USB_VAL 0x0300
40#define CLKCFG_FFRAC_MASK 0x001f
41#define CLKCFG_FFRAC_USB_VAL 0x0003
42
43
44#define EFUSE_MT7688 0x100000
45
46
47#define DRAM_TYPE_MT7628_MASK 0x1
48
49
50static int dram_type;
51
52static __init u32
53mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
54{
55 u64 t;
56
57 t = ref_rate;
58 t *= mul;
59 do_div(t, div);
60
61 return t;
62}
63
64#define MHZ(x) ((x) * 1000 * 1000)
65
66static __init unsigned long
67mt7620_get_xtal_rate(void)
68{
69 u32 reg;
70
71 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
72 if (reg & SYSCFG0_XTAL_FREQ_SEL)
73 return MHZ(40);
74
75 return MHZ(20);
76}
77
78static __init unsigned long
79mt7620_get_periph_rate(unsigned long xtal_rate)
80{
81 u32 reg;
82
83 reg = rt_sysc_r32(SYSC_REG_CLKCFG0);
84 if (reg & CLKCFG0_PERI_CLK_SEL)
85 return xtal_rate;
86
87 return MHZ(40);
88}
89
90static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 };
91
92static __init unsigned long
93mt7620_get_cpu_pll_rate(unsigned long xtal_rate)
94{
95 u32 reg;
96 u32 mul;
97 u32 div;
98
99 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
100 if (reg & CPLL_CFG0_BYPASS_REF_CLK)
101 return xtal_rate;
102
103 if ((reg & CPLL_CFG0_SW_CFG) == 0)
104 return MHZ(600);
105
106 mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
107 CPLL_CFG0_PLL_MULT_RATIO_MASK;
108 mul += 24;
109 if (reg & CPLL_CFG0_LC_CURFCK)
110 mul *= 2;
111
112 div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
113 CPLL_CFG0_PLL_DIV_RATIO_MASK;
114
115 WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider));
116
117 return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]);
118}
119
120static __init unsigned long
121mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate)
122{
123 u32 reg;
124
125 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
126 if (reg & CPLL_CFG1_CPU_AUX1)
127 return xtal_rate;
128
129 if (reg & CPLL_CFG1_CPU_AUX0)
130 return MHZ(480);
131
132 return cpu_pll_rate;
133}
134
135static __init unsigned long
136mt7620_get_cpu_rate(unsigned long pll_rate)
137{
138 u32 reg;
139 u32 mul;
140 u32 div;
141
142 reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
143
144 mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
145 div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
146 CPU_SYS_CLKCFG_CPU_FDIV_MASK;
147
148 return mt7620_calc_rate(pll_rate, mul, div);
149}
150
151static const u32 mt7620_ocp_dividers[16] __initconst = {
152 [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
153 [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
154 [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
155 [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
156 [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
157};
158
159static __init unsigned long
160mt7620_get_dram_rate(unsigned long pll_rate)
161{
162 if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
163 return pll_rate / 4;
164
165 return pll_rate / 3;
166}
167
168static __init unsigned long
169mt7620_get_sys_rate(unsigned long cpu_rate)
170{
171 u32 reg;
172 u32 ocp_ratio;
173 u32 div;
174
175 reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
176
177 ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
178 CPU_SYS_CLKCFG_OCP_RATIO_MASK;
179
180 if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers)))
181 return cpu_rate;
182
183 div = mt7620_ocp_dividers[ocp_ratio];
184 if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
185 return cpu_rate;
186
187 return cpu_rate / div;
188}
189
190void __init ralink_clk_init(void)
191{
192 unsigned long xtal_rate;
193 unsigned long cpu_pll_rate;
194 unsigned long pll_rate;
195 unsigned long cpu_rate;
196 unsigned long sys_rate;
197 unsigned long dram_rate;
198 unsigned long periph_rate;
199 unsigned long pcmi2s_rate;
200
201 xtal_rate = mt7620_get_xtal_rate();
202
203#define RFMT(label) label ":%lu.%03luMHz "
204#define RINT(x) ((x) / 1000000)
205#define RFRAC(x) (((x) / 1000) % 1000)
206
207 if (is_mt76x8()) {
208 if (xtal_rate == MHZ(40))
209 cpu_rate = MHZ(580);
210 else
211 cpu_rate = MHZ(575);
212 dram_rate = sys_rate = cpu_rate / 3;
213 periph_rate = MHZ(40);
214 pcmi2s_rate = MHZ(480);
215
216 ralink_clk_add("10000d00.uartlite", periph_rate);
217 ralink_clk_add("10000e00.uartlite", periph_rate);
218 } else {
219 cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
220 pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
221
222 cpu_rate = mt7620_get_cpu_rate(pll_rate);
223 dram_rate = mt7620_get_dram_rate(pll_rate);
224 sys_rate = mt7620_get_sys_rate(cpu_rate);
225 periph_rate = mt7620_get_periph_rate(xtal_rate);
226 pcmi2s_rate = periph_rate;
227
228 pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
229 RINT(xtal_rate), RFRAC(xtal_rate),
230 RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
231 RINT(pll_rate), RFRAC(pll_rate));
232
233 ralink_clk_add("10000500.uart", periph_rate);
234 }
235
236 pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
237 RINT(cpu_rate), RFRAC(cpu_rate),
238 RINT(dram_rate), RFRAC(dram_rate),
239 RINT(sys_rate), RFRAC(sys_rate),
240 RINT(periph_rate), RFRAC(periph_rate));
241#undef RFRAC
242#undef RINT
243#undef RFMT
244
245 ralink_clk_add("cpu", cpu_rate);
246 ralink_clk_add("10000100.timer", periph_rate);
247 ralink_clk_add("10000120.watchdog", periph_rate);
248 ralink_clk_add("10000900.i2c", periph_rate);
249 ralink_clk_add("10000a00.i2s", pcmi2s_rate);
250 ralink_clk_add("10000b00.spi", sys_rate);
251 ralink_clk_add("10000b40.spi", sys_rate);
252 ralink_clk_add("10000c00.uartlite", periph_rate);
253 ralink_clk_add("10000d00.uart1", periph_rate);
254 ralink_clk_add("10000e00.uart2", periph_rate);
255 ralink_clk_add("10180000.wmac", xtal_rate);
256
257 if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
258
259
260
261
262
263 u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
264
265 val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
266 val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
267
268 rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
269 }
270}
271
272void __init ralink_of_remap(void)
273{
274 rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
275 rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc");
276
277 if (!rt_sysc_membase || !rt_memc_membase)
278 panic("Failed to remap core resources");
279}
280
281static __init void
282mt7620_dram_init(struct ralink_soc_info *soc_info)
283{
284 switch (dram_type) {
285 case SYSCFG0_DRAM_TYPE_SDRAM:
286 pr_info("Board has SDRAM\n");
287 soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
288 soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
289 break;
290
291 case SYSCFG0_DRAM_TYPE_DDR1:
292 pr_info("Board has DDR1\n");
293 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
294 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
295 break;
296
297 case SYSCFG0_DRAM_TYPE_DDR2:
298 pr_info("Board has DDR2\n");
299 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
300 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
301 break;
302 default:
303 BUG();
304 }
305}
306
307static __init void
308mt7628_dram_init(struct ralink_soc_info *soc_info)
309{
310 switch (dram_type) {
311 case SYSCFG0_DRAM_TYPE_DDR1_MT7628:
312 pr_info("Board has DDR1\n");
313 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
314 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
315 break;
316
317 case SYSCFG0_DRAM_TYPE_DDR2_MT7628:
318 pr_info("Board has DDR2\n");
319 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
320 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
321 break;
322 default:
323 BUG();
324 }
325}
326
327void __init prom_soc_init(struct ralink_soc_info *soc_info)
328{
329 void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
330 unsigned char *name = NULL;
331 u32 n0;
332 u32 n1;
333 u32 rev;
334 u32 cfg0;
335 u32 pmu0;
336 u32 pmu1;
337 u32 bga;
338
339 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
340 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
341 rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
342 bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK;
343
344 if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) {
345 if (bga) {
346 ralink_soc = MT762X_SOC_MT7620A;
347 name = "MT7620A";
348 soc_info->compatible = "ralink,mt7620a-soc";
349 } else {
350 ralink_soc = MT762X_SOC_MT7620N;
351 name = "MT7620N";
352 soc_info->compatible = "ralink,mt7620n-soc";
353 }
354 } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
355 u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG);
356
357 if (efuse & EFUSE_MT7688) {
358 ralink_soc = MT762X_SOC_MT7688;
359 name = "MT7688";
360 } else {
361 ralink_soc = MT762X_SOC_MT7628AN;
362 name = "MT7628AN";
363 }
364 soc_info->compatible = "ralink,mt7628an-soc";
365 } else {
366 panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
367 }
368
369 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
370 "MediaTek %s ver:%u eco:%u",
371 name,
372 (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
373 (rev & CHIP_REV_ECO_MASK));
374
375 cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
376 if (is_mt76x8()) {
377 dram_type = cfg0 & DRAM_TYPE_MT7628_MASK;
378 } else {
379 dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) &
380 SYSCFG0_DRAM_TYPE_MASK;
381 if (dram_type == SYSCFG0_DRAM_TYPE_UNKNOWN)
382 dram_type = SYSCFG0_DRAM_TYPE_SDRAM;
383 }
384
385 soc_info->mem_base = MT7620_DRAM_BASE;
386 if (is_mt76x8())
387 mt7628_dram_init(soc_info);
388 else
389 mt7620_dram_init(soc_info);
390
391 pmu0 = __raw_readl(sysc + PMU0_CFG);
392 pmu1 = __raw_readl(sysc + PMU1_CFG);
393
394 pr_info("Analog PMU set to %s control\n",
395 (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
396 pr_info("Digital PMU set to %s control\n",
397 (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
398}
399
