LXR linux/arch/mips/pistachio/init.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Pistachio platform setup
   4 *
   5 * Copyright (C) 2014 Google, Inc.
   6 * Copyright (C) 2016 Imagination Technologies
   7 */
   8
   9#include <linux/init.h>
  10#include <linux/io.h>
  11#include <linux/kernel.h>
  12#include <linux/of_address.h>
  13#include <linux/of_fdt.h>
  14
  15#include <asm/cacheflush.h>
  16#include <asm/fw/fw.h>
  17#include <asm/mips-boards/generic.h>
  18#include <asm/mips-cps.h>
  19#include <asm/prom.h>
  20#include <asm/smp-ops.h>
  21#include <asm/traps.h>
  22
  23/*
  24 * Core revision register decoding
  25 * Bits 23 to 20: Major rev
  26 * Bits 15 to 8: Minor rev
  27 * Bits 7 to 0: Maintenance rev
  28 */
  29#define PISTACHIO_CORE_REV_REG  0xB81483D0
  30#define PISTACHIO_CORE_REV_A1   0x00100006
  31#define PISTACHIO_CORE_REV_B0   0x00100106
  32
  33const char *get_system_type(void)
  34{
  35        u32 core_rev;
  36        const char *sys_type;
  37
  38        core_rev = __raw_readl((const void *)PISTACHIO_CORE_REV_REG);
  39
  40        switch (core_rev) {
  41        case PISTACHIO_CORE_REV_B0:
  42                sys_type = "IMG Pistachio SoC (B0)";
  43                break;
  44
  45        case PISTACHIO_CORE_REV_A1:
  46                sys_type = "IMG Pistachio SoC (A1)";
  47                break;
  48
  49        default:
  50                sys_type = "IMG Pistachio SoC";
  51                break;
  52        }
  53
  54        return sys_type;
  55}
  56
  57void __init *plat_get_fdt(void)
  58{
  59        if (fw_arg0 != -2)
  60                panic("Device-tree not present");
  61        return (void *)fw_arg1;
  62}
  63
  64void __init plat_mem_setup(void)
  65{
  66        __dt_setup_arch(plat_get_fdt());
  67}
  68
  69#define DEFAULT_CPC_BASE_ADDR   0x1bde0000
  70#define DEFAULT_CDMM_BASE_ADDR  0x1bdd0000
  71
  72phys_addr_t mips_cpc_default_phys_base(void)
  73{
  74        return DEFAULT_CPC_BASE_ADDR;
  75}
  76
  77phys_addr_t mips_cdmm_phys_base(void)
  78{
  79        return DEFAULT_CDMM_BASE_ADDR;
  80}
  81
  82static void __init mips_nmi_setup(void)
  83{
  84        void *base;
  85
  86        base = cpu_has_veic ?
  87                (void *)(CAC_BASE + 0xa80) :
  88                (void *)(CAC_BASE + 0x380);
  89        memcpy(base, except_vec_nmi, 0x80);
  90        flush_icache_range((unsigned long)base,
  91                           (unsigned long)base + 0x80);
  92}
  93
  94static void __init mips_ejtag_setup(void)
  95{
  96        void *base;
  97        extern char except_vec_ejtag_debug[];
  98
  99        base = cpu_has_veic ?
 100                (void *)(CAC_BASE + 0xa00) :
 101                (void *)(CAC_BASE + 0x300);
 102        memcpy(base, except_vec_ejtag_debug, 0x80);
 103        flush_icache_range((unsigned long)base,
 104                           (unsigned long)base + 0x80);
 105}
 106
 107void __init prom_init(void)
 108{
 109        board_nmi_handler_setup = mips_nmi_setup;
 110        board_ejtag_handler_setup = mips_ejtag_setup;
 111
 112        mips_cm_probe();
 113        mips_cpc_probe();
 114        register_cps_smp_ops();
 115
 116        pr_info("SoC Type: %s\n", get_system_type());
 117}
 118
 119void __init device_tree_init(void)
 120{
 121        if (!initial_boot_params)
 122                return;
 123
 124        unflatten_and_copy_device_tree();
 125}
 126