linux/arch/mips/pci/pci-xlp.c
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   1/*
   2 * Copyright (c) 2003-2012 Broadcom Corporation
   3 * All Rights Reserved
   4 *
   5 * This software is available to you under a choice of one of two
   6 * licenses.  You may choose to be licensed under the terms of the GNU
   7 * General Public License (GPL) Version 2, available from the file
   8 * COPYING in the main directory of this source tree, or the Broadcom
   9 * license below:
  10 *
  11 * Redistribution and use in source and binary forms, with or without
  12 * modification, are permitted provided that the following conditions
  13 * are met:
  14 *
  15 * 1. Redistributions of source code must retain the above copyright
  16 *    notice, this list of conditions and the following disclaimer.
  17 * 2. Redistributions in binary form must reproduce the above copyright
  18 *    notice, this list of conditions and the following disclaimer in
  19 *    the documentation and/or other materials provided with the
  20 *    distribution.
  21 *
  22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
  23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
  26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33 */
  34
  35#include <linux/types.h>
  36#include <linux/pci.h>
  37#include <linux/kernel.h>
  38#include <linux/init.h>
  39#include <linux/msi.h>
  40#include <linux/mm.h>
  41#include <linux/irq.h>
  42#include <linux/irqdesc.h>
  43#include <linux/console.h>
  44
  45#include <asm/io.h>
  46
  47#include <asm/netlogic/interrupt.h>
  48#include <asm/netlogic/haldefs.h>
  49#include <asm/netlogic/common.h>
  50#include <asm/netlogic/mips-extns.h>
  51
  52#include <asm/netlogic/xlp-hal/iomap.h>
  53#include <asm/netlogic/xlp-hal/xlp.h>
  54#include <asm/netlogic/xlp-hal/pic.h>
  55#include <asm/netlogic/xlp-hal/pcibus.h>
  56#include <asm/netlogic/xlp-hal/bridge.h>
  57
  58static void *pci_config_base;
  59
  60#define pci_cfg_addr(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off))
  61
  62/* PCI ops */
  63static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
  64        int where)
  65{
  66        u32 data;
  67        u32 *cfgaddr;
  68
  69        where &= ~3;
  70        if (cpu_is_xlp9xx()) {
  71                /* be very careful on SoC buses */
  72                if (bus->number == 0) {
  73                        /* Scan only existing nodes - uboot bug? */
  74                        if (PCI_SLOT(devfn) != 0 ||
  75                                           !nlm_node_present(PCI_FUNC(devfn)))
  76                                return 0xffffffff;
  77                } else if (bus->parent->number == 0) {  /* SoC bus */
  78                        if (PCI_SLOT(devfn) == 0)       /* b.0.0 hangs */
  79                                return 0xffffffff;
  80                        if (devfn == 44)                /* b.5.4 hangs */
  81                                return 0xffffffff;
  82                }
  83        } else if (bus->number == 0 && PCI_SLOT(devfn) == 1 && where == 0x954) {
  84                return 0xffffffff;
  85        }
  86        cfgaddr = (u32 *)(pci_config_base +
  87                        pci_cfg_addr(bus->number, devfn, where));
  88        data = *cfgaddr;
  89        return data;
  90}
  91
  92static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn,
  93        int where, u32 data)
  94{
  95        u32 *cfgaddr;
  96
  97        cfgaddr = (u32 *)(pci_config_base +
  98                        pci_cfg_addr(bus->number, devfn, where & ~3));
  99        *cfgaddr = data;
 100}
 101
 102static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn,
 103        int where, int size, u32 *val)
 104{
 105        u32 data;
 106
 107        if ((size == 2) && (where & 1))
 108                return PCIBIOS_BAD_REGISTER_NUMBER;
 109        else if ((size == 4) && (where & 3))
 110                return PCIBIOS_BAD_REGISTER_NUMBER;
 111
 112        data = pci_cfg_read_32bit(bus, devfn, where);
 113
 114        if (size == 1)
 115                *val = (data >> ((where & 3) << 3)) & 0xff;
 116        else if (size == 2)
 117                *val = (data >> ((where & 3) << 3)) & 0xffff;
 118        else
 119                *val = data;
 120
 121        return PCIBIOS_SUCCESSFUL;
 122}
 123
 124
 125static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn,
 126                int where, int size, u32 val)
 127{
 128        u32 data;
 129
 130        if ((size == 2) && (where & 1))
 131                return PCIBIOS_BAD_REGISTER_NUMBER;
 132        else if ((size == 4) && (where & 3))
 133                return PCIBIOS_BAD_REGISTER_NUMBER;
 134
 135        data = pci_cfg_read_32bit(bus, devfn, where);
 136
 137        if (size == 1)
 138                data = (data & ~(0xff << ((where & 3) << 3))) |
 139                        (val << ((where & 3) << 3));
 140        else if (size == 2)
 141                data = (data & ~(0xffff << ((where & 3) << 3))) |
 142                        (val << ((where & 3) << 3));
 143        else
 144                data = val;
 145
 146        pci_cfg_write_32bit(bus, devfn, where, data);
 147
 148        return PCIBIOS_SUCCESSFUL;
 149}
 150
 151struct pci_ops nlm_pci_ops = {
 152        .read  = nlm_pcibios_read,
 153        .write = nlm_pcibios_write
 154};
 155
 156static struct resource nlm_pci_mem_resource = {
 157        .name           = "XLP PCI MEM",
 158        .start          = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
 159        .end            = 0xdfffffffUL,
 160        .flags          = IORESOURCE_MEM,
 161};
 162
 163static struct resource nlm_pci_io_resource = {
 164        .name           = "XLP IO MEM",
 165        .start          = 0x14000000UL, /* 64MB PCI IO @ 0x1000_0000 */
 166        .end            = 0x17ffffffUL,
 167        .flags          = IORESOURCE_IO,
 168};
 169
 170struct pci_controller nlm_pci_controller = {
 171        .index          = 0,
 172        .pci_ops        = &nlm_pci_ops,
 173        .mem_resource   = &nlm_pci_mem_resource,
 174        .mem_offset     = 0x00000000UL,
 175        .io_resource    = &nlm_pci_io_resource,
 176        .io_offset      = 0x00000000UL,
 177};
 178
 179struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev)
 180{
 181        struct pci_bus *bus, *p;
 182
 183        bus = dev->bus;
 184
 185        if (cpu_is_xlp9xx()) {
 186                /* find bus with grand parent number == 0 */
 187                for (p = bus->parent; p && p->parent && p->parent->number != 0;
 188                                p = p->parent)
 189                        bus = p;
 190                return (p && p->parent) ? bus->self : NULL;
 191        } else {
 192                /* Find the bridge on bus 0 */
 193                for (p = bus->parent; p && p->number != 0; p = p->parent)
 194                        bus = p;
 195
 196                return p ? bus->self : NULL;
 197        }
 198}
 199
 200int xlp_socdev_to_node(const struct pci_dev *lnkdev)
 201{
 202        if (cpu_is_xlp9xx())
 203                return PCI_FUNC(lnkdev->bus->self->devfn);
 204        else
 205                return PCI_SLOT(lnkdev->devfn) / 8;
 206}
 207
 208int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 209{
 210        struct pci_dev *lnkdev;
 211        int lnkfunc, node;
 212
 213        /*
 214         * For XLP PCIe, there is an IRQ per Link, find out which
 215         * link the device is on to assign interrupts
 216        */
 217        lnkdev = xlp_get_pcie_link(dev);
 218        if (lnkdev == NULL)
 219                return 0;
 220
 221        lnkfunc = PCI_FUNC(lnkdev->devfn);
 222        node = xlp_socdev_to_node(lnkdev);
 223
 224        return nlm_irq_to_xirq(node, PIC_PCIE_LINK_LEGACY_IRQ(lnkfunc));
 225}
 226
 227/* Do platform specific device initialization at pci_enable_device() time */
 228int pcibios_plat_dev_init(struct pci_dev *dev)
 229{
 230        return 0;
 231}
 232
 233/*
 234 * If big-endian, enable hardware byteswap on the PCIe bridges.
 235 * This will make both the SoC and PCIe devices behave consistently with
 236 * readl/writel.
 237 */
 238#ifdef __BIG_ENDIAN
 239static void xlp_config_pci_bswap(int node, int link)
 240{
 241        uint64_t nbubase, lnkbase;
 242        u32 reg;
 243
 244        nbubase = nlm_get_bridge_regbase(node);
 245        lnkbase = nlm_get_pcie_base(node, link);
 246
 247        /*
 248         *  Enable byte swap in hardware. Program each link's PCIe SWAP regions
 249         * from the link's address ranges.
 250         */
 251        if (cpu_is_xlp9xx()) {
 252                reg = nlm_read_bridge_reg(nbubase,
 253                                BRIDGE_9XX_PCIEMEM_BASE0 + link);
 254                nlm_write_pci_reg(lnkbase, PCIE_9XX_BYTE_SWAP_MEM_BASE, reg);
 255
 256                reg = nlm_read_bridge_reg(nbubase,
 257                                BRIDGE_9XX_PCIEMEM_LIMIT0 + link);
 258                nlm_write_pci_reg(lnkbase,
 259                                PCIE_9XX_BYTE_SWAP_MEM_LIM, reg | 0xfff);
 260
 261                reg = nlm_read_bridge_reg(nbubase,
 262                                BRIDGE_9XX_PCIEIO_BASE0 + link);
 263                nlm_write_pci_reg(lnkbase, PCIE_9XX_BYTE_SWAP_IO_BASE, reg);
 264
 265                reg = nlm_read_bridge_reg(nbubase,
 266                                BRIDGE_9XX_PCIEIO_LIMIT0 + link);
 267                nlm_write_pci_reg(lnkbase,
 268                                PCIE_9XX_BYTE_SWAP_IO_LIM, reg | 0xfff);
 269        } else {
 270                reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_BASE0 + link);
 271                nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_BASE, reg);
 272
 273                reg = nlm_read_bridge_reg(nbubase,
 274                                        BRIDGE_PCIEMEM_LIMIT0 + link);
 275                nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_LIM, reg | 0xfff);
 276
 277                reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_BASE0 + link);
 278                nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_BASE, reg);
 279
 280                reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_LIMIT0 + link);
 281                nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff);
 282        }
 283}
 284#else
 285/* Swap configuration not needed in little-endian mode */
 286static inline void xlp_config_pci_bswap(int node, int link) {}
 287#endif /* __BIG_ENDIAN */
 288
 289static int __init pcibios_init(void)
 290{
 291        uint64_t pciebase;
 292        int link, n;
 293        u32 reg;
 294
 295        /* Firmware assigns PCI resources */
 296        pci_set_flags(PCI_PROBE_ONLY);
 297        pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20);
 298
 299        /* Extend IO port for memory mapped io */
 300        ioport_resource.start =  0;
 301        ioport_resource.end   = ~0;
 302
 303        for (n = 0; n < NLM_NR_NODES; n++) {
 304                if (!nlm_node_present(n))
 305                        continue;
 306
 307                for (link = 0; link < PCIE_NLINKS; link++) {
 308                        pciebase = nlm_get_pcie_base(n, link);
 309                        if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff)
 310                                continue;
 311                        xlp_config_pci_bswap(n, link);
 312                        xlp_init_node_msi_irqs(n, link);
 313
 314                        /* put in intpin and irq - u-boot does not */
 315                        reg = nlm_read_pci_reg(pciebase, 0xf);
 316                        reg &= ~0x1ffu;
 317                        reg |= (1 << 8) | PIC_PCIE_LINK_LEGACY_IRQ(link);
 318                        nlm_write_pci_reg(pciebase, 0xf, reg);
 319                        pr_info("XLP PCIe: Link %d-%d initialized.\n", n, link);
 320                }
 321        }
 322
 323        set_io_port_base(CKSEG1);
 324        nlm_pci_controller.io_map_base = CKSEG1;
 325
 326        register_pci_controller(&nlm_pci_controller);
 327        pr_info("XLP PCIe Controller %pR%pR.\n", &nlm_pci_io_resource,
 328                &nlm_pci_mem_resource);
 329
 330        return 0;
 331}
 332arch_initcall(pcibios_init);
 333