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10#include <linux/types.h>
11#include <linux/pci.h>
12#include <linux/io.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/interrupt.h>
16#include <linux/irqdomain.h>
17#include <linux/of.h>
18#include <linux/of_irq.h>
19#include <linux/of_pci.h>
20#include <linux/platform_device.h>
21
22#include <asm/mach-ralink/rt3883.h>
23#include <asm/mach-ralink/ralink_regs.h>
24
25#define RT3883_MEMORY_BASE 0x00000000
26#define RT3883_MEMORY_SIZE 0x02000000
27
28#define RT3883_PCI_REG_PCICFG 0x00
29#define RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf
30#define RT3883_PCICFG_P2P_BR_DEVNUM_S 16
31#define RT3883_PCICFG_PCIRST BIT(1)
32#define RT3883_PCI_REG_PCIRAW 0x04
33#define RT3883_PCI_REG_PCIINT 0x08
34#define RT3883_PCI_REG_PCIENA 0x0c
35
36#define RT3883_PCI_REG_CFGADDR 0x20
37#define RT3883_PCI_REG_CFGDATA 0x24
38#define RT3883_PCI_REG_MEMBASE 0x28
39#define RT3883_PCI_REG_IOBASE 0x2c
40#define RT3883_PCI_REG_ARBCTL 0x80
41
42#define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000)
43#define RT3883_PCI_REG_BAR0SETUP(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10)
44#define RT3883_PCI_REG_IMBASEBAR0(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18)
45#define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30)
46#define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34)
47#define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38)
48#define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50)
49
50#define RT3883_PCI_MODE_NONE 0
51#define RT3883_PCI_MODE_PCI BIT(0)
52#define RT3883_PCI_MODE_PCIE BIT(1)
53#define RT3883_PCI_MODE_BOTH (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE)
54
55#define RT3883_PCI_IRQ_COUNT 32
56
57#define RT3883_P2P_BR_DEVNUM 1
58
59struct rt3883_pci_controller {
60 void __iomem *base;
61
62 struct device_node *intc_of_node;
63 struct irq_domain *irq_domain;
64
65 struct pci_controller pci_controller;
66 struct resource io_res;
67 struct resource mem_res;
68
69 bool pcie_ready;
70};
71
72static inline struct rt3883_pci_controller *
73pci_bus_to_rt3883_controller(struct pci_bus *bus)
74{
75 struct pci_controller *hose;
76
77 hose = (struct pci_controller *) bus->sysdata;
78 return container_of(hose, struct rt3883_pci_controller, pci_controller);
79}
80
81static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc,
82 unsigned reg)
83{
84 return ioread32(rpc->base + reg);
85}
86
87static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc,
88 u32 val, unsigned reg)
89{
90 iowrite32(val, rpc->base + reg);
91}
92
93static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
94 unsigned int func, unsigned int where)
95{
96 return (bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
97 0x80000000;
98}
99
100static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc,
101 unsigned bus, unsigned slot,
102 unsigned func, unsigned reg)
103{
104 u32 address;
105 u32 ret;
106
107 address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
108
109 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
110 ret = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
111
112 return ret;
113}
114
115static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc,
116 unsigned bus, unsigned slot,
117 unsigned func, unsigned reg, u32 val)
118{
119 u32 address;
120
121 address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
122
123 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
124 rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA);
125}
126
127static void rt3883_pci_irq_handler(struct irq_desc *desc)
128{
129 struct rt3883_pci_controller *rpc;
130 u32 pending;
131
132 rpc = irq_desc_get_handler_data(desc);
133
134 pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) &
135 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
136
137 if (!pending) {
138 spurious_interrupt();
139 return;
140 }
141
142 while (pending) {
143 unsigned irq, bit = __ffs(pending);
144
145 irq = irq_find_mapping(rpc->irq_domain, bit);
146 generic_handle_irq(irq);
147
148 pending &= ~BIT(bit);
149 }
150}
151
152static void rt3883_pci_irq_unmask(struct irq_data *d)
153{
154 struct rt3883_pci_controller *rpc;
155 u32 t;
156
157 rpc = irq_data_get_irq_chip_data(d);
158
159 t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
160 rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
161
162 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
163}
164
165static void rt3883_pci_irq_mask(struct irq_data *d)
166{
167 struct rt3883_pci_controller *rpc;
168 u32 t;
169
170 rpc = irq_data_get_irq_chip_data(d);
171
172 t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
173 rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
174
175 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
176}
177
178static struct irq_chip rt3883_pci_irq_chip = {
179 .name = "RT3883 PCI",
180 .irq_mask = rt3883_pci_irq_mask,
181 .irq_unmask = rt3883_pci_irq_unmask,
182 .irq_mask_ack = rt3883_pci_irq_mask,
183};
184
185static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq,
186 irq_hw_number_t hw)
187{
188 irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq);
189 irq_set_chip_data(irq, d->host_data);
190
191 return 0;
192}
193
194static const struct irq_domain_ops rt3883_pci_irq_domain_ops = {
195 .map = rt3883_pci_irq_map,
196 .xlate = irq_domain_xlate_onecell,
197};
198
199static int rt3883_pci_irq_init(struct device *dev,
200 struct rt3883_pci_controller *rpc)
201{
202 int irq;
203
204 irq = irq_of_parse_and_map(rpc->intc_of_node, 0);
205 if (irq == 0) {
206 dev_err(dev, "%pOF has no IRQ", rpc->intc_of_node);
207 return -EINVAL;
208 }
209
210
211 rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA);
212
213 rpc->irq_domain =
214 irq_domain_add_linear(rpc->intc_of_node, RT3883_PCI_IRQ_COUNT,
215 &rt3883_pci_irq_domain_ops,
216 rpc);
217 if (!rpc->irq_domain) {
218 dev_err(dev, "unable to add IRQ domain\n");
219 return -ENODEV;
220 }
221
222 irq_set_chained_handler_and_data(irq, rt3883_pci_irq_handler, rpc);
223
224 return 0;
225}
226
227static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
228 int where, int size, u32 *val)
229{
230 struct rt3883_pci_controller *rpc;
231 u32 address;
232 u32 data;
233
234 rpc = pci_bus_to_rt3883_controller(bus);
235
236 if (!rpc->pcie_ready && bus->number == 1)
237 return PCIBIOS_DEVICE_NOT_FOUND;
238
239 address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
240 PCI_FUNC(devfn), where);
241
242 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
243 data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
244
245 switch (size) {
246 case 1:
247 *val = (data >> ((where & 3) << 3)) & 0xff;
248 break;
249 case 2:
250 *val = (data >> ((where & 3) << 3)) & 0xffff;
251 break;
252 case 4:
253 *val = data;
254 break;
255 }
256
257 return PCIBIOS_SUCCESSFUL;
258}
259
260static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
261 int where, int size, u32 val)
262{
263 struct rt3883_pci_controller *rpc;
264 u32 address;
265 u32 data;
266
267 rpc = pci_bus_to_rt3883_controller(bus);
268
269 if (!rpc->pcie_ready && bus->number == 1)
270 return PCIBIOS_DEVICE_NOT_FOUND;
271
272 address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
273 PCI_FUNC(devfn), where);
274
275 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
276 data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
277
278 switch (size) {
279 case 1:
280 data = (data & ~(0xff << ((where & 3) << 3))) |
281 (val << ((where & 3) << 3));
282 break;
283 case 2:
284 data = (data & ~(0xffff << ((where & 3) << 3))) |
285 (val << ((where & 3) << 3));
286 break;
287 case 4:
288 data = val;
289 break;
290 }
291
292 rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA);
293
294 return PCIBIOS_SUCCESSFUL;
295}
296
297static struct pci_ops rt3883_pci_ops = {
298 .read = rt3883_pci_config_read,
299 .write = rt3883_pci_config_write,
300};
301
302static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode)
303{
304 u32 syscfg1;
305 u32 rstctrl;
306 u32 clkcfg1;
307 u32 t;
308
309 rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
310 syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
311 clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
312
313 if (mode & RT3883_PCI_MODE_PCIE) {
314 rstctrl |= RT3883_RSTCTRL_PCIE;
315 rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
316
317
318 syscfg1 &= ~(0x30);
319 syscfg1 |= (2 << 4);
320 rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
321
322 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
323 t &= ~BIT(31);
324 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
325
326 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
327 t &= 0x80ffffff;
328 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
329
330 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
331 t |= 0xa << 24;
332 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
333
334 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
335 t |= BIT(31);
336 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
337
338 msleep(50);
339
340 rstctrl &= ~RT3883_RSTCTRL_PCIE;
341 rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
342 }
343
344 syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE);
345
346 clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN);
347
348 if (mode & RT3883_PCI_MODE_PCI) {
349 clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
350 rstctrl &= ~RT3883_RSTCTRL_PCI;
351 }
352
353 if (mode & RT3883_PCI_MODE_PCIE) {
354 clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
355 rstctrl &= ~RT3883_RSTCTRL_PCIE;
356 }
357
358 rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
359 rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
360 rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
361
362 msleep(500);
363
364
365
366
367
368 t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S);
369 rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG);
370
371
372 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG);
373 msleep(500);
374
375 if (mode & RT3883_PCI_MODE_PCIE) {
376 msleep(500);
377
378 t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1));
379
380 rpc->pcie_ready = t & BIT(0);
381
382 if (!rpc->pcie_ready) {
383
384 t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
385 t |= RT3883_RSTCTRL_PCIE;
386 rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
387 t &= ~RT3883_RSTCTRL_PCIE;
388 rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
389
390
391 t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
392 t &= ~RT3883_CLKCFG1_PCIE_CLK_EN;
393 rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1);
394
395 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
396 t &= ~0xf000c080;
397 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
398 }
399 }
400
401
402 rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL);
403}
404
405static int rt3883_pci_probe(struct platform_device *pdev)
406{
407 struct rt3883_pci_controller *rpc;
408 struct device *dev = &pdev->dev;
409 struct device_node *np = dev->of_node;
410 struct resource *res;
411 struct device_node *child;
412 u32 val;
413 int err;
414 int mode;
415
416 rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL);
417 if (!rpc)
418 return -ENOMEM;
419
420 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
421 rpc->base = devm_ioremap_resource(dev, res);
422 if (IS_ERR(rpc->base))
423 return PTR_ERR(rpc->base);
424
425
426 for_each_child_of_node(np, child) {
427 if (of_get_property(child, "interrupt-controller", NULL)) {
428 rpc->intc_of_node = child;
429 break;
430 }
431 }
432
433 if (!rpc->intc_of_node) {
434 dev_err(dev, "%pOF has no %s child node",
435 np, "interrupt controller");
436 return -EINVAL;
437 }
438
439
440 for_each_child_of_node(np, child) {
441 if (of_node_is_type(child, "pci")) {
442 rpc->pci_controller.of_node = child;
443 break;
444 }
445 }
446
447 if (!rpc->pci_controller.of_node) {
448 dev_err(dev, "%pOF has no %s child node",
449 np, "PCI host bridge");
450 err = -EINVAL;
451 goto err_put_intc_node;
452 }
453
454 mode = RT3883_PCI_MODE_NONE;
455 for_each_available_child_of_node(rpc->pci_controller.of_node, child) {
456 int devfn;
457
458 if (!of_node_is_type(child, "pci"))
459 continue;
460
461 devfn = of_pci_get_devfn(child);
462 if (devfn < 0)
463 continue;
464
465 switch (PCI_SLOT(devfn)) {
466 case 1:
467 mode |= RT3883_PCI_MODE_PCIE;
468 break;
469
470 case 17:
471 case 18:
472 mode |= RT3883_PCI_MODE_PCI;
473 break;
474 }
475 }
476
477 if (mode == RT3883_PCI_MODE_NONE) {
478 dev_err(dev, "unable to determine PCI mode\n");
479 err = -EINVAL;
480 goto err_put_hb_node;
481 }
482
483 dev_info(dev, "mode:%s%s\n",
484 (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "",
485 (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : "");
486
487 rt3883_pci_preinit(rpc, mode);
488
489 rpc->pci_controller.pci_ops = &rt3883_pci_ops;
490 rpc->pci_controller.io_resource = &rpc->io_res;
491 rpc->pci_controller.mem_resource = &rpc->mem_res;
492
493
494 pci_load_of_ranges(&rpc->pci_controller,
495 rpc->pci_controller.of_node);
496
497 rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE);
498 rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE);
499
500 ioport_resource.start = rpc->io_res.start;
501 ioport_resource.end = rpc->io_res.end;
502
503
504 rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0));
505 rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0));
506 rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0));
507 rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0));
508 rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0));
509
510
511 rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1));
512 rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1));
513 rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1));
514 rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1));
515 rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1));
516
517 err = rt3883_pci_irq_init(dev, rpc);
518 if (err)
519 goto err_put_hb_node;
520
521
522 val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND);
523 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
524 rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val);
525
526
527 val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND);
528 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
529 rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val);
530
531 if (mode == RT3883_PCI_MODE_PCIE) {
532 rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0));
533 rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1));
534
535 rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
536 PCI_BASE_ADDRESS_0,
537 RT3883_MEMORY_BASE);
538
539 rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
540 PCI_BASE_ADDRESS_0);
541 } else {
542 rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
543 PCI_IO_BASE, 0x00000101);
544 }
545
546 register_pci_controller(&rpc->pci_controller);
547
548 return 0;
549
550err_put_hb_node:
551 of_node_put(rpc->pci_controller.of_node);
552err_put_intc_node:
553 of_node_put(rpc->intc_of_node);
554 return err;
555}
556
557int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
558{
559 return of_irq_parse_and_map_pci(dev, slot, pin);
560}
561
562int pcibios_plat_dev_init(struct pci_dev *dev)
563{
564 return 0;
565}
566
567static const struct of_device_id rt3883_pci_ids[] = {
568 { .compatible = "ralink,rt3883-pci" },
569 {},
570};
571
572static struct platform_driver rt3883_pci_driver = {
573 .probe = rt3883_pci_probe,
574 .driver = {
575 .name = "rt3883-pci",
576 .of_match_table = of_match_ptr(rt3883_pci_ids),
577 },
578};
579
580static int __init rt3883_pci_init(void)
581{
582 return platform_driver_register(&rt3883_pci_driver);
583}
584
585postcore_initcall(rt3883_pci_init);
586
