linux/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
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   1/*
   2 * Copyright (c) 2003-2012 Broadcom Corporation
   3 * All Rights Reserved
   4 *
   5 * This software is available to you under a choice of one of two
   6 * licenses.  You may choose to be licensed under the terms of the GNU
   7 * General Public License (GPL) Version 2, available from the file
   8 * COPYING in the main directory of this source tree, or the Broadcom
   9 * license below:
  10 *
  11 * Redistribution and use in source and binary forms, with or without
  12 * modification, are permitted provided that the following conditions
  13 * are met:
  14 *
  15 * 1. Redistributions of source code must retain the above copyright
  16 *    notice, this list of conditions and the following disclaimer.
  17 * 2. Redistributions in binary form must reproduce the above copyright
  18 *    notice, this list of conditions and the following disclaimer in
  19 *    the documentation and/or other materials provided with the
  20 *    distribution.
  21 *
  22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
  23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
  26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33 */
  34
  35#ifndef __NLM_HAL_PCIBUS_H__
  36#define __NLM_HAL_PCIBUS_H__
  37
  38/* PCIE Memory and IO regions */
  39#define PCIE_MEM_BASE                   0xd0000000ULL
  40#define PCIE_MEM_LIMIT                  0xdfffffffULL
  41#define PCIE_IO_BASE                    0x14000000ULL
  42#define PCIE_IO_LIMIT                   0x15ffffffULL
  43
  44#define PCIE_BRIDGE_CMD                 0x1
  45#define PCIE_BRIDGE_MSI_CAP             0x14
  46#define PCIE_BRIDGE_MSI_ADDRL           0x15
  47#define PCIE_BRIDGE_MSI_ADDRH           0x16
  48#define PCIE_BRIDGE_MSI_DATA            0x17
  49
  50/* XLP Global PCIE configuration space registers */
  51#define PCIE_BYTE_SWAP_MEM_BASE         0x247
  52#define PCIE_BYTE_SWAP_MEM_LIM          0x248
  53#define PCIE_BYTE_SWAP_IO_BASE          0x249
  54#define PCIE_BYTE_SWAP_IO_LIM           0x24A
  55
  56#define PCIE_BRIDGE_MSIX_ADDR_BASE      0x24F
  57#define PCIE_BRIDGE_MSIX_ADDR_LIMIT     0x250
  58#define PCIE_MSI_STATUS                 0x25A
  59#define PCIE_MSI_EN                     0x25B
  60#define PCIE_MSIX_STATUS                0x25D
  61#define PCIE_INT_STATUS0                0x25F
  62#define PCIE_INT_STATUS1                0x260
  63#define PCIE_INT_EN0                    0x261
  64#define PCIE_INT_EN1                    0x262
  65
  66/* XLP9XX has basic changes */
  67#define PCIE_9XX_BYTE_SWAP_MEM_BASE     0x25c
  68#define PCIE_9XX_BYTE_SWAP_MEM_LIM      0x25d
  69#define PCIE_9XX_BYTE_SWAP_IO_BASE      0x25e
  70#define PCIE_9XX_BYTE_SWAP_IO_LIM       0x25f
  71
  72#define PCIE_9XX_BRIDGE_MSIX_ADDR_BASE  0x264
  73#define PCIE_9XX_BRIDGE_MSIX_ADDR_LIMIT 0x265
  74#define PCIE_9XX_MSI_STATUS             0x283
  75#define PCIE_9XX_MSI_EN                 0x284
  76/* 128 MSIX vectors available in 9xx */
  77#define PCIE_9XX_MSIX_STATUS0           0x286
  78#define PCIE_9XX_MSIX_STATUSX(n)        (n + 0x286)
  79#define PCIE_9XX_MSIX_VEC               0x296
  80#define PCIE_9XX_MSIX_VECX(n)           (n + 0x296)
  81#define PCIE_9XX_INT_STATUS0            0x397
  82#define PCIE_9XX_INT_STATUS1            0x398
  83#define PCIE_9XX_INT_EN0                0x399
  84#define PCIE_9XX_INT_EN1                0x39a
  85
  86/* other */
  87#define PCIE_NLINKS                     4
  88
  89/* MSI addresses */
  90#define MSI_ADDR_BASE                   0xfffee00000ULL
  91#define MSI_ADDR_SZ                     0x10000
  92#define MSI_LINK_ADDR(n, l)             (MSI_ADDR_BASE + \
  93                                (PCIE_NLINKS * (n) + (l)) * MSI_ADDR_SZ)
  94#define MSIX_ADDR_BASE                  0xfffef00000ULL
  95#define MSIX_LINK_ADDR(n, l)            (MSIX_ADDR_BASE + \
  96                                (PCIE_NLINKS * (n) + (l)) * MSI_ADDR_SZ)
  97#ifndef __ASSEMBLY__
  98
  99#define nlm_read_pcie_reg(b, r)         nlm_read_reg(b, r)
 100#define nlm_write_pcie_reg(b, r, v)     nlm_write_reg(b, r, v)
 101#define nlm_get_pcie_base(node, inst)   nlm_pcicfg_base(cpu_is_xlp9xx() ? \
 102        XLP9XX_IO_PCIE_OFFSET(node, inst) : XLP_IO_PCIE_OFFSET(node, inst))
 103
 104#ifdef CONFIG_PCI_MSI
 105void xlp_init_node_msi_irqs(int node, int link);
 106#else
 107static inline void xlp_init_node_msi_irqs(int node, int link) {}
 108#endif
 109
 110struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev);
 111
 112#endif
 113#endif /* __NLM_HAL_PCIBUS_H__ */
 114