LXR linux/drivers/net/ethernet/chelsio/cxgb4/t4

   1/*
   2 * This file is part of the Chelsio T4/T5/T6 Ethernet driver for Linux.
   3 *
   4 * Copyright (c) 2017 Chelsio Communications, Inc. All rights reserved.
   5 *
   6 * This software is available to you under a choice of one of two
   7 * licenses.  You may choose to be licensed under the terms of the GNU
   8 * General Public License (GPL) Version 2, available from the file
   9 * COPYING in the main directory of this source tree, or the
  10 * OpenIB.org BSD license below:
  11 *
  12 *     Redistribution and use in source and binary forms, with or
  13 *     without modification, are permitted provided that the following
  14 *     conditions are met:
  15 *
  16 *      - Redistributions of source code must retain the above
  17 *        copyright notice, this list of conditions and the following
  18 *        disclaimer.
  19 *
  20 *      - Redistributions in binary form must reproduce the above
  21 *        copyright notice, this list of conditions and the following
  22 *        disclaimer in the documentation and/or other materials
  23 *        provided with the distribution.
  24 *
  25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32 * SOFTWARE.
  33 */
  34
  35#ifndef __T4_TCB_H
  36#define __T4_TCB_H
  37
  38#define TCB_L2T_IX_W            0
  39#define TCB_L2T_IX_S            12
  40#define TCB_L2T_IX_M            0xfffULL
  41#define TCB_L2T_IX_V(x)         ((x) << TCB_L2T_IX_S)
  42
  43#define TCB_T_FLAGS_W           1
  44#define TCB_T_FLAGS_S           0
  45#define TCB_T_FLAGS_M           0xffffffffffffffffULL
  46#define TCB_T_FLAGS_V(x)        ((__u64)(x) << TCB_T_FLAGS_S)
  47
  48#define TCB_FIELD_COOKIE_TFLAG  1
  49
  50#define TCB_SMAC_SEL_W          0
  51#define TCB_SMAC_SEL_S          24
  52#define TCB_SMAC_SEL_M          0xffULL
  53#define TCB_SMAC_SEL_V(x)       ((x) << TCB_SMAC_SEL_S)
  54
  55#define TCB_T_FLAGS_W           1
  56#define TCB_T_FLAGS_S           0
  57#define TCB_T_FLAGS_M           0xffffffffffffffffULL
  58#define TCB_T_FLAGS_V(x)        ((__u64)(x) << TCB_T_FLAGS_S)
  59
  60#define TF_DROP_S               22
  61#define TF_DIRECT_STEER_S       23
  62#define TF_LPBK_S               59
  63
  64#define TF_CCTRL_ECE_S          60
  65#define TF_CCTRL_CWR_S          61
  66#define TF_CCTRL_RFR_S          62
  67
  68#define TCB_RSS_INFO_W          3
  69#define TCB_RSS_INFO_S          0
  70#define TCB_RSS_INFO_M          0x3ffULL
  71#define TCB_RSS_INFO_V(x)       ((x) << TCB_RSS_INFO_S)
  72
  73#define TCB_T_STATE_W           3
  74#define TCB_T_STATE_S           16
  75#define TCB_T_STATE_M           0xfULL
  76#define TCB_T_STATE_V(x)        ((x) << TCB_T_STATE_S)
  77
  78#define TCB_TIMESTAMP_W         5
  79#define TCB_TIMESTAMP_S         0
  80#define TCB_TIMESTAMP_M         0xffffffffULL
  81#define TCB_TIMESTAMP_V(x)      ((x) << TCB_TIMESTAMP_S)
  82
  83#define TCB_RTT_TS_RECENT_AGE_W         6
  84#define TCB_RTT_TS_RECENT_AGE_S         0
  85#define TCB_RTT_TS_RECENT_AGE_M         0xffffffffULL
  86#define TCB_RTT_TS_RECENT_AGE_V(x)      ((x) << TCB_RTT_TS_RECENT_AGE_S)
  87
  88#define TCB_T_RTSEQ_RECENT_W    7
  89#define TCB_T_RTSEQ_RECENT_S    0
  90#define TCB_T_RTSEQ_RECENT_M    0xffffffffULL
  91#define TCB_T_RTSEQ_RECENT_V(x) ((x) << TCB_T_RTSEQ_RECENT_S)
  92
  93#define TCB_TX_MAX_W            9
  94#define TCB_TX_MAX_S            0
  95#define TCB_TX_MAX_M            0xffffffffULL
  96#define TCB_TX_MAX_V(x)         ((x) << TCB_TX_MAX_S)
  97
  98#define TCB_SND_UNA_RAW_W       10
  99#define TCB_SND_UNA_RAW_S       0
 100#define TCB_SND_UNA_RAW_M       0xfffffffULL
 101#define TCB_SND_UNA_RAW_V(x)    ((x) << TCB_SND_UNA_RAW_S)
 102
 103#define TCB_SND_NXT_RAW_W       10
 104#define TCB_SND_NXT_RAW_S       28
 105#define TCB_SND_NXT_RAW_M       0xfffffffULL
 106#define TCB_SND_NXT_RAW_V(x)    ((x) << TCB_SND_NXT_RAW_S)
 107
 108#define TCB_SND_MAX_RAW_W       11
 109#define TCB_SND_MAX_RAW_S       24
 110#define TCB_SND_MAX_RAW_M       0xfffffffULL
 111#define TCB_SND_MAX_RAW_V(x)    ((x) << TCB_SND_MAX_RAW_S)
 112
 113#define TCB_RCV_NXT_W           16
 114#define TCB_RCV_NXT_S           10
 115#define TCB_RCV_NXT_M           0xffffffffULL
 116#define TCB_RCV_NXT_V(x)        ((x) << TCB_RCV_NXT_S)
 117
 118#define TCB_RCV_WND_W           17
 119#define TCB_RCV_WND_S           10
 120#define TCB_RCV_WND_M           0xffffffULL
 121#define TCB_RCV_WND_V(x)        ((x) << TCB_RCV_WND_S)
 122
 123#define TCB_RX_FRAG2_PTR_RAW_W  27
 124#define TCB_RX_FRAG3_LEN_RAW_W  29
 125#define TCB_RX_FRAG3_START_IDX_OFFSET_RAW_W     30
 126#define TCB_PDU_HDR_LEN_W       31
 127
 128#define TCB_RQ_START_W          30
 129#define TCB_RQ_START_S          0
 130#define TCB_RQ_START_M          0x3ffffffULL
 131#define TCB_RQ_START_V(x)       ((x) << TCB_RQ_START_S)
 132
 133#define TF_RX_PDU_OUT_S         49
 134#define TF_RX_PDU_OUT_V(x)      ((__u64)(x) << TF_RX_PDU_OUT_S)
 135
 136#define TF_CORE_BYPASS_S        63
 137#define TF_CORE_BYPASS_V(x)     ((__u64)(x) << TF_CORE_BYPASS_S)
 138#define TF_CORE_BYPASS_F        TF_CORE_BYPASS_V(1)
 139
 140#define TF_NON_OFFLOAD_S        1
 141#define TF_NON_OFFLOAD_V(x)     ((x) << TF_NON_OFFLOAD_S)
 142#define TF_NON_OFFLOAD_F        TF_NON_OFFLOAD_V(1)
 143
 144#endif /* __T4_TCB_H */
 145