linux/drivers/misc/habanalabs/include/goya/asic_reg/
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cpu_ca53_cfg_masks.h 11062 2021-08-29 15:04:50 -0700
cpu_ca53_cfg_regs.h 2020 2021-08-29 15:04:50 -0700
cpu_if_regs.h 1520 2021-08-29 15:04:50 -0700
cpu_pll_regs.h 3733 2021-08-29 15:04:50 -0700
dma_ch_0_masks.h 19405 2021-08-29 15:04:50 -0700
dma_ch_0_regs.h 7848 2021-08-29 15:04:50 -0700
dma_ch_1_regs.h 7848 2021-08-29 15:04:50 -0700
dma_ch_2_regs.h 7848 2021-08-29 15:04:50 -0700
dma_ch_3_regs.h 7848 2021-08-29 15:04:50 -0700
dma_ch_4_regs.h 7848 2021-08-29 15:04:50 -0700
dma_macro_masks.h 4146 2021-08-29 15:04:50 -0700
dma_macro_regs.h 6749 2021-08-29 15:04:50 -0700
dma_nrtr_masks.h 10312 2021-08-29 15:04:50 -0700
dma_nrtr_regs.h 8560 2021-08-29 15:04:50 -0700
dma_qm_0_masks.h 23975 2021-08-29 15:04:50 -0700
dma_qm_0_regs.h 6661 2021-08-29 15:04:50 -0700
dma_qm_1_regs.h 6661 2021-08-29 15:04:50 -0700
dma_qm_2_regs.h 6661 2021-08-29 15:04:50 -0700
dma_qm_3_regs.h 6661 2021-08-29 15:04:50 -0700
dma_qm_4_regs.h 6661 2021-08-29 15:04:50 -0700
goya_blocks.h 82732 2021-08-29 15:04:50 -0700
goya_masks.h 10138 2021-08-29 15:04:50 -0700
goya_regs.h 3647 2021-08-29 15:04:50 -0700
ic_pll_regs.h 3729 2021-08-29 15:04:50 -0700
mc_pll_regs.h 3729 2021-08-29 15:04:50 -0700
mme1_rtr_masks.h 37014 2021-08-29 15:04:50 -0700
mme1_rtr_regs.h 12514 2021-08-29 15:04:50 -0700
mme2_rtr_regs.h 12514 2021-08-29 15:04:50 -0700
mme3_rtr_regs.h 12514 2021-08-29 15:04:50 -0700
mme4_rtr_regs.h 12668 2021-08-29 15:04:50 -0700
mme5_rtr_regs.h 12668 2021-08-29 15:04:50 -0700
mme6_rtr_regs.h 12668 2021-08-29 15:04:50 -0700
mme_cmdq_masks.h 19549 2021-08-29 15:04:50 -0700
mme_cmdq_regs.h 5023 2021-08-29 15:04:50 -0700
mme_masks.h 85229 2021-08-29 15:04:50 -0700
mme_qm_masks.h 23811 2021-08-29 15:04:50 -0700
mme_qm_regs.h 6575 2021-08-29 15:04:50 -0700
mme_regs.h 44548 2021-08-29 15:04:50 -0700
mmu_masks.h 7476 2021-08-29 15:04:50 -0700
mmu_regs.h 1663 2021-08-29 15:04:50 -0700
pci_nrtr_masks.h 10312 2021-08-29 15:04:50 -0700
pci_nrtr_regs.h 8254 2021-08-29 15:04:50 -0700
pcie_aux_regs.h 9193 2021-08-29 15:04:50 -0700
pcie_wrap_regs.h 11726 2021-08-29 15:04:50 -0700
psoc_emmc_pll_regs.h 3757 2021-08-29 15:04:50 -0700
psoc_etr_regs.h 4178 2021-08-29 15:04:50 -0700
psoc_global_conf_masks.h 26041 2021-08-29 15:04:50 -0700
psoc_global_conf_regs.h 29057 2021-08-29 15:04:50 -0700
psoc_mme_pll_regs.h 3753 2021-08-29 15:04:50 -0700
psoc_pci_pll_regs.h 3753 2021-08-29 15:04:50 -0700
psoc_spi_regs.h 5238 2021-08-29 15:04:50 -0700
psoc_timestamp_regs.h 1871 2021-08-29 15:04:50 -0700
sram_y0_x0_rtr_regs.h 2895 2021-08-29 15:04:50 -0700
sram_y0_x1_rtr_regs.h 2895 2021-08-29 15:04:50 -0700
sram_y0_x2_rtr_regs.h 2895 2021-08-29 15:04:50 -0700
sram_y0_x3_rtr_regs.h 2895 2021-08-29 15:04:50 -0700
sram_y0_x4_rtr_regs.h 2895 2021-08-29 15:04:50 -0700
stlb_masks.h 5432 2021-08-29 15:04:50 -0700
stlb_regs.h 1747 2021-08-29 15:04:50 -0700
tpc0_cfg_masks.h 80427 2021-08-29 15:04:50 -0700
tpc0_cfg_regs.h 34626 2021-08-29 15:04:50 -0700
tpc0_cmdq_masks.h 19611 2021-08-29 15:04:50 -0700
tpc0_cmdq_regs.h 5085 2021-08-29 15:04:50 -0700
tpc0_eml_cfg_masks.h 17981 2021-08-29 15:04:50 -0700
tpc0_eml_cfg_regs.h 12122 2021-08-29 15:04:50 -0700
tpc0_nrtr_masks.h 10349 2021-08-29 15:04:50 -0700
tpc0_nrtr_regs.h 8564 2021-08-29 15:04:50 -0700
tpc0_qm_masks.h 23893 2021-08-29 15:04:50 -0700
tpc0_qm_regs.h 6657 2021-08-29 15:04:50 -0700
tpc1_cfg_regs.h 34626 2021-08-29 15:04:50 -0700
tpc1_cmdq_regs.h 5085 2021-08-29 15:04:50 -0700
tpc1_qm_regs.h 6657 2021-08-29 15:04:50 -0700
tpc1_rtr_regs.h 12352 2021-08-29 15:04:50 -0700
tpc2_cfg_regs.h 34626 2021-08-29 15:04:50 -0700
tpc2_cmdq_regs.h 5085 2021-08-29 15:04:50 -0700
tpc2_qm_regs.h 6657 2021-08-29 15:04:50 -0700
tpc2_rtr_regs.h 12352 2021-08-29 15:04:50 -0700
tpc3_cfg_regs.h 34626 2021-08-29 15:04:50 -0700
tpc3_cmdq_regs.h 5085 2021-08-29 15:04:50 -0700
tpc3_qm_regs.h 6657 2021-08-29 15:04:50 -0700
tpc3_rtr_regs.h 12352 2021-08-29 15:04:50 -0700
tpc4_cfg_regs.h 34626 2021-08-29 15:04:50 -0700
tpc4_cmdq_regs.h 5085 2021-08-29 15:04:50 -0700
tpc4_qm_regs.h 6657 2021-08-29 15:04:50 -0700
tpc4_rtr_regs.h 12352 2021-08-29 15:04:50 -0700
tpc5_cfg_regs.h 34626 2021-08-29 15:04:50 -0700
tpc5_cmdq_regs.h 5085 2021-08-29 15:04:50 -0700
tpc5_qm_regs.h 6657 2021-08-29 15:04:50 -0700
tpc5_rtr_regs.h 12352 2021-08-29 15:04:50 -0700
tpc6_cfg_regs.h 34626 2021-08-29 15:04:50 -0700
tpc6_cmdq_regs.h 5085 2021-08-29 15:04:50 -0700
tpc6_qm_regs.h 6657 2021-08-29 15:04:50 -0700
tpc6_rtr_regs.h 12352 2021-08-29 15:04:50 -0700
tpc7_cfg_regs.h 34626 2021-08-29 15:04:50 -0700
tpc7_cmdq_regs.h 5085 2021-08-29 15:04:50 -0700
tpc7_nrtr_regs.h 8564 2021-08-29 15:04:50 -0700
tpc7_qm_regs.h 6657 2021-08-29 15:04:50 -0700
tpc_pll_regs.h 3733 2021-08-29 15:04:50 -0700