linux/Documentation/spi/pxa2xx.rst
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   2PXA2xx SPI on SSP driver HOWTO
   3==============================
   4
   5This a mini HOWTO on the pxa2xx_spi driver. The driver turns a PXA2xx
   6synchronous serial port into an SPI master controller
   7(see Documentation/spi/spi-summary.rst). The driver has the following features
   8
   9- Support for any PXA2xx and compatible SSP.
  10- SSP PIO and SSP DMA data transfers.
  11- External and Internal (SSPFRM) chip selects.
  12- Per slave device (chip) configuration.
  13- Full suspend, freeze, resume support.
  14
  15The driver is built around a &struct spi_message FIFO serviced by kernel
  16thread. The kernel thread, spi_pump_messages(), drives message FIFO and
  17is responsible for queuing SPI transactions and setting up and launching
  18the DMA or interrupt driven transfers.
  19
  20Declaring PXA2xx Master Controllers
  21-----------------------------------
  22Typically, for a legacy platform, an SPI master is defined in the
  23arch/.../mach-*/board-*.c as a "platform device". The master configuration
  24is passed to the driver via a table found in include/linux/spi/pxa2xx_spi.h::
  25
  26  struct pxa2xx_spi_controller {
  27        u16 num_chipselect;
  28        u8 enable_dma;
  29        ...
  30  };
  31
  32The "pxa2xx_spi_controller.num_chipselect" field is used to determine the number of
  33slave device (chips) attached to this SPI master.
  34
  35The "pxa2xx_spi_controller.enable_dma" field informs the driver that SSP DMA should
  36be used. This caused the driver to acquire two DMA channels: Rx channel and
  37Tx channel. The Rx channel has a higher DMA service priority than the Tx channel.
  38See the "PXA2xx Developer Manual" section "DMA Controller".
  39
  40For the new platforms the description of the controller and peripheral devices
  41comes from Device Tree or ACPI.
  42
  43NSSP MASTER SAMPLE
  44------------------
  45Below is a sample configuration using the PXA255 NSSP for a legacy platform::
  46
  47  static struct resource pxa_spi_nssp_resources[] = {
  48        [0] = {
  49                .start  = __PREG(SSCR0_P(2)), /* Start address of NSSP */
  50                .end    = __PREG(SSCR0_P(2)) + 0x2c, /* Range of registers */
  51                .flags  = IORESOURCE_MEM,
  52        },
  53        [1] = {
  54                .start  = IRQ_NSSP, /* NSSP IRQ */
  55                .end    = IRQ_NSSP,
  56                .flags  = IORESOURCE_IRQ,
  57        },
  58  };
  59
  60  static struct pxa2xx_spi_controller pxa_nssp_master_info = {
  61        .num_chipselect = 1, /* Matches the number of chips attached to NSSP */
  62        .enable_dma = 1, /* Enables NSSP DMA */
  63  };
  64
  65  static struct platform_device pxa_spi_nssp = {
  66        .name = "pxa2xx-spi", /* MUST BE THIS VALUE, so device match driver */
  67        .id = 2, /* Bus number, MUST MATCH SSP number 1..n */
  68        .resource = pxa_spi_nssp_resources,
  69        .num_resources = ARRAY_SIZE(pxa_spi_nssp_resources),
  70        .dev = {
  71                .platform_data = &pxa_nssp_master_info, /* Passed to driver */
  72        },
  73  };
  74
  75  static struct platform_device *devices[] __initdata = {
  76        &pxa_spi_nssp,
  77  };
  78
  79  static void __init board_init(void)
  80  {
  81        (void)platform_add_device(devices, ARRAY_SIZE(devices));
  82  }
  83
  84Declaring Slave Devices
  85-----------------------
  86Typically, for a legacy platform, each SPI slave (chip) is defined in the
  87arch/.../mach-*/board-*.c using the "spi_board_info" structure found in
  88"linux/spi/spi.h". See "Documentation/spi/spi-summary.rst" for additional
  89information.
  90
  91Each slave device attached to the PXA must provide slave specific configuration
  92information via the structure "pxa2xx_spi_chip" found in
  93"include/linux/spi/pxa2xx_spi.h".  The pxa2xx_spi master controller driver
  94will uses the configuration whenever the driver communicates with the slave
  95device. All fields are optional.
  96
  97::
  98
  99  struct pxa2xx_spi_chip {
 100        u8 tx_threshold;
 101        u8 rx_threshold;
 102        u8 dma_burst_size;
 103        u32 timeout;
 104        u8 enable_loopback;
 105        void (*cs_control)(u32 command);
 106  };
 107
 108The "pxa2xx_spi_chip.tx_threshold" and "pxa2xx_spi_chip.rx_threshold" fields are
 109used to configure the SSP hardware FIFO. These fields are critical to the
 110performance of pxa2xx_spi driver and misconfiguration will result in rx
 111FIFO overruns (especially in PIO mode transfers). Good default values are::
 112
 113        .tx_threshold = 8,
 114        .rx_threshold = 8,
 115
 116The range is 1 to 16 where zero indicates "use default".
 117
 118The "pxa2xx_spi_chip.dma_burst_size" field is used to configure PXA2xx DMA
 119engine and is related the "spi_device.bits_per_word" field.  Read and understand
 120the PXA2xx "Developer Manual" sections on the DMA controller and SSP Controllers
 121to determine the correct value. An SSP configured for byte-wide transfers would
 122use a value of 8. The driver will determine a reasonable default if
 123dma_burst_size == 0.
 124
 125The "pxa2xx_spi_chip.timeout" fields is used to efficiently handle
 126trailing bytes in the SSP receiver FIFO. The correct value for this field is
 127dependent on the SPI bus speed ("spi_board_info.max_speed_hz") and the specific
 128slave device.  Please note that the PXA2xx SSP 1 does not support trailing byte
 129timeouts and must busy-wait any trailing bytes.
 130
 131The "pxa2xx_spi_chip.enable_loopback" field is used to place the SSP porting
 132into internal loopback mode.  In this mode the SSP controller internally
 133connects the SSPTX pin to the SSPRX pin.  This is useful for initial setup
 134testing.
 135
 136The "pxa2xx_spi_chip.cs_control" field is used to point to a board specific
 137function for asserting/deasserting a slave device chip select.  If the field is
 138NULL, the pxa2xx_spi master controller driver assumes that the SSP port is
 139configured to use GPIO or SSPFRM instead.
 140
 141NOTE: the SPI driver cannot control the chip select if SSPFRM is used, so the
 142chipselect is dropped after each spi_transfer.  Most devices need chip select
 143asserted around the complete message. Use SSPFRM as a GPIO (through a descriptor)
 144to accommodate these chips.
 145
 146
 147NSSP SLAVE SAMPLE
 148-----------------
 149For a legacy platform or in some other cases, the pxa2xx_spi_chip structure
 150is passed to the pxa2xx_spi driver in the "spi_board_info.controller_data"
 151field. Below is a sample configuration using the PXA255 NSSP.
 152
 153::
 154
 155  /* Chip Select control for the CS8415A SPI slave device */
 156  static void cs8415a_cs_control(u32 command)
 157  {
 158        if (command & PXA2XX_CS_ASSERT)
 159                GPCR(2) = GPIO_bit(2);
 160        else
 161                GPSR(2) = GPIO_bit(2);
 162  }
 163
 164  /* Chip Select control for the CS8405A SPI slave device */
 165  static void cs8405a_cs_control(u32 command)
 166  {
 167        if (command & PXA2XX_CS_ASSERT)
 168                GPCR(3) = GPIO_bit(3);
 169        else
 170                GPSR(3) = GPIO_bit(3);
 171  }
 172
 173  static struct pxa2xx_spi_chip cs8415a_chip_info = {
 174        .tx_threshold = 8, /* SSP hardward FIFO threshold */
 175        .rx_threshold = 8, /* SSP hardward FIFO threshold */
 176        .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
 177        .timeout = 235, /* See Intel documentation */
 178        .cs_control = cs8415a_cs_control, /* Use external chip select */
 179  };
 180
 181  static struct pxa2xx_spi_chip cs8405a_chip_info = {
 182        .tx_threshold = 8, /* SSP hardward FIFO threshold */
 183        .rx_threshold = 8, /* SSP hardward FIFO threshold */
 184        .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
 185        .timeout = 235, /* See Intel documentation */
 186        .cs_control = cs8405a_cs_control, /* Use external chip select */
 187  };
 188
 189  static struct spi_board_info streetracer_spi_board_info[] __initdata = {
 190        {
 191                .modalias = "cs8415a", /* Name of spi_driver for this device */
 192                .max_speed_hz = 3686400, /* Run SSP as fast a possbile */
 193                .bus_num = 2, /* Framework bus number */
 194                .chip_select = 0, /* Framework chip select */
 195                .platform_data = NULL; /* No spi_driver specific config */
 196                .controller_data = &cs8415a_chip_info, /* Master chip config */
 197                .irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */
 198        },
 199        {
 200                .modalias = "cs8405a", /* Name of spi_driver for this device */
 201                .max_speed_hz = 3686400, /* Run SSP as fast a possbile */
 202                .bus_num = 2, /* Framework bus number */
 203                .chip_select = 1, /* Framework chip select */
 204                .controller_data = &cs8405a_chip_info, /* Master chip config */
 205                .irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */
 206        },
 207  };
 208
 209  static void __init streetracer_init(void)
 210  {
 211        spi_register_board_info(streetracer_spi_board_info,
 212                                ARRAY_SIZE(streetracer_spi_board_info));
 213  }
 214
 215
 216DMA and PIO I/O Support
 217-----------------------
 218The pxa2xx_spi driver supports both DMA and interrupt driven PIO message
 219transfers.  The driver defaults to PIO mode and DMA transfers must be enabled
 220by setting the "enable_dma" flag in the "pxa2xx_spi_controller" structure.
 221For the newer platforms, that are known to support DMA, the driver will enable
 222it automatically and try it first with a possible fallback to PIO. The DMA
 223mode supports both coherent and stream based DMA mappings.
 224
 225The following logic is used to determine the type of I/O to be used on
 226a per "spi_transfer" basis::
 227
 228  if !enable_dma then
 229        always use PIO transfers
 230
 231  if spi_message.len > 8191 then
 232        print "rate limited" warning
 233        use PIO transfers
 234
 235  if spi_message.is_dma_mapped and rx_dma_buf != 0 and tx_dma_buf != 0 then
 236        use coherent DMA mode
 237
 238  if rx_buf and tx_buf are aligned on 8 byte boundary then
 239        use streaming DMA mode
 240
 241  otherwise
 242        use PIO transfer
 243
 244THANKS TO
 245---------
 246David Brownell and others for mentoring the development of this driver.
 247