linux/include/drm/drm_dp_helper.h
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   1/*
   2 * Copyright \xC2\xA9 2008 Keith Packard
   3 *
   4 * Permission to use, copy, modify, distribute, and sell this software and its
   5 * documentation for any purpose is hereby granted without fee, provided that
   6 * the above copyright notice appear in all copies and that both that copyright
   7 * notice and this permission notice appear in supporting documentation, and
   8 * that the name of the copyright holders not be used in advertising or
   9 * publicity pertaining to distribution of the software without specific,
  10 * written prior permission.  The copyright holders make no representations
  11 * about the suitability of this software for any purpose.  It is provided "as
  12 * is" without express or implied warranty.
  13 *
  14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
  15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
  16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
  17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
  18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
  20 * OF THIS SOFTWARE.
  21 */
  22
  23#ifndef _DRM_DP_HELPER_H_
  24#define _DRM_DP_HELPER_H_
  25
  26#include <linux/delay.h>
  27#include <linux/i2c.h>
  28#include <linux/types.h>
  29#include <drm/drm_connector.h>
  30
  31struct drm_device;
  32
  33/*
  34 * Unless otherwise noted, all values are from the DP 1.1a spec.  Note that
  35 * DP and DPCD versions are independent.  Differences from 1.0 are not noted,
  36 * 1.0 devices basically don't exist in the wild.
  37 *
  38 * Abbreviations, in chronological order:
  39 *
  40 * eDP: Embedded DisplayPort version 1
  41 * DPI: DisplayPort Interoperability Guideline v1.1a
  42 * 1.2: DisplayPort 1.2
  43 * MST: Multistream Transport - part of DP 1.2a
  44 *
  45 * 1.2 formally includes both eDP and DPI definitions.
  46 */
  47
  48/* MSA (Main Stream Attribute) MISC bits (as MISC1<<8|MISC0) */
  49#define DP_MSA_MISC_SYNC_CLOCK                  (1 << 0)
  50#define DP_MSA_MISC_INTERLACE_VTOTAL_EVEN       (1 << 8)
  51#define DP_MSA_MISC_STEREO_NO_3D                (0 << 9)
  52#define DP_MSA_MISC_STEREO_PROG_RIGHT_EYE       (1 << 9)
  53#define DP_MSA_MISC_STEREO_PROG_LEFT_EYE        (3 << 9)
  54/* bits per component for non-RAW */
  55#define DP_MSA_MISC_6_BPC                       (0 << 5)
  56#define DP_MSA_MISC_8_BPC                       (1 << 5)
  57#define DP_MSA_MISC_10_BPC                      (2 << 5)
  58#define DP_MSA_MISC_12_BPC                      (3 << 5)
  59#define DP_MSA_MISC_16_BPC                      (4 << 5)
  60/* bits per component for RAW */
  61#define DP_MSA_MISC_RAW_6_BPC                   (1 << 5)
  62#define DP_MSA_MISC_RAW_7_BPC                   (2 << 5)
  63#define DP_MSA_MISC_RAW_8_BPC                   (3 << 5)
  64#define DP_MSA_MISC_RAW_10_BPC                  (4 << 5)
  65#define DP_MSA_MISC_RAW_12_BPC                  (5 << 5)
  66#define DP_MSA_MISC_RAW_14_BPC                  (6 << 5)
  67#define DP_MSA_MISC_RAW_16_BPC                  (7 << 5)
  68/* pixel encoding/colorimetry format */
  69#define _DP_MSA_MISC_COLOR(misc1_7, misc0_21, misc0_3, misc0_4) \
  70        ((misc1_7) << 15 | (misc0_4) << 4 | (misc0_3) << 3 | ((misc0_21) << 1))
  71#define DP_MSA_MISC_COLOR_RGB                   _DP_MSA_MISC_COLOR(0, 0, 0, 0)
  72#define DP_MSA_MISC_COLOR_CEA_RGB               _DP_MSA_MISC_COLOR(0, 0, 1, 0)
  73#define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED        _DP_MSA_MISC_COLOR(0, 3, 0, 0)
  74#define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT        _DP_MSA_MISC_COLOR(0, 3, 0, 1)
  75#define DP_MSA_MISC_COLOR_Y_ONLY                _DP_MSA_MISC_COLOR(1, 0, 0, 0)
  76#define DP_MSA_MISC_COLOR_RAW                   _DP_MSA_MISC_COLOR(1, 1, 0, 0)
  77#define DP_MSA_MISC_COLOR_YCBCR_422_BT601       _DP_MSA_MISC_COLOR(0, 1, 1, 0)
  78#define DP_MSA_MISC_COLOR_YCBCR_422_BT709       _DP_MSA_MISC_COLOR(0, 1, 1, 1)
  79#define DP_MSA_MISC_COLOR_YCBCR_444_BT601       _DP_MSA_MISC_COLOR(0, 2, 1, 0)
  80#define DP_MSA_MISC_COLOR_YCBCR_444_BT709       _DP_MSA_MISC_COLOR(0, 2, 1, 1)
  81#define DP_MSA_MISC_COLOR_XVYCC_422_BT601       _DP_MSA_MISC_COLOR(0, 1, 0, 0)
  82#define DP_MSA_MISC_COLOR_XVYCC_422_BT709       _DP_MSA_MISC_COLOR(0, 1, 0, 1)
  83#define DP_MSA_MISC_COLOR_XVYCC_444_BT601       _DP_MSA_MISC_COLOR(0, 2, 0, 0)
  84#define DP_MSA_MISC_COLOR_XVYCC_444_BT709       _DP_MSA_MISC_COLOR(0, 2, 0, 1)
  85#define DP_MSA_MISC_COLOR_OPRGB                 _DP_MSA_MISC_COLOR(0, 0, 1, 1)
  86#define DP_MSA_MISC_COLOR_DCI_P3                _DP_MSA_MISC_COLOR(0, 3, 1, 0)
  87#define DP_MSA_MISC_COLOR_COLOR_PROFILE         _DP_MSA_MISC_COLOR(0, 3, 1, 1)
  88#define DP_MSA_MISC_COLOR_VSC_SDP               (1 << 14)
  89
  90#define DP_AUX_MAX_PAYLOAD_BYTES        16
  91
  92#define DP_AUX_I2C_WRITE                0x0
  93#define DP_AUX_I2C_READ                 0x1
  94#define DP_AUX_I2C_WRITE_STATUS_UPDATE  0x2
  95#define DP_AUX_I2C_MOT                  0x4
  96#define DP_AUX_NATIVE_WRITE             0x8
  97#define DP_AUX_NATIVE_READ              0x9
  98
  99#define DP_AUX_NATIVE_REPLY_ACK         (0x0 << 0)
 100#define DP_AUX_NATIVE_REPLY_NACK        (0x1 << 0)
 101#define DP_AUX_NATIVE_REPLY_DEFER       (0x2 << 0)
 102#define DP_AUX_NATIVE_REPLY_MASK        (0x3 << 0)
 103
 104#define DP_AUX_I2C_REPLY_ACK            (0x0 << 2)
 105#define DP_AUX_I2C_REPLY_NACK           (0x1 << 2)
 106#define DP_AUX_I2C_REPLY_DEFER          (0x2 << 2)
 107#define DP_AUX_I2C_REPLY_MASK           (0x3 << 2)
 108
 109/* DPCD Field Address Mapping */
 110
 111/* Receiver Capability */
 112#define DP_DPCD_REV                         0x000
 113# define DP_DPCD_REV_10                     0x10
 114# define DP_DPCD_REV_11                     0x11
 115# define DP_DPCD_REV_12                     0x12
 116# define DP_DPCD_REV_13                     0x13
 117# define DP_DPCD_REV_14                     0x14
 118
 119#define DP_MAX_LINK_RATE                    0x001
 120
 121#define DP_MAX_LANE_COUNT                   0x002
 122# define DP_MAX_LANE_COUNT_MASK             0x1f
 123# define DP_TPS3_SUPPORTED                  (1 << 6) /* 1.2 */
 124# define DP_ENHANCED_FRAME_CAP              (1 << 7)
 125
 126#define DP_MAX_DOWNSPREAD                   0x003
 127# define DP_MAX_DOWNSPREAD_0_5              (1 << 0)
 128# define DP_STREAM_REGENERATION_STATUS_CAP  (1 << 1) /* 2.0 */
 129# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING  (1 << 6)
 130# define DP_TPS4_SUPPORTED                  (1 << 7)
 131
 132#define DP_NORP                             0x004
 133
 134#define DP_DOWNSTREAMPORT_PRESENT           0x005
 135# define DP_DWN_STRM_PORT_PRESENT           (1 << 0)
 136# define DP_DWN_STRM_PORT_TYPE_MASK         0x06
 137# define DP_DWN_STRM_PORT_TYPE_DP           (0 << 1)
 138# define DP_DWN_STRM_PORT_TYPE_ANALOG       (1 << 1)
 139# define DP_DWN_STRM_PORT_TYPE_TMDS         (2 << 1)
 140# define DP_DWN_STRM_PORT_TYPE_OTHER        (3 << 1)
 141# define DP_FORMAT_CONVERSION               (1 << 3)
 142# define DP_DETAILED_CAP_INFO_AVAILABLE     (1 << 4) /* DPI */
 143
 144#define DP_MAIN_LINK_CHANNEL_CODING         0x006
 145# define DP_CAP_ANSI_8B10B                  (1 << 0)
 146# define DP_CAP_ANSI_128B132B               (1 << 1) /* 2.0 */
 147
 148#define DP_DOWN_STREAM_PORT_COUNT           0x007
 149# define DP_PORT_COUNT_MASK                 0x0f
 150# define DP_MSA_TIMING_PAR_IGNORED          (1 << 6) /* eDP */
 151# define DP_OUI_SUPPORT                     (1 << 7)
 152
 153#define DP_RECEIVE_PORT_0_CAP_0             0x008
 154# define DP_LOCAL_EDID_PRESENT              (1 << 1)
 155# define DP_ASSOCIATED_TO_PRECEDING_PORT    (1 << 2)
 156
 157#define DP_RECEIVE_PORT_0_BUFFER_SIZE       0x009
 158
 159#define DP_RECEIVE_PORT_1_CAP_0             0x00a
 160#define DP_RECEIVE_PORT_1_BUFFER_SIZE       0x00b
 161
 162#define DP_I2C_SPEED_CAP                    0x00c    /* DPI */
 163# define DP_I2C_SPEED_1K                    0x01
 164# define DP_I2C_SPEED_5K                    0x02
 165# define DP_I2C_SPEED_10K                   0x04
 166# define DP_I2C_SPEED_100K                  0x08
 167# define DP_I2C_SPEED_400K                  0x10
 168# define DP_I2C_SPEED_1M                    0x20
 169
 170#define DP_EDP_CONFIGURATION_CAP            0x00d   /* XXX 1.2? */
 171# define DP_ALTERNATE_SCRAMBLER_RESET_CAP   (1 << 0)
 172# define DP_FRAMING_CHANGE_CAP              (1 << 1)
 173# define DP_DPCD_DISPLAY_CONTROL_CAPABLE     (1 << 3) /* edp v1.2 or higher */
 174
 175#define DP_TRAINING_AUX_RD_INTERVAL             0x00e   /* XXX 1.2? */
 176# define DP_TRAINING_AUX_RD_MASK                0x7F    /* DP 1.3 */
 177# define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7) /* DP 1.3 */
 178
 179#define DP_ADAPTER_CAP                      0x00f   /* 1.2 */
 180# define DP_FORCE_LOAD_SENSE_CAP            (1 << 0)
 181# define DP_ALTERNATE_I2C_PATTERN_CAP       (1 << 1)
 182
 183#define DP_SUPPORTED_LINK_RATES             0x010 /* eDP 1.4 */
 184# define DP_MAX_SUPPORTED_RATES              8      /* 16-bit little-endian */
 185
 186/* Multiple stream transport */
 187#define DP_FAUX_CAP                         0x020   /* 1.2 */
 188# define DP_FAUX_CAP_1                      (1 << 0)
 189
 190#define DP_SINK_VIDEO_FALLBACK_FORMATS      0x020   /* 2.0 */
 191# define DP_FALLBACK_1024x768_60HZ_24BPP    (1 << 0)
 192# define DP_FALLBACK_1280x720_60HZ_24BPP    (1 << 1)
 193# define DP_FALLBACK_1920x1080_60HZ_24BPP   (1 << 2)
 194
 195#define DP_MSTM_CAP                         0x021   /* 1.2 */
 196# define DP_MST_CAP                         (1 << 0)
 197# define DP_SINGLE_STREAM_SIDEBAND_MSG      (1 << 1) /* 2.0 */
 198
 199#define DP_NUMBER_OF_AUDIO_ENDPOINTS        0x022   /* 1.2 */
 200
 201/* AV_SYNC_DATA_BLOCK                                  1.2 */
 202#define DP_AV_GRANULARITY                   0x023
 203# define DP_AG_FACTOR_MASK                  (0xf << 0)
 204# define DP_AG_FACTOR_3MS                   (0 << 0)
 205# define DP_AG_FACTOR_2MS                   (1 << 0)
 206# define DP_AG_FACTOR_1MS                   (2 << 0)
 207# define DP_AG_FACTOR_500US                 (3 << 0)
 208# define DP_AG_FACTOR_200US                 (4 << 0)
 209# define DP_AG_FACTOR_100US                 (5 << 0)
 210# define DP_AG_FACTOR_10US                  (6 << 0)
 211# define DP_AG_FACTOR_1US                   (7 << 0)
 212# define DP_VG_FACTOR_MASK                  (0xf << 4)
 213# define DP_VG_FACTOR_3MS                   (0 << 4)
 214# define DP_VG_FACTOR_2MS                   (1 << 4)
 215# define DP_VG_FACTOR_1MS                   (2 << 4)
 216# define DP_VG_FACTOR_500US                 (3 << 4)
 217# define DP_VG_FACTOR_200US                 (4 << 4)
 218# define DP_VG_FACTOR_100US                 (5 << 4)
 219
 220#define DP_AUD_DEC_LAT0                     0x024
 221#define DP_AUD_DEC_LAT1                     0x025
 222
 223#define DP_AUD_PP_LAT0                      0x026
 224#define DP_AUD_PP_LAT1                      0x027
 225
 226#define DP_VID_INTER_LAT                    0x028
 227
 228#define DP_VID_PROG_LAT                     0x029
 229
 230#define DP_REP_LAT                          0x02a
 231
 232#define DP_AUD_DEL_INS0                     0x02b
 233#define DP_AUD_DEL_INS1                     0x02c
 234#define DP_AUD_DEL_INS2                     0x02d
 235/* End of AV_SYNC_DATA_BLOCK */
 236
 237#define DP_RECEIVER_ALPM_CAP                0x02e   /* eDP 1.4 */
 238# define DP_ALPM_CAP                        (1 << 0)
 239
 240#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP   0x02f   /* eDP 1.4 */
 241# define DP_AUX_FRAME_SYNC_CAP              (1 << 0)
 242
 243#define DP_GUID                             0x030   /* 1.2 */
 244
 245#define DP_DSC_SUPPORT                      0x060   /* DP 1.4 */
 246# define DP_DSC_DECOMPRESSION_IS_SUPPORTED  (1 << 0)
 247
 248#define DP_DSC_REV                          0x061
 249# define DP_DSC_MAJOR_MASK                  (0xf << 0)
 250# define DP_DSC_MINOR_MASK                  (0xf << 4)
 251# define DP_DSC_MAJOR_SHIFT                 0
 252# define DP_DSC_MINOR_SHIFT                 4
 253
 254#define DP_DSC_RC_BUF_BLK_SIZE              0x062
 255# define DP_DSC_RC_BUF_BLK_SIZE_1           0x0
 256# define DP_DSC_RC_BUF_BLK_SIZE_4           0x1
 257# define DP_DSC_RC_BUF_BLK_SIZE_16          0x2
 258# define DP_DSC_RC_BUF_BLK_SIZE_64          0x3
 259
 260#define DP_DSC_RC_BUF_SIZE                  0x063
 261
 262#define DP_DSC_SLICE_CAP_1                  0x064
 263# define DP_DSC_1_PER_DP_DSC_SINK           (1 << 0)
 264# define DP_DSC_2_PER_DP_DSC_SINK           (1 << 1)
 265# define DP_DSC_4_PER_DP_DSC_SINK           (1 << 3)
 266# define DP_DSC_6_PER_DP_DSC_SINK           (1 << 4)
 267# define DP_DSC_8_PER_DP_DSC_SINK           (1 << 5)
 268# define DP_DSC_10_PER_DP_DSC_SINK          (1 << 6)
 269# define DP_DSC_12_PER_DP_DSC_SINK          (1 << 7)
 270
 271#define DP_DSC_LINE_BUF_BIT_DEPTH           0x065
 272# define DP_DSC_LINE_BUF_BIT_DEPTH_MASK     (0xf << 0)
 273# define DP_DSC_LINE_BUF_BIT_DEPTH_9        0x0
 274# define DP_DSC_LINE_BUF_BIT_DEPTH_10       0x1
 275# define DP_DSC_LINE_BUF_BIT_DEPTH_11       0x2
 276# define DP_DSC_LINE_BUF_BIT_DEPTH_12       0x3
 277# define DP_DSC_LINE_BUF_BIT_DEPTH_13       0x4
 278# define DP_DSC_LINE_BUF_BIT_DEPTH_14       0x5
 279# define DP_DSC_LINE_BUF_BIT_DEPTH_15       0x6
 280# define DP_DSC_LINE_BUF_BIT_DEPTH_16       0x7
 281# define DP_DSC_LINE_BUF_BIT_DEPTH_8        0x8
 282
 283#define DP_DSC_BLK_PREDICTION_SUPPORT       0x066
 284# define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
 285
 286#define DP_DSC_MAX_BITS_PER_PIXEL_LOW       0x067   /* eDP 1.4 */
 287
 288#define DP_DSC_MAX_BITS_PER_PIXEL_HI        0x068   /* eDP 1.4 */
 289# define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK  (0x3 << 0)
 290# define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8
 291
 292#define DP_DSC_DEC_COLOR_FORMAT_CAP         0x069
 293# define DP_DSC_RGB                         (1 << 0)
 294# define DP_DSC_YCbCr444                    (1 << 1)
 295# define DP_DSC_YCbCr422_Simple             (1 << 2)
 296# define DP_DSC_YCbCr422_Native             (1 << 3)
 297# define DP_DSC_YCbCr420_Native             (1 << 4)
 298
 299#define DP_DSC_DEC_COLOR_DEPTH_CAP          0x06A
 300# define DP_DSC_8_BPC                       (1 << 1)
 301# define DP_DSC_10_BPC                      (1 << 2)
 302# define DP_DSC_12_BPC                      (1 << 3)
 303
 304#define DP_DSC_PEAK_THROUGHPUT              0x06B
 305# define DP_DSC_THROUGHPUT_MODE_0_MASK      (0xf << 0)
 306# define DP_DSC_THROUGHPUT_MODE_0_SHIFT     0
 307# define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED 0
 308# define DP_DSC_THROUGHPUT_MODE_0_340       (1 << 0)
 309# define DP_DSC_THROUGHPUT_MODE_0_400       (2 << 0)
 310# define DP_DSC_THROUGHPUT_MODE_0_450       (3 << 0)
 311# define DP_DSC_THROUGHPUT_MODE_0_500       (4 << 0)
 312# define DP_DSC_THROUGHPUT_MODE_0_550       (5 << 0)
 313# define DP_DSC_THROUGHPUT_MODE_0_600       (6 << 0)
 314# define DP_DSC_THROUGHPUT_MODE_0_650       (7 << 0)
 315# define DP_DSC_THROUGHPUT_MODE_0_700       (8 << 0)
 316# define DP_DSC_THROUGHPUT_MODE_0_750       (9 << 0)
 317# define DP_DSC_THROUGHPUT_MODE_0_800       (10 << 0)
 318# define DP_DSC_THROUGHPUT_MODE_0_850       (11 << 0)
 319# define DP_DSC_THROUGHPUT_MODE_0_900       (12 << 0)
 320# define DP_DSC_THROUGHPUT_MODE_0_950       (13 << 0)
 321# define DP_DSC_THROUGHPUT_MODE_0_1000      (14 << 0)
 322# define DP_DSC_THROUGHPUT_MODE_0_170       (15 << 0) /* 1.4a */
 323# define DP_DSC_THROUGHPUT_MODE_1_MASK      (0xf << 4)
 324# define DP_DSC_THROUGHPUT_MODE_1_SHIFT     4
 325# define DP_DSC_THROUGHPUT_MODE_1_UNSUPPORTED 0
 326# define DP_DSC_THROUGHPUT_MODE_1_340       (1 << 4)
 327# define DP_DSC_THROUGHPUT_MODE_1_400       (2 << 4)
 328# define DP_DSC_THROUGHPUT_MODE_1_450       (3 << 4)
 329# define DP_DSC_THROUGHPUT_MODE_1_500       (4 << 4)
 330# define DP_DSC_THROUGHPUT_MODE_1_550       (5 << 4)
 331# define DP_DSC_THROUGHPUT_MODE_1_600       (6 << 4)
 332# define DP_DSC_THROUGHPUT_MODE_1_650       (7 << 4)
 333# define DP_DSC_THROUGHPUT_MODE_1_700       (8 << 4)
 334# define DP_DSC_THROUGHPUT_MODE_1_750       (9 << 4)
 335# define DP_DSC_THROUGHPUT_MODE_1_800       (10 << 4)
 336# define DP_DSC_THROUGHPUT_MODE_1_850       (11 << 4)
 337# define DP_DSC_THROUGHPUT_MODE_1_900       (12 << 4)
 338# define DP_DSC_THROUGHPUT_MODE_1_950       (13 << 4)
 339# define DP_DSC_THROUGHPUT_MODE_1_1000      (14 << 4)
 340# define DP_DSC_THROUGHPUT_MODE_1_170       (15 << 4)
 341
 342#define DP_DSC_MAX_SLICE_WIDTH              0x06C
 343#define DP_DSC_MIN_SLICE_WIDTH_VALUE        2560
 344#define DP_DSC_SLICE_WIDTH_MULTIPLIER       320
 345
 346#define DP_DSC_SLICE_CAP_2                  0x06D
 347# define DP_DSC_16_PER_DP_DSC_SINK          (1 << 0)
 348# define DP_DSC_20_PER_DP_DSC_SINK          (1 << 1)
 349# define DP_DSC_24_PER_DP_DSC_SINK          (1 << 2)
 350
 351#define DP_DSC_BITS_PER_PIXEL_INC           0x06F
 352# define DP_DSC_BITS_PER_PIXEL_1_16         0x0
 353# define DP_DSC_BITS_PER_PIXEL_1_8          0x1
 354# define DP_DSC_BITS_PER_PIXEL_1_4          0x2
 355# define DP_DSC_BITS_PER_PIXEL_1_2          0x3
 356# define DP_DSC_BITS_PER_PIXEL_1            0x4
 357
 358#define DP_PSR_SUPPORT                      0x070   /* XXX 1.2? */
 359# define DP_PSR_IS_SUPPORTED                1
 360# define DP_PSR2_IS_SUPPORTED               2       /* eDP 1.4 */
 361# define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED  3       /* eDP 1.4a */
 362
 363#define DP_PSR_CAPS                         0x071   /* XXX 1.2? */
 364# define DP_PSR_NO_TRAIN_ON_EXIT            1
 365# define DP_PSR_SETUP_TIME_330              (0 << 1)
 366# define DP_PSR_SETUP_TIME_275              (1 << 1)
 367# define DP_PSR_SETUP_TIME_220              (2 << 1)
 368# define DP_PSR_SETUP_TIME_165              (3 << 1)
 369# define DP_PSR_SETUP_TIME_110              (4 << 1)
 370# define DP_PSR_SETUP_TIME_55               (5 << 1)
 371# define DP_PSR_SETUP_TIME_0                (6 << 1)
 372# define DP_PSR_SETUP_TIME_MASK             (7 << 1)
 373# define DP_PSR_SETUP_TIME_SHIFT            1
 374# define DP_PSR2_SU_Y_COORDINATE_REQUIRED   (1 << 4)  /* eDP 1.4a */
 375# define DP_PSR2_SU_GRANULARITY_REQUIRED    (1 << 5)  /* eDP 1.4b */
 376
 377#define DP_PSR2_SU_X_GRANULARITY            0x072 /* eDP 1.4b */
 378#define DP_PSR2_SU_Y_GRANULARITY            0x074 /* eDP 1.4b */
 379
 380/*
 381 * 0x80-0x8f describe downstream port capabilities, but there are two layouts
 382 * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set.  If it was not,
 383 * each port's descriptor is one byte wide.  If it was set, each port's is
 384 * four bytes wide, starting with the one byte from the base info.  As of
 385 * DP interop v1.1a only VGA defines additional detail.
 386 */
 387
 388/* offset 0 */
 389#define DP_DOWNSTREAM_PORT_0                0x80
 390# define DP_DS_PORT_TYPE_MASK               (7 << 0)
 391# define DP_DS_PORT_TYPE_DP                 0
 392# define DP_DS_PORT_TYPE_VGA                1
 393# define DP_DS_PORT_TYPE_DVI                2
 394# define DP_DS_PORT_TYPE_HDMI               3
 395# define DP_DS_PORT_TYPE_NON_EDID           4
 396# define DP_DS_PORT_TYPE_DP_DUALMODE        5
 397# define DP_DS_PORT_TYPE_WIRELESS           6
 398# define DP_DS_PORT_HPD                     (1 << 3)
 399# define DP_DS_NON_EDID_MASK                (0xf << 4)
 400# define DP_DS_NON_EDID_720x480i_60         (1 << 4)
 401# define DP_DS_NON_EDID_720x480i_50         (2 << 4)
 402# define DP_DS_NON_EDID_1920x1080i_60       (3 << 4)
 403# define DP_DS_NON_EDID_1920x1080i_50       (4 << 4)
 404# define DP_DS_NON_EDID_1280x720_60         (5 << 4)
 405# define DP_DS_NON_EDID_1280x720_50         (7 << 4)
 406/* offset 1 for VGA is maximum megapixels per second / 8 */
 407/* offset 1 for DVI/HDMI is maximum TMDS clock in Mbps / 2.5 */
 408/* offset 2 for VGA/DVI/HDMI */
 409# define DP_DS_MAX_BPC_MASK                 (3 << 0)
 410# define DP_DS_8BPC                         0
 411# define DP_DS_10BPC                        1
 412# define DP_DS_12BPC                        2
 413# define DP_DS_16BPC                        3
 414/* HDMI2.1 PCON FRL CONFIGURATION */
 415# define DP_PCON_MAX_FRL_BW                 (7 << 2)
 416# define DP_PCON_MAX_0GBPS                  (0 << 2)
 417# define DP_PCON_MAX_9GBPS                  (1 << 2)
 418# define DP_PCON_MAX_18GBPS                 (2 << 2)
 419# define DP_PCON_MAX_24GBPS                 (3 << 2)
 420# define DP_PCON_MAX_32GBPS                 (4 << 2)
 421# define DP_PCON_MAX_40GBPS                 (5 << 2)
 422# define DP_PCON_MAX_48GBPS                 (6 << 2)
 423# define DP_PCON_SOURCE_CTL_MODE            (1 << 5)
 424
 425/* offset 3 for DVI */
 426# define DP_DS_DVI_DUAL_LINK                (1 << 1)
 427# define DP_DS_DVI_HIGH_COLOR_DEPTH         (1 << 2)
 428/* offset 3 for HDMI */
 429# define DP_DS_HDMI_FRAME_SEQ_TO_FRAME_PACK (1 << 0)
 430# define DP_DS_HDMI_YCBCR422_PASS_THROUGH   (1 << 1)
 431# define DP_DS_HDMI_YCBCR420_PASS_THROUGH   (1 << 2)
 432# define DP_DS_HDMI_YCBCR444_TO_422_CONV    (1 << 3)
 433# define DP_DS_HDMI_YCBCR444_TO_420_CONV    (1 << 4)
 434
 435/*
 436 * VESA DP-to-HDMI PCON Specification adds caps for colorspace
 437 * conversion in DFP cap DPCD 83h. Sec6.1 Table-3.
 438 * Based on the available support the source can enable
 439 * color conversion by writing into PROTOCOL_COVERTER_CONTROL_2
 440 * DPCD 3052h.
 441 */
 442# define DP_DS_HDMI_BT601_RGB_YCBCR_CONV    (1 << 5)
 443# define DP_DS_HDMI_BT709_RGB_YCBCR_CONV    (1 << 6)
 444# define DP_DS_HDMI_BT2020_RGB_YCBCR_CONV   (1 << 7)
 445
 446#define DP_MAX_DOWNSTREAM_PORTS             0x10
 447
 448/* DP Forward error Correction Registers */
 449#define DP_FEC_CAPABILITY                   0x090    /* 1.4 */
 450# define DP_FEC_CAPABLE                     (1 << 0)
 451# define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP  (1 << 1)
 452# define DP_FEC_CORR_BLK_ERROR_COUNT_CAP    (1 << 2)
 453# define DP_FEC_BIT_ERROR_COUNT_CAP         (1 << 3)
 454
 455/* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */
 456#define DP_PCON_DSC_ENCODER_CAP_SIZE        0xC /* 0x9E - 0x92 */
 457#define DP_PCON_DSC_ENCODER                 0x092
 458# define DP_PCON_DSC_ENCODER_SUPPORTED      (1 << 0)
 459# define DP_PCON_DSC_PPS_ENC_OVERRIDE       (1 << 1)
 460
 461/* DP-HDMI2.1 PCON DSC Version */
 462#define DP_PCON_DSC_VERSION                 0x093
 463# define DP_PCON_DSC_MAJOR_MASK             (0xF << 0)
 464# define DP_PCON_DSC_MINOR_MASK             (0xF << 4)
 465# define DP_PCON_DSC_MAJOR_SHIFT            0
 466# define DP_PCON_DSC_MINOR_SHIFT            4
 467
 468/* DP-HDMI2.1 PCON DSC RC Buffer block size */
 469#define DP_PCON_DSC_RC_BUF_BLK_INFO         0x094
 470# define DP_PCON_DSC_RC_BUF_BLK_SIZE        (0x3 << 0)
 471# define DP_PCON_DSC_RC_BUF_BLK_1KB         0
 472# define DP_PCON_DSC_RC_BUF_BLK_4KB         1
 473# define DP_PCON_DSC_RC_BUF_BLK_16KB        2
 474# define DP_PCON_DSC_RC_BUF_BLK_64KB        3
 475
 476/* DP-HDMI2.1 PCON DSC RC Buffer size */
 477#define DP_PCON_DSC_RC_BUF_SIZE             0x095
 478
 479/* DP-HDMI2.1 PCON DSC Slice capabilities-1 */
 480#define DP_PCON_DSC_SLICE_CAP_1             0x096
 481# define DP_PCON_DSC_1_PER_DSC_ENC     (0x1 << 0)
 482# define DP_PCON_DSC_2_PER_DSC_ENC     (0x1 << 1)
 483# define DP_PCON_DSC_4_PER_DSC_ENC     (0x1 << 3)
 484# define DP_PCON_DSC_6_PER_DSC_ENC     (0x1 << 4)
 485# define DP_PCON_DSC_8_PER_DSC_ENC     (0x1 << 5)
 486# define DP_PCON_DSC_10_PER_DSC_ENC    (0x1 << 6)
 487# define DP_PCON_DSC_12_PER_DSC_ENC    (0x1 << 7)
 488
 489#define DP_PCON_DSC_BUF_BIT_DEPTH           0x097
 490# define DP_PCON_DSC_BIT_DEPTH_MASK         (0xF << 0)
 491# define DP_PCON_DSC_DEPTH_9_BITS           0
 492# define DP_PCON_DSC_DEPTH_10_BITS          1
 493# define DP_PCON_DSC_DEPTH_11_BITS          2
 494# define DP_PCON_DSC_DEPTH_12_BITS          3
 495# define DP_PCON_DSC_DEPTH_13_BITS          4
 496# define DP_PCON_DSC_DEPTH_14_BITS          5
 497# define DP_PCON_DSC_DEPTH_15_BITS          6
 498# define DP_PCON_DSC_DEPTH_16_BITS          7
 499# define DP_PCON_DSC_DEPTH_8_BITS           8
 500
 501#define DP_PCON_DSC_BLOCK_PREDICTION        0x098
 502# define DP_PCON_DSC_BLOCK_PRED_SUPPORT     (0x1 << 0)
 503
 504#define DP_PCON_DSC_ENC_COLOR_FMT_CAP       0x099
 505# define DP_PCON_DSC_ENC_RGB                (0x1 << 0)
 506# define DP_PCON_DSC_ENC_YUV444             (0x1 << 1)
 507# define DP_PCON_DSC_ENC_YUV422_S           (0x1 << 2)
 508# define DP_PCON_DSC_ENC_YUV422_N           (0x1 << 3)
 509# define DP_PCON_DSC_ENC_YUV420_N           (0x1 << 4)
 510
 511#define DP_PCON_DSC_ENC_COLOR_DEPTH_CAP     0x09A
 512# define DP_PCON_DSC_ENC_8BPC               (0x1 << 1)
 513# define DP_PCON_DSC_ENC_10BPC              (0x1 << 2)
 514# define DP_PCON_DSC_ENC_12BPC              (0x1 << 3)
 515
 516#define DP_PCON_DSC_MAX_SLICE_WIDTH         0x09B
 517
 518/* DP-HDMI2.1 PCON DSC Slice capabilities-2 */
 519#define DP_PCON_DSC_SLICE_CAP_2             0x09C
 520# define DP_PCON_DSC_16_PER_DSC_ENC         (0x1 << 0)
 521# define DP_PCON_DSC_20_PER_DSC_ENC         (0x1 << 1)
 522# define DP_PCON_DSC_24_PER_DSC_ENC         (0x1 << 2)
 523
 524/* DP-HDMI2.1 PCON HDMI TX Encoder Bits/pixel increment */
 525#define DP_PCON_DSC_BPP_INCR                0x09E
 526# define DP_PCON_DSC_BPP_INCR_MASK          (0x7 << 0)
 527# define DP_PCON_DSC_ONE_16TH_BPP           0
 528# define DP_PCON_DSC_ONE_8TH_BPP            1
 529# define DP_PCON_DSC_ONE_4TH_BPP            2
 530# define DP_PCON_DSC_ONE_HALF_BPP           3
 531# define DP_PCON_DSC_ONE_BPP                4
 532
 533/* DP Extended DSC Capabilities */
 534#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0  0x0a0   /* DP 1.4a SCR */
 535#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1  0x0a1
 536#define DP_DSC_BRANCH_MAX_LINE_WIDTH        0x0a2
 537
 538/* Link Configuration */
 539#define DP_LINK_BW_SET                      0x100
 540# define DP_LINK_RATE_TABLE                 0x00    /* eDP 1.4 */
 541# define DP_LINK_BW_1_62                    0x06
 542# define DP_LINK_BW_2_7                     0x0a
 543# define DP_LINK_BW_5_4                     0x14    /* 1.2 */
 544# define DP_LINK_BW_8_1                     0x1e    /* 1.4 */
 545# define DP_LINK_BW_10                      0x01    /* 2.0 128b/132b Link Layer */
 546# define DP_LINK_BW_13_5                    0x04    /* 2.0 128b/132b Link Layer */
 547# define DP_LINK_BW_20                      0x02    /* 2.0 128b/132b Link Layer */
 548
 549#define DP_LANE_COUNT_SET                   0x101
 550# define DP_LANE_COUNT_MASK                 0x0f
 551# define DP_LANE_COUNT_ENHANCED_FRAME_EN    (1 << 7)
 552
 553#define DP_TRAINING_PATTERN_SET             0x102
 554# define DP_TRAINING_PATTERN_DISABLE        0
 555# define DP_TRAINING_PATTERN_1              1
 556# define DP_TRAINING_PATTERN_2              2
 557# define DP_TRAINING_PATTERN_3              3       /* 1.2 */
 558# define DP_TRAINING_PATTERN_4              7       /* 1.4 */
 559# define DP_TRAINING_PATTERN_MASK           0x3
 560# define DP_TRAINING_PATTERN_MASK_1_4       0xf
 561
 562/* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */
 563# define DP_LINK_QUAL_PATTERN_11_DISABLE    (0 << 2)
 564# define DP_LINK_QUAL_PATTERN_11_D10_2      (1 << 2)
 565# define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2)
 566# define DP_LINK_QUAL_PATTERN_11_PRBS7      (3 << 2)
 567# define DP_LINK_QUAL_PATTERN_11_MASK       (3 << 2)
 568
 569# define DP_RECOVERED_CLOCK_OUT_EN          (1 << 4)
 570# define DP_LINK_SCRAMBLING_DISABLE         (1 << 5)
 571
 572# define DP_SYMBOL_ERROR_COUNT_BOTH         (0 << 6)
 573# define DP_SYMBOL_ERROR_COUNT_DISPARITY    (1 << 6)
 574# define DP_SYMBOL_ERROR_COUNT_SYMBOL       (2 << 6)
 575# define DP_SYMBOL_ERROR_COUNT_MASK         (3 << 6)
 576
 577#define DP_TRAINING_LANE0_SET               0x103
 578#define DP_TRAINING_LANE1_SET               0x104
 579#define DP_TRAINING_LANE2_SET               0x105
 580#define DP_TRAINING_LANE3_SET               0x106
 581
 582# define DP_TRAIN_VOLTAGE_SWING_MASK        0x3
 583# define DP_TRAIN_VOLTAGE_SWING_SHIFT       0
 584# define DP_TRAIN_MAX_SWING_REACHED         (1 << 2)
 585# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
 586# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
 587# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
 588# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
 589
 590# define DP_TRAIN_PRE_EMPHASIS_MASK         (3 << 3)
 591# define DP_TRAIN_PRE_EMPH_LEVEL_0              (0 << 3)
 592# define DP_TRAIN_PRE_EMPH_LEVEL_1              (1 << 3)
 593# define DP_TRAIN_PRE_EMPH_LEVEL_2              (2 << 3)
 594# define DP_TRAIN_PRE_EMPH_LEVEL_3              (3 << 3)
 595
 596# define DP_TRAIN_PRE_EMPHASIS_SHIFT        3
 597# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED  (1 << 5)
 598
 599# define DP_TX_FFE_PRESET_VALUE_MASK        (0xf << 0) /* 2.0 128b/132b Link Layer */
 600
 601#define DP_DOWNSPREAD_CTRL                  0x107
 602# define DP_SPREAD_AMP_0_5                  (1 << 4)
 603# define DP_MSA_TIMING_PAR_IGNORE_EN        (1 << 7) /* eDP */
 604
 605#define DP_MAIN_LINK_CHANNEL_CODING_SET     0x108
 606# define DP_SET_ANSI_8B10B                  (1 << 0)
 607# define DP_SET_ANSI_128B132B               (1 << 1)
 608
 609#define DP_I2C_SPEED_CONTROL_STATUS         0x109   /* DPI */
 610/* bitmask as for DP_I2C_SPEED_CAP */
 611
 612#define DP_EDP_CONFIGURATION_SET            0x10a   /* XXX 1.2? */
 613# define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
 614# define DP_FRAMING_CHANGE_ENABLE           (1 << 1)
 615# define DP_PANEL_SELF_TEST_ENABLE          (1 << 7)
 616
 617#define DP_LINK_QUAL_LANE0_SET              0x10b   /* DPCD >= 1.2 */
 618#define DP_LINK_QUAL_LANE1_SET              0x10c
 619#define DP_LINK_QUAL_LANE2_SET              0x10d
 620#define DP_LINK_QUAL_LANE3_SET              0x10e
 621# define DP_LINK_QUAL_PATTERN_DISABLE       0
 622# define DP_LINK_QUAL_PATTERN_D10_2         1
 623# define DP_LINK_QUAL_PATTERN_ERROR_RATE    2
 624# define DP_LINK_QUAL_PATTERN_PRBS7         3
 625# define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM  4
 626# define DP_LINK_QUAL_PATTERN_CP2520_PAT_1  5
 627# define DP_LINK_QUAL_PATTERN_CP2520_PAT_2  6
 628# define DP_LINK_QUAL_PATTERN_CP2520_PAT_3  7
 629/* DP 2.0 UHBR10, UHBR13.5, UHBR20 */
 630# define DP_LINK_QUAL_PATTERN_128B132B_TPS1 0x08
 631# define DP_LINK_QUAL_PATTERN_128B132B_TPS2 0x10
 632# define DP_LINK_QUAL_PATTERN_PRSBS9        0x18
 633# define DP_LINK_QUAL_PATTERN_PRSBS11       0x20
 634# define DP_LINK_QUAL_PATTERN_PRSBS15       0x28
 635# define DP_LINK_QUAL_PATTERN_PRSBS23       0x30
 636# define DP_LINK_QUAL_PATTERN_PRSBS31       0x38
 637# define DP_LINK_QUAL_PATTERN_CUSTOM        0x40
 638# define DP_LINK_QUAL_PATTERN_SQUARE        0x48
 639
 640#define DP_TRAINING_LANE0_1_SET2            0x10f
 641#define DP_TRAINING_LANE2_3_SET2            0x110
 642# define DP_LANE02_POST_CURSOR2_SET_MASK    (3 << 0)
 643# define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2)
 644# define DP_LANE13_POST_CURSOR2_SET_MASK    (3 << 4)
 645# define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6)
 646
 647#define DP_MSTM_CTRL                        0x111   /* 1.2 */
 648# define DP_MST_EN                          (1 << 0)
 649# define DP_UP_REQ_EN                       (1 << 1)
 650# define DP_UPSTREAM_IS_SRC                 (1 << 2)
 651
 652#define DP_AUDIO_DELAY0                     0x112   /* 1.2 */
 653#define DP_AUDIO_DELAY1                     0x113
 654#define DP_AUDIO_DELAY2                     0x114
 655
 656#define DP_LINK_RATE_SET                    0x115   /* eDP 1.4 */
 657# define DP_LINK_RATE_SET_SHIFT             0
 658# define DP_LINK_RATE_SET_MASK              (7 << 0)
 659
 660#define DP_RECEIVER_ALPM_CONFIG             0x116   /* eDP 1.4 */
 661# define DP_ALPM_ENABLE                     (1 << 0)
 662# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE  (1 << 1)
 663
 664#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF  0x117   /* eDP 1.4 */
 665# define DP_AUX_FRAME_SYNC_ENABLE           (1 << 0)
 666# define DP_IRQ_HPD_ENABLE                  (1 << 1)
 667
 668#define DP_UPSTREAM_DEVICE_DP_PWR_NEED      0x118   /* 1.2 */
 669# define DP_PWR_NOT_NEEDED                  (1 << 0)
 670
 671#define DP_FEC_CONFIGURATION                0x120    /* 1.4 */
 672# define DP_FEC_READY                       (1 << 0)
 673# define DP_FEC_ERR_COUNT_SEL_MASK          (7 << 1)
 674# define DP_FEC_ERR_COUNT_DIS               (0 << 1)
 675# define DP_FEC_UNCORR_BLK_ERROR_COUNT      (1 << 1)
 676# define DP_FEC_CORR_BLK_ERROR_COUNT        (2 << 1)
 677# define DP_FEC_BIT_ERROR_COUNT             (3 << 1)
 678# define DP_FEC_LANE_SELECT_MASK            (3 << 4)
 679# define DP_FEC_LANE_0_SELECT               (0 << 4)
 680# define DP_FEC_LANE_1_SELECT               (1 << 4)
 681# define DP_FEC_LANE_2_SELECT               (2 << 4)
 682# define DP_FEC_LANE_3_SELECT               (3 << 4)
 683
 684#define DP_AUX_FRAME_SYNC_VALUE             0x15c   /* eDP 1.4 */
 685# define DP_AUX_FRAME_SYNC_VALID            (1 << 0)
 686
 687#define DP_DSC_ENABLE                       0x160   /* DP 1.4 */
 688# define DP_DECOMPRESSION_EN                (1 << 0)
 689
 690#define DP_PSR_EN_CFG                       0x170   /* XXX 1.2? */
 691# define DP_PSR_ENABLE                      (1 << 0)
 692# define DP_PSR_MAIN_LINK_ACTIVE            (1 << 1)
 693# define DP_PSR_CRC_VERIFICATION            (1 << 2)
 694# define DP_PSR_FRAME_CAPTURE               (1 << 3)
 695# define DP_PSR_SELECTIVE_UPDATE            (1 << 4)
 696# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS     (1 << 5)
 697# define DP_PSR_ENABLE_PSR2                 (1 << 6) /* eDP 1.4a */
 698
 699#define DP_ADAPTER_CTRL                     0x1a0
 700# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE   (1 << 0)
 701
 702#define DP_BRANCH_DEVICE_CTRL               0x1a1
 703# define DP_BRANCH_DEVICE_IRQ_HPD           (1 << 0)
 704
 705#define DP_PAYLOAD_ALLOCATE_SET             0x1c0
 706#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
 707#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
 708
 709/* Link/Sink Device Status */
 710#define DP_SINK_COUNT                       0x200
 711/* prior to 1.2 bit 7 was reserved mbz */
 712# define DP_GET_SINK_COUNT(x)               ((((x) & 0x80) >> 1) | ((x) & 0x3f))
 713# define DP_SINK_CP_READY                   (1 << 6)
 714
 715#define DP_DEVICE_SERVICE_IRQ_VECTOR        0x201
 716# define DP_REMOTE_CONTROL_COMMAND_PENDING  (1 << 0)
 717# define DP_AUTOMATED_TEST_REQUEST          (1 << 1)
 718# define DP_CP_IRQ                          (1 << 2)
 719# define DP_MCCS_IRQ                        (1 << 3)
 720# define DP_DOWN_REP_MSG_RDY                (1 << 4) /* 1.2 MST */
 721# define DP_UP_REQ_MSG_RDY                  (1 << 5) /* 1.2 MST */
 722# define DP_SINK_SPECIFIC_IRQ               (1 << 6)
 723
 724#define DP_LANE0_1_STATUS                   0x202
 725#define DP_LANE2_3_STATUS                   0x203
 726# define DP_LANE_CR_DONE                    (1 << 0)
 727# define DP_LANE_CHANNEL_EQ_DONE            (1 << 1)
 728# define DP_LANE_SYMBOL_LOCKED              (1 << 2)
 729
 730#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE |           \
 731                            DP_LANE_CHANNEL_EQ_DONE |   \
 732                            DP_LANE_SYMBOL_LOCKED)
 733
 734#define DP_LANE_ALIGN_STATUS_UPDATED        0x204
 735
 736#define DP_INTERLANE_ALIGN_DONE             (1 << 0)
 737#define DP_DOWNSTREAM_PORT_STATUS_CHANGED   (1 << 6)
 738#define DP_LINK_STATUS_UPDATED              (1 << 7)
 739
 740#define DP_SINK_STATUS                      0x205
 741# define DP_RECEIVE_PORT_0_STATUS           (1 << 0)
 742# define DP_RECEIVE_PORT_1_STATUS           (1 << 1)
 743# define DP_STREAM_REGENERATION_STATUS      (1 << 2) /* 2.0 */
 744
 745#define DP_ADJUST_REQUEST_LANE0_1           0x206
 746#define DP_ADJUST_REQUEST_LANE2_3           0x207
 747# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK  0x03
 748# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
 749# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK   0x0c
 750# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT  2
 751# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK  0x30
 752# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
 753# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK   0xc0
 754# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT  6
 755
 756/* DP 2.0 128b/132b Link Layer */
 757# define DP_ADJUST_TX_FFE_PRESET_LANE0_MASK  (0xf << 0)
 758# define DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT 0
 759# define DP_ADJUST_TX_FFE_PRESET_LANE1_MASK  (0xf << 4)
 760# define DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT 4
 761
 762#define DP_ADJUST_REQUEST_POST_CURSOR2      0x20c
 763# define DP_ADJUST_POST_CURSOR2_LANE0_MASK  0x03
 764# define DP_ADJUST_POST_CURSOR2_LANE0_SHIFT 0
 765# define DP_ADJUST_POST_CURSOR2_LANE1_MASK  0x0c
 766# define DP_ADJUST_POST_CURSOR2_LANE1_SHIFT 2
 767# define DP_ADJUST_POST_CURSOR2_LANE2_MASK  0x30
 768# define DP_ADJUST_POST_CURSOR2_LANE2_SHIFT 4
 769# define DP_ADJUST_POST_CURSOR2_LANE3_MASK  0xc0
 770# define DP_ADJUST_POST_CURSOR2_LANE3_SHIFT 6
 771
 772#define DP_TEST_REQUEST                     0x218
 773# define DP_TEST_LINK_TRAINING              (1 << 0)
 774# define DP_TEST_LINK_VIDEO_PATTERN         (1 << 1)
 775# define DP_TEST_LINK_EDID_READ             (1 << 2)
 776# define DP_TEST_LINK_PHY_TEST_PATTERN      (1 << 3) /* DPCD >= 1.1 */
 777# define DP_TEST_LINK_FAUX_PATTERN          (1 << 4) /* DPCD >= 1.2 */
 778# define DP_TEST_LINK_AUDIO_PATTERN         (1 << 5) /* DPCD >= 1.2 */
 779# define DP_TEST_LINK_AUDIO_DISABLED_VIDEO  (1 << 6) /* DPCD >= 1.2 */
 780
 781#define DP_TEST_LINK_RATE                   0x219
 782# define DP_LINK_RATE_162                   (0x6)
 783# define DP_LINK_RATE_27                    (0xa)
 784
 785#define DP_TEST_LANE_COUNT                  0x220
 786
 787#define DP_TEST_PATTERN                     0x221
 788# define DP_NO_TEST_PATTERN                 0x0
 789# define DP_COLOR_RAMP                      0x1
 790# define DP_BLACK_AND_WHITE_VERTICAL_LINES  0x2
 791# define DP_COLOR_SQUARE                    0x3
 792
 793#define DP_TEST_H_TOTAL_HI                  0x222
 794#define DP_TEST_H_TOTAL_LO                  0x223
 795
 796#define DP_TEST_V_TOTAL_HI                  0x224
 797#define DP_TEST_V_TOTAL_LO                  0x225
 798
 799#define DP_TEST_H_START_HI                  0x226
 800#define DP_TEST_H_START_LO                  0x227
 801
 802#define DP_TEST_V_START_HI                  0x228
 803#define DP_TEST_V_START_LO                  0x229
 804
 805#define DP_TEST_HSYNC_HI                    0x22A
 806# define DP_TEST_HSYNC_POLARITY             (1 << 7)
 807# define DP_TEST_HSYNC_WIDTH_HI_MASK        (127 << 0)
 808#define DP_TEST_HSYNC_WIDTH_LO              0x22B
 809
 810#define DP_TEST_VSYNC_HI                    0x22C
 811# define DP_TEST_VSYNC_POLARITY             (1 << 7)
 812# define DP_TEST_VSYNC_WIDTH_HI_MASK        (127 << 0)
 813#define DP_TEST_VSYNC_WIDTH_LO              0x22D
 814
 815#define DP_TEST_H_WIDTH_HI                  0x22E
 816#define DP_TEST_H_WIDTH_LO                  0x22F
 817
 818#define DP_TEST_V_HEIGHT_HI                 0x230
 819#define DP_TEST_V_HEIGHT_LO                 0x231
 820
 821#define DP_TEST_MISC0                       0x232
 822# define DP_TEST_SYNC_CLOCK                 (1 << 0)
 823# define DP_TEST_COLOR_FORMAT_MASK          (3 << 1)
 824# define DP_TEST_COLOR_FORMAT_SHIFT         1
 825# define DP_COLOR_FORMAT_RGB                (0 << 1)
 826# define DP_COLOR_FORMAT_YCbCr422           (1 << 1)
 827# define DP_COLOR_FORMAT_YCbCr444           (2 << 1)
 828# define DP_TEST_DYNAMIC_RANGE_VESA         (0 << 3)
 829# define DP_TEST_DYNAMIC_RANGE_CEA          (1 << 3)
 830# define DP_TEST_YCBCR_COEFFICIENTS         (1 << 4)
 831# define DP_YCBCR_COEFFICIENTS_ITU601       (0 << 4)
 832# define DP_YCBCR_COEFFICIENTS_ITU709       (1 << 4)
 833# define DP_TEST_BIT_DEPTH_MASK             (7 << 5)
 834# define DP_TEST_BIT_DEPTH_SHIFT            5
 835# define DP_TEST_BIT_DEPTH_6                (0 << 5)
 836# define DP_TEST_BIT_DEPTH_8                (1 << 5)
 837# define DP_TEST_BIT_DEPTH_10               (2 << 5)
 838# define DP_TEST_BIT_DEPTH_12               (3 << 5)
 839# define DP_TEST_BIT_DEPTH_16               (4 << 5)
 840
 841#define DP_TEST_MISC1                       0x233
 842# define DP_TEST_REFRESH_DENOMINATOR        (1 << 0)
 843# define DP_TEST_INTERLACED                 (1 << 1)
 844
 845#define DP_TEST_REFRESH_RATE_NUMERATOR      0x234
 846
 847#define DP_TEST_MISC0                       0x232
 848
 849#define DP_TEST_CRC_R_CR                    0x240
 850#define DP_TEST_CRC_G_Y                     0x242
 851#define DP_TEST_CRC_B_CB                    0x244
 852
 853#define DP_TEST_SINK_MISC                   0x246
 854# define DP_TEST_CRC_SUPPORTED              (1 << 5)
 855# define DP_TEST_COUNT_MASK                 0xf
 856
 857#define DP_PHY_TEST_PATTERN                 0x248
 858# define DP_PHY_TEST_PATTERN_SEL_MASK       0x7
 859# define DP_PHY_TEST_PATTERN_NONE           0x0
 860# define DP_PHY_TEST_PATTERN_D10_2          0x1
 861# define DP_PHY_TEST_PATTERN_ERROR_COUNT    0x2
 862# define DP_PHY_TEST_PATTERN_PRBS7          0x3
 863# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM   0x4
 864# define DP_PHY_TEST_PATTERN_CP2520         0x5
 865
 866#define DP_TEST_HBR2_SCRAMBLER_RESET        0x24A
 867#define DP_TEST_80BIT_CUSTOM_PATTERN_7_0    0x250
 868#define DP_TEST_80BIT_CUSTOM_PATTERN_15_8   0x251
 869#define DP_TEST_80BIT_CUSTOM_PATTERN_23_16  0x252
 870#define DP_TEST_80BIT_CUSTOM_PATTERN_31_24  0x253
 871#define DP_TEST_80BIT_CUSTOM_PATTERN_39_32  0x254
 872#define DP_TEST_80BIT_CUSTOM_PATTERN_47_40  0x255
 873#define DP_TEST_80BIT_CUSTOM_PATTERN_55_48  0x256
 874#define DP_TEST_80BIT_CUSTOM_PATTERN_63_56  0x257
 875#define DP_TEST_80BIT_CUSTOM_PATTERN_71_64  0x258
 876#define DP_TEST_80BIT_CUSTOM_PATTERN_79_72  0x259
 877
 878#define DP_TEST_RESPONSE                    0x260
 879# define DP_TEST_ACK                        (1 << 0)
 880# define DP_TEST_NAK                        (1 << 1)
 881# define DP_TEST_EDID_CHECKSUM_WRITE        (1 << 2)
 882
 883#define DP_TEST_EDID_CHECKSUM               0x261
 884
 885#define DP_TEST_SINK                        0x270
 886# define DP_TEST_SINK_START                 (1 << 0)
 887#define DP_TEST_AUDIO_MODE                  0x271
 888#define DP_TEST_AUDIO_PATTERN_TYPE          0x272
 889#define DP_TEST_AUDIO_PERIOD_CH1            0x273
 890#define DP_TEST_AUDIO_PERIOD_CH2            0x274
 891#define DP_TEST_AUDIO_PERIOD_CH3            0x275
 892#define DP_TEST_AUDIO_PERIOD_CH4            0x276
 893#define DP_TEST_AUDIO_PERIOD_CH5            0x277
 894#define DP_TEST_AUDIO_PERIOD_CH6            0x278
 895#define DP_TEST_AUDIO_PERIOD_CH7            0x279
 896#define DP_TEST_AUDIO_PERIOD_CH8            0x27A
 897
 898#define DP_FEC_STATUS                       0x280    /* 1.4 */
 899# define DP_FEC_DECODE_EN_DETECTED          (1 << 0)
 900# define DP_FEC_DECODE_DIS_DETECTED         (1 << 1)
 901
 902#define DP_FEC_ERROR_COUNT_LSB              0x0281    /* 1.4 */
 903
 904#define DP_FEC_ERROR_COUNT_MSB              0x0282    /* 1.4 */
 905# define DP_FEC_ERROR_COUNT_MASK            0x7F
 906# define DP_FEC_ERR_COUNT_VALID             (1 << 7)
 907
 908#define DP_PAYLOAD_TABLE_UPDATE_STATUS      0x2c0   /* 1.2 MST */
 909# define DP_PAYLOAD_TABLE_UPDATED           (1 << 0)
 910# define DP_PAYLOAD_ACT_HANDLED             (1 << 1)
 911
 912#define DP_VC_PAYLOAD_ID_SLOT_1             0x2c1   /* 1.2 MST */
 913/* up to ID_SLOT_63 at 0x2ff */
 914
 915/* Source Device-specific */
 916#define DP_SOURCE_OUI                       0x300
 917
 918/* Sink Device-specific */
 919#define DP_SINK_OUI                         0x400
 920
 921/* Branch Device-specific */
 922#define DP_BRANCH_OUI                       0x500
 923#define DP_BRANCH_ID                        0x503
 924#define DP_BRANCH_REVISION_START            0x509
 925#define DP_BRANCH_HW_REV                    0x509
 926#define DP_BRANCH_SW_REV                    0x50A
 927
 928/* Link/Sink Device Power Control */
 929#define DP_SET_POWER                        0x600
 930# define DP_SET_POWER_D0                    0x1
 931# define DP_SET_POWER_D3                    0x2
 932# define DP_SET_POWER_MASK                  0x3
 933# define DP_SET_POWER_D3_AUX_ON             0x5
 934
 935/* eDP-specific */
 936#define DP_EDP_DPCD_REV                     0x700    /* eDP 1.2 */
 937# define DP_EDP_11                          0x00
 938# define DP_EDP_12                          0x01
 939# define DP_EDP_13                          0x02
 940# define DP_EDP_14                          0x03
 941# define DP_EDP_14a                         0x04    /* eDP 1.4a */
 942# define DP_EDP_14b                         0x05    /* eDP 1.4b */
 943
 944#define DP_EDP_GENERAL_CAP_1                0x701
 945# define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP           (1 << 0)
 946# define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP                (1 << 1)
 947# define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP                (1 << 2)
 948# define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP          (1 << 3)
 949# define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP          (1 << 4)
 950# define DP_EDP_FRC_ENABLE_CAP                          (1 << 5)
 951# define DP_EDP_COLOR_ENGINE_CAP                        (1 << 6)
 952# define DP_EDP_SET_POWER_CAP                           (1 << 7)
 953
 954#define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP     0x702
 955# define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP        (1 << 0)
 956# define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP        (1 << 1)
 957# define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT         (1 << 2)
 958# define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP           (1 << 3)
 959# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP     (1 << 4)
 960# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP              (1 << 5)
 961# define DP_EDP_DYNAMIC_BACKLIGHT_CAP                   (1 << 6)
 962# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP             (1 << 7)
 963
 964#define DP_EDP_GENERAL_CAP_2                0x703
 965# define DP_EDP_OVERDRIVE_ENGINE_ENABLED                (1 << 0)
 966
 967#define DP_EDP_GENERAL_CAP_3                0x704    /* eDP 1.4 */
 968# define DP_EDP_X_REGION_CAP_MASK                       (0xf << 0)
 969# define DP_EDP_X_REGION_CAP_SHIFT                      0
 970# define DP_EDP_Y_REGION_CAP_MASK                       (0xf << 4)
 971# define DP_EDP_Y_REGION_CAP_SHIFT                      4
 972
 973#define DP_EDP_DISPLAY_CONTROL_REGISTER     0x720
 974# define DP_EDP_BACKLIGHT_ENABLE                        (1 << 0)
 975# define DP_EDP_BLACK_VIDEO_ENABLE                      (1 << 1)
 976# define DP_EDP_FRC_ENABLE                              (1 << 2)
 977# define DP_EDP_COLOR_ENGINE_ENABLE                     (1 << 3)
 978# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE          (1 << 7)
 979
 980#define DP_EDP_BACKLIGHT_MODE_SET_REGISTER  0x721
 981# define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK             (3 << 0)
 982# define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM              (0 << 0)
 983# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET           (1 << 0)
 984# define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD             (2 << 0)
 985# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT          (3 << 0)
 986# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE  (1 << 2)
 987# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE           (1 << 3)
 988# define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE                (1 << 4)
 989# define DP_EDP_REGIONAL_BACKLIGHT_ENABLE               (1 << 5)
 990# define DP_EDP_UPDATE_REGION_BRIGHTNESS                (1 << 6) /* eDP 1.4 */
 991
 992#define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB     0x722
 993#define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB     0x723
 994
 995#define DP_EDP_PWMGEN_BIT_COUNT             0x724
 996#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN     0x725
 997#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX     0x726
 998# define DP_EDP_PWMGEN_BIT_COUNT_MASK       (0x1f << 0)
 999
1000#define DP_EDP_BACKLIGHT_CONTROL_STATUS     0x727
1001
1002#define DP_EDP_BACKLIGHT_FREQ_SET           0x728
1003# define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ     27000
1004
1005#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB   0x72a
1006#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID   0x72b
1007#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB   0x72c
1008
1009#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB   0x72d
1010#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID   0x72e
1011#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB   0x72f
1012
1013#define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET   0x732
1014#define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET   0x733
1015
1016#define DP_EDP_REGIONAL_BACKLIGHT_BASE      0x740    /* eDP 1.4 */
1017#define DP_EDP_REGIONAL_BACKLIGHT_0         0x741    /* eDP 1.4 */
1018
1019#define DP_EDP_MSO_LINK_CAPABILITIES        0x7a4    /* eDP 1.4 */
1020# define DP_EDP_MSO_NUMBER_OF_LINKS_MASK    (7 << 0)
1021# define DP_EDP_MSO_NUMBER_OF_LINKS_SHIFT   0
1022# define DP_EDP_MSO_INDEPENDENT_LINK_BIT    (1 << 3)
1023
1024/* Sideband MSG Buffers */
1025#define DP_SIDEBAND_MSG_DOWN_REQ_BASE       0x1000   /* 1.2 MST */
1026#define DP_SIDEBAND_MSG_UP_REP_BASE         0x1200   /* 1.2 MST */
1027#define DP_SIDEBAND_MSG_DOWN_REP_BASE       0x1400   /* 1.2 MST */
1028#define DP_SIDEBAND_MSG_UP_REQ_BASE         0x1600   /* 1.2 MST */
1029
1030/* DPRX Event Status Indicator */
1031#define DP_SINK_COUNT_ESI                   0x2002   /* 1.2 */
1032/* 0-5 sink count */
1033# define DP_SINK_COUNT_CP_READY             (1 << 6)
1034
1035#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0   0x2003   /* 1.2 */
1036
1037#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1   0x2004   /* 1.2 */
1038# define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE    (1 << 0)
1039# define DP_LOCK_ACQUISITION_REQUEST         (1 << 1)
1040# define DP_CEC_IRQ                          (1 << 2)
1041
1042#define DP_LINK_SERVICE_IRQ_VECTOR_ESI0     0x2005   /* 1.2 */
1043# define RX_CAP_CHANGED                      (1 << 0)
1044# define LINK_STATUS_CHANGED                 (1 << 1)
1045# define STREAM_STATUS_CHANGED               (1 << 2)
1046# define HDMI_LINK_STATUS_CHANGED            (1 << 3)
1047# define CONNECTED_OFF_ENTRY_REQUESTED       (1 << 4)
1048
1049#define DP_PSR_ERROR_STATUS                 0x2006  /* XXX 1.2? */
1050# define DP_PSR_LINK_CRC_ERROR              (1 << 0)
1051# define DP_PSR_RFB_STORAGE_ERROR           (1 << 1)
1052# define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */
1053
1054#define DP_PSR_ESI                          0x2007  /* XXX 1.2? */
1055# define DP_PSR_CAPS_CHANGE                 (1 << 0)
1056
1057#define DP_PSR_STATUS                       0x2008  /* XXX 1.2? */
1058# define DP_PSR_SINK_INACTIVE               0
1059# define DP_PSR_SINK_ACTIVE_SRC_SYNCED      1
1060# define DP_PSR_SINK_ACTIVE_RFB             2
1061# define DP_PSR_SINK_ACTIVE_SINK_SYNCED     3
1062# define DP_PSR_SINK_ACTIVE_RESYNC          4
1063# define DP_PSR_SINK_INTERNAL_ERROR         7
1064# define DP_PSR_SINK_STATE_MASK             0x07
1065
1066#define DP_SYNCHRONIZATION_LATENCY_IN_SINK              0x2009 /* edp 1.4 */
1067# define DP_MAX_RESYNC_FRAME_COUNT_MASK                 (0xf << 0)
1068# define DP_MAX_RESYNC_FRAME_COUNT_SHIFT                0
1069# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK    (0xf << 4)
1070# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT   4
1071
1072#define DP_LAST_RECEIVED_PSR_SDP            0x200a /* eDP 1.2 */
1073# define DP_PSR_STATE_BIT                   (1 << 0) /* eDP 1.2 */
1074# define DP_UPDATE_RFB_BIT                  (1 << 1) /* eDP 1.2 */
1075# define DP_CRC_VALID_BIT                   (1 << 2) /* eDP 1.2 */
1076# define DP_SU_VALID                        (1 << 3) /* eDP 1.4 */
1077# define DP_FIRST_SCAN_LINE_SU_REGION       (1 << 4) /* eDP 1.4 */
1078# define DP_LAST_SCAN_LINE_SU_REGION        (1 << 5) /* eDP 1.4 */
1079# define DP_Y_COORDINATE_VALID              (1 << 6) /* eDP 1.4a */
1080
1081#define DP_RECEIVER_ALPM_STATUS             0x200b  /* eDP 1.4 */
1082# define DP_ALPM_LOCK_TIMEOUT_ERROR         (1 << 0)
1083
1084#define DP_LANE0_1_STATUS_ESI                  0x200c /* status same as 0x202 */
1085#define DP_LANE2_3_STATUS_ESI                  0x200d /* status same as 0x203 */
1086#define DP_LANE_ALIGN_STATUS_UPDATED_ESI       0x200e /* status same as 0x204 */
1087#define DP_SINK_STATUS_ESI                     0x200f /* status same as 0x205 */
1088
1089/* Extended Receiver Capability: See DP_DPCD_REV for definitions */
1090#define DP_DP13_DPCD_REV                    0x2200
1091
1092#define DP_DPRX_FEATURE_ENUMERATION_LIST    0x2210  /* DP 1.3 */
1093# define DP_GTC_CAP                                     (1 << 0)  /* DP 1.3 */
1094# define DP_SST_SPLIT_SDP_CAP                           (1 << 1)  /* DP 1.4 */
1095# define DP_AV_SYNC_CAP                                 (1 << 2)  /* DP 1.3 */
1096# define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED       (1 << 3)  /* DP 1.3 */
1097# define DP_VSC_EXT_VESA_SDP_SUPPORTED                  (1 << 4)  /* DP 1.4 */
1098# define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED         (1 << 5)  /* DP 1.4 */
1099# define DP_VSC_EXT_CEA_SDP_SUPPORTED                   (1 << 6)  /* DP 1.4 */
1100# define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED          (1 << 7)  /* DP 1.4 */
1101
1102#define DP_128B132B_SUPPORTED_LINK_RATES       0x2215 /* 2.0 */
1103# define DP_UHBR10                             (1 << 0)
1104# define DP_UHBR20                             (1 << 1)
1105# define DP_UHBR13_5                           (1 << 2)
1106
1107#define DP_128B132B_TRAINING_AUX_RD_INTERVAL   0x2216 /* 2.0 */
1108# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f
1109
1110/* Protocol Converter Extension */
1111/* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
1112#define DP_CEC_TUNNELING_CAPABILITY            0x3000
1113# define DP_CEC_TUNNELING_CAPABLE               (1 << 0)
1114# define DP_CEC_SNOOPING_CAPABLE                (1 << 1)
1115# define DP_CEC_MULTIPLE_LA_CAPABLE             (1 << 2)
1116
1117#define DP_CEC_TUNNELING_CONTROL               0x3001
1118# define DP_CEC_TUNNELING_ENABLE                (1 << 0)
1119# define DP_CEC_SNOOPING_ENABLE                 (1 << 1)
1120
1121#define DP_CEC_RX_MESSAGE_INFO                 0x3002
1122# define DP_CEC_RX_MESSAGE_LEN_MASK             (0xf << 0)
1123# define DP_CEC_RX_MESSAGE_LEN_SHIFT            0
1124# define DP_CEC_RX_MESSAGE_HPD_STATE            (1 << 4)
1125# define DP_CEC_RX_MESSAGE_HPD_LOST             (1 << 5)
1126# define DP_CEC_RX_MESSAGE_ACKED                (1 << 6)
1127# define DP_CEC_RX_MESSAGE_ENDED                (1 << 7)
1128
1129#define DP_CEC_TX_MESSAGE_INFO                 0x3003
1130# define DP_CEC_TX_MESSAGE_LEN_MASK             (0xf << 0)
1131# define DP_CEC_TX_MESSAGE_LEN_SHIFT            0
1132# define DP_CEC_TX_RETRY_COUNT_MASK             (0x7 << 4)
1133# define DP_CEC_TX_RETRY_COUNT_SHIFT            4
1134# define DP_CEC_TX_MESSAGE_SEND                 (1 << 7)
1135
1136#define DP_CEC_TUNNELING_IRQ_FLAGS             0x3004
1137# define DP_CEC_RX_MESSAGE_INFO_VALID           (1 << 0)
1138# define DP_CEC_RX_MESSAGE_OVERFLOW             (1 << 1)
1139# define DP_CEC_TX_MESSAGE_SENT                 (1 << 4)
1140# define DP_CEC_TX_LINE_ERROR                   (1 << 5)
1141# define DP_CEC_TX_ADDRESS_NACK_ERROR           (1 << 6)
1142# define DP_CEC_TX_DATA_NACK_ERROR              (1 << 7)
1143
1144#define DP_CEC_LOGICAL_ADDRESS_MASK            0x300E /* 0x300F word */
1145# define DP_CEC_LOGICAL_ADDRESS_0               (1 << 0)
1146# define DP_CEC_LOGICAL_ADDRESS_1               (1 << 1)
1147# define DP_CEC_LOGICAL_ADDRESS_2               (1 << 2)
1148# define DP_CEC_LOGICAL_ADDRESS_3               (1 << 3)
1149# define DP_CEC_LOGICAL_ADDRESS_4               (1 << 4)
1150# define DP_CEC_LOGICAL_ADDRESS_5               (1 << 5)
1151# define DP_CEC_LOGICAL_ADDRESS_6               (1 << 6)
1152# define DP_CEC_LOGICAL_ADDRESS_7               (1 << 7)
1153#define DP_CEC_LOGICAL_ADDRESS_MASK_2          0x300F /* 0x300E word */
1154# define DP_CEC_LOGICAL_ADDRESS_8               (1 << 0)
1155# define DP_CEC_LOGICAL_ADDRESS_9               (1 << 1)
1156# define DP_CEC_LOGICAL_ADDRESS_10              (1 << 2)
1157# define DP_CEC_LOGICAL_ADDRESS_11              (1 << 3)
1158# define DP_CEC_LOGICAL_ADDRESS_12              (1 << 4)
1159# define DP_CEC_LOGICAL_ADDRESS_13              (1 << 5)
1160# define DP_CEC_LOGICAL_ADDRESS_14              (1 << 6)
1161# define DP_CEC_LOGICAL_ADDRESS_15              (1 << 7)
1162
1163#define DP_CEC_RX_MESSAGE_BUFFER               0x3010
1164#define DP_CEC_TX_MESSAGE_BUFFER               0x3020
1165#define DP_CEC_MESSAGE_BUFFER_LENGTH             0x10
1166
1167/* PCON CONFIGURE-1 FRL FOR HDMI SINK */
1168#define DP_PCON_HDMI_LINK_CONFIG_1             0x305A
1169# define DP_PCON_ENABLE_MAX_FRL_BW             (7 << 0)
1170# define DP_PCON_ENABLE_MAX_BW_0GBPS           0
1171# define DP_PCON_ENABLE_MAX_BW_9GBPS           1
1172# define DP_PCON_ENABLE_MAX_BW_18GBPS          2
1173# define DP_PCON_ENABLE_MAX_BW_24GBPS          3
1174# define DP_PCON_ENABLE_MAX_BW_32GBPS          4
1175# define DP_PCON_ENABLE_MAX_BW_40GBPS          5
1176# define DP_PCON_ENABLE_MAX_BW_48GBPS          6
1177# define DP_PCON_ENABLE_SOURCE_CTL_MODE       (1 << 3)
1178# define DP_PCON_ENABLE_CONCURRENT_LINK       (1 << 4)
1179# define DP_PCON_ENABLE_SEQUENTIAL_LINK       (0 << 4)
1180# define DP_PCON_ENABLE_LINK_FRL_MODE         (1 << 5)
1181# define DP_PCON_ENABLE_HPD_READY             (1 << 6)
1182# define DP_PCON_ENABLE_HDMI_LINK             (1 << 7)
1183
1184/* PCON CONFIGURE-2 FRL FOR HDMI SINK */
1185#define DP_PCON_HDMI_LINK_CONFIG_2            0x305B
1186# define DP_PCON_MAX_LINK_BW_MASK             (0x3F << 0)
1187# define DP_PCON_FRL_BW_MASK_9GBPS            (1 << 0)
1188# define DP_PCON_FRL_BW_MASK_18GBPS           (1 << 1)
1189# define DP_PCON_FRL_BW_MASK_24GBPS           (1 << 2)
1190# define DP_PCON_FRL_BW_MASK_32GBPS           (1 << 3)
1191# define DP_PCON_FRL_BW_MASK_40GBPS           (1 << 4)
1192# define DP_PCON_FRL_BW_MASK_48GBPS           (1 << 5)
1193# define DP_PCON_FRL_LINK_TRAIN_EXTENDED      (1 << 6)
1194# define DP_PCON_FRL_LINK_TRAIN_NORMAL        (0 << 6)
1195
1196/* PCON HDMI LINK STATUS */
1197#define DP_PCON_HDMI_TX_LINK_STATUS           0x303B
1198# define DP_PCON_HDMI_TX_LINK_ACTIVE          (1 << 0)
1199# define DP_PCON_FRL_READY                    (1 << 1)
1200
1201/* PCON HDMI POST FRL STATUS */
1202#define DP_PCON_HDMI_POST_FRL_STATUS          0x3036
1203# define DP_PCON_HDMI_LINK_MODE               (1 << 0)
1204# define DP_PCON_HDMI_MODE_TMDS               0
1205# define DP_PCON_HDMI_MODE_FRL                1
1206# define DP_PCON_HDMI_FRL_TRAINED_BW          (0x3F << 1)
1207# define DP_PCON_FRL_TRAINED_BW_9GBPS         (1 << 1)
1208# define DP_PCON_FRL_TRAINED_BW_18GBPS        (1 << 2)
1209# define DP_PCON_FRL_TRAINED_BW_24GBPS        (1 << 3)
1210# define DP_PCON_FRL_TRAINED_BW_32GBPS        (1 << 4)
1211# define DP_PCON_FRL_TRAINED_BW_40GBPS        (1 << 5)
1212# define DP_PCON_FRL_TRAINED_BW_48GBPS        (1 << 6)
1213
1214#define DP_PROTOCOL_CONVERTER_CONTROL_0         0x3050 /* DP 1.3 */
1215# define DP_HDMI_DVI_OUTPUT_CONFIG              (1 << 0) /* DP 1.3 */
1216#define DP_PROTOCOL_CONVERTER_CONTROL_1         0x3051 /* DP 1.3 */
1217# define DP_CONVERSION_TO_YCBCR420_ENABLE       (1 << 0) /* DP 1.3 */
1218# define DP_HDMI_EDID_PROCESSING_DISABLE        (1 << 1) /* DP 1.4 */
1219# define DP_HDMI_AUTONOMOUS_SCRAMBLING_DISABLE  (1 << 2) /* DP 1.4 */
1220# define DP_HDMI_FORCE_SCRAMBLING               (1 << 3) /* DP 1.4 */
1221#define DP_PROTOCOL_CONVERTER_CONTROL_2         0x3052 /* DP 1.3 */
1222# define DP_CONVERSION_TO_YCBCR422_ENABLE       (1 << 0) /* DP 1.3 */
1223# define DP_PCON_ENABLE_DSC_ENCODER             (1 << 1)
1224# define DP_PCON_ENCODER_PPS_OVERRIDE_MASK      (0x3 << 2)
1225# define DP_PCON_ENC_PPS_OVERRIDE_DISABLED      0
1226# define DP_PCON_ENC_PPS_OVERRIDE_EN_PARAMS     1
1227# define DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER     2
1228# define DP_CONVERSION_RGB_YCBCR_MASK          (7 << 4)
1229# define DP_CONVERSION_BT601_RGB_YCBCR_ENABLE  (1 << 4)
1230# define DP_CONVERSION_BT709_RGB_YCBCR_ENABLE  (1 << 5)
1231# define DP_CONVERSION_BT2020_RGB_YCBCR_ENABLE (1 << 6)
1232
1233/* PCON Downstream HDMI ERROR Status per Lane */
1234#define DP_PCON_HDMI_ERROR_STATUS_LN0          0x3037
1235#define DP_PCON_HDMI_ERROR_STATUS_LN1          0x3038
1236#define DP_PCON_HDMI_ERROR_STATUS_LN2          0x3039
1237#define DP_PCON_HDMI_ERROR_STATUS_LN3          0x303A
1238# define DP_PCON_HDMI_ERROR_COUNT_MASK         (0x7 << 0)
1239# define DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS   (1 << 0)
1240# define DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS     (1 << 1)
1241# define DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS (1 << 2)
1242
1243/* PCON HDMI CONFIG PPS Override Buffer
1244 * Valid Offsets to be added to Base : 0-127
1245 */
1246#define DP_PCON_HDMI_PPS_OVERRIDE_BASE        0x3100
1247
1248/* PCON HDMI CONFIG PPS Override Parameter: Slice height
1249 * Offset-0 8LSBs of the Slice height.
1250 * Offset-1 8MSBs of the Slice height.
1251 */
1252#define DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT    0x3180
1253
1254/* PCON HDMI CONFIG PPS Override Parameter: Slice width
1255 * Offset-0 8LSBs of the Slice width.
1256 * Offset-1 8MSBs of the Slice width.
1257 */
1258#define DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH    0x3182
1259
1260/* PCON HDMI CONFIG PPS Override Parameter: bits_per_pixel
1261 * Offset-0 8LSBs of the bits_per_pixel.
1262 * Offset-1 2MSBs of the bits_per_pixel.
1263 */
1264#define DP_PCON_HDMI_PPS_OVRD_BPP            0x3184
1265
1266/* HDCP 1.3 and HDCP 2.2 */
1267#define DP_AUX_HDCP_BKSV                0x68000
1268#define DP_AUX_HDCP_RI_PRIME            0x68005
1269#define DP_AUX_HDCP_AKSV                0x68007
1270#define DP_AUX_HDCP_AN                  0x6800C
1271#define DP_AUX_HDCP_V_PRIME(h)          (0x68014 + h * 4)
1272#define DP_AUX_HDCP_BCAPS               0x68028
1273# define DP_BCAPS_REPEATER_PRESENT      BIT(1)
1274# define DP_BCAPS_HDCP_CAPABLE          BIT(0)
1275#define DP_AUX_HDCP_BSTATUS             0x68029
1276# define DP_BSTATUS_REAUTH_REQ          BIT(3)
1277# define DP_BSTATUS_LINK_FAILURE        BIT(2)
1278# define DP_BSTATUS_R0_PRIME_READY      BIT(1)
1279# define DP_BSTATUS_READY               BIT(0)
1280#define DP_AUX_HDCP_BINFO               0x6802A
1281#define DP_AUX_HDCP_KSV_FIFO            0x6802C
1282#define DP_AUX_HDCP_AINFO               0x6803B
1283
1284/* DP HDCP2.2 parameter offsets in DPCD address space */
1285#define DP_HDCP_2_2_REG_RTX_OFFSET              0x69000
1286#define DP_HDCP_2_2_REG_TXCAPS_OFFSET           0x69008
1287#define DP_HDCP_2_2_REG_CERT_RX_OFFSET          0x6900B
1288#define DP_HDCP_2_2_REG_RRX_OFFSET              0x69215
1289#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET          0x6921D
1290#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET         0x69220
1291#define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET        0x692A0
1292#define DP_HDCP_2_2_REG_M_OFFSET                0x692B0
1293#define DP_HDCP_2_2_REG_HPRIME_OFFSET           0x692C0
1294#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET        0x692E0
1295#define DP_HDCP_2_2_REG_RN_OFFSET               0x692F0
1296#define DP_HDCP_2_2_REG_LPRIME_OFFSET           0x692F8
1297#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET         0x69318
1298#define DP_HDCP_2_2_REG_RIV_OFFSET              0x69328
1299#define DP_HDCP_2_2_REG_RXINFO_OFFSET           0x69330
1300#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET        0x69332
1301#define DP_HDCP_2_2_REG_VPRIME_OFFSET           0x69335
1302#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET     0x69345
1303#define DP_HDCP_2_2_REG_V_OFFSET                0x693E0
1304#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET        0x693F0
1305#define DP_HDCP_2_2_REG_K_OFFSET                0x693F3
1306#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET   0x693F5
1307#define DP_HDCP_2_2_REG_MPRIME_OFFSET           0x69473
1308#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET         0x69493
1309#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET      0x69494
1310#define DP_HDCP_2_2_REG_DBG_OFFSET              0x69518
1311
1312/* LTTPR: Link Training (LT)-tunable PHY Repeaters */
1313#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */
1314#define DP_MAX_LINK_RATE_PHY_REPEATER                       0xf0001 /* 1.4a */
1315#define DP_PHY_REPEATER_CNT                                 0xf0002 /* 1.3 */
1316#define DP_PHY_REPEATER_MODE                                0xf0003 /* 1.3 */
1317#define DP_MAX_LANE_COUNT_PHY_REPEATER                      0xf0004 /* 1.4a */
1318#define DP_Repeater_FEC_CAPABILITY                          0xf0004 /* 1.4 */
1319#define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT               0xf0005 /* 1.4a */
1320
1321enum drm_dp_phy {
1322        DP_PHY_DPRX,
1323
1324        DP_PHY_LTTPR1,
1325        DP_PHY_LTTPR2,
1326        DP_PHY_LTTPR3,
1327        DP_PHY_LTTPR4,
1328        DP_PHY_LTTPR5,
1329        DP_PHY_LTTPR6,
1330        DP_PHY_LTTPR7,
1331        DP_PHY_LTTPR8,
1332
1333        DP_MAX_LTTPR_COUNT = DP_PHY_LTTPR8,
1334};
1335
1336#define DP_PHY_LTTPR(i)                                     (DP_PHY_LTTPR1 + (i))
1337
1338#define __DP_LTTPR1_BASE                                    0xf0010 /* 1.3 */
1339#define __DP_LTTPR2_BASE                                    0xf0060 /* 1.3 */
1340#define DP_LTTPR_BASE(dp_phy) \
1341        (__DP_LTTPR1_BASE + (__DP_LTTPR2_BASE - __DP_LTTPR1_BASE) * \
1342                ((dp_phy) - DP_PHY_LTTPR1))
1343
1344#define DP_LTTPR_REG(dp_phy, lttpr1_reg) \
1345        (DP_LTTPR_BASE(dp_phy) - DP_LTTPR_BASE(DP_PHY_LTTPR1) + (lttpr1_reg))
1346
1347#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1               0xf0010 /* 1.3 */
1348#define DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy) \
1349        DP_LTTPR_REG(dp_phy, DP_TRAINING_PATTERN_SET_PHY_REPEATER1)
1350
1351#define DP_TRAINING_LANE0_SET_PHY_REPEATER1                 0xf0011 /* 1.3 */
1352#define DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy) \
1353        DP_LTTPR_REG(dp_phy, DP_TRAINING_LANE0_SET_PHY_REPEATER1)
1354
1355#define DP_TRAINING_LANE1_SET_PHY_REPEATER1                 0xf0012 /* 1.3 */
1356#define DP_TRAINING_LANE2_SET_PHY_REPEATER1                 0xf0013 /* 1.3 */
1357#define DP_TRAINING_LANE3_SET_PHY_REPEATER1                 0xf0014 /* 1.3 */
1358#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1           0xf0020 /* 1.4a */
1359#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy)        \
1360        DP_LTTPR_REG(dp_phy, DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1)
1361
1362#define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1             0xf0021 /* 1.4a */
1363# define DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED                 BIT(0)
1364# define DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED                  BIT(1)
1365
1366#define DP_LANE0_1_STATUS_PHY_REPEATER1                     0xf0030 /* 1.3 */
1367#define DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy) \
1368        DP_LTTPR_REG(dp_phy, DP_LANE0_1_STATUS_PHY_REPEATER1)
1369
1370#define DP_LANE2_3_STATUS_PHY_REPEATER1                     0xf0031 /* 1.3 */
1371
1372#define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1          0xf0032 /* 1.3 */
1373#define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1             0xf0033 /* 1.3 */
1374#define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1             0xf0034 /* 1.3 */
1375#define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1           0xf0035 /* 1.3 */
1376#define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1           0xf0037 /* 1.3 */
1377#define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1           0xf0039 /* 1.3 */
1378#define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1           0xf003b /* 1.3 */
1379#define DP_FEC_STATUS_PHY_REPEATER1                         0xf0290 /* 1.4 */
1380#define DP_FEC_ERROR_COUNT_PHY_REPEATER1                    0xf0291 /* 1.4 */
1381#define DP_FEC_CAPABILITY_PHY_REPEATER1                     0xf0294 /* 1.4a */
1382
1383/* Repeater modes */
1384#define DP_PHY_REPEATER_MODE_TRANSPARENT                    0x55    /* 1.3 */
1385#define DP_PHY_REPEATER_MODE_NON_TRANSPARENT                0xaa    /* 1.3 */
1386
1387/* DP HDCP message start offsets in DPCD address space */
1388#define DP_HDCP_2_2_AKE_INIT_OFFSET             DP_HDCP_2_2_REG_RTX_OFFSET
1389#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET        DP_HDCP_2_2_REG_CERT_RX_OFFSET
1390#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET     DP_HDCP_2_2_REG_EKPUB_KM_OFFSET
1391#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET        DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET
1392#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET      DP_HDCP_2_2_REG_HPRIME_OFFSET
1393#define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \
1394                                                DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET
1395#define DP_HDCP_2_2_LC_INIT_OFFSET              DP_HDCP_2_2_REG_RN_OFFSET
1396#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET       DP_HDCP_2_2_REG_LPRIME_OFFSET
1397#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET         DP_HDCP_2_2_REG_EDKEY_KS_OFFSET
1398#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET
1399#define DP_HDCP_2_2_REP_SEND_ACK_OFFSET         DP_HDCP_2_2_REG_V_OFFSET
1400#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET    DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET
1401#define DP_HDCP_2_2_REP_STREAM_READY_OFFSET     DP_HDCP_2_2_REG_MPRIME_OFFSET
1402
1403#define HDCP_2_2_DP_RXSTATUS_LEN                1
1404#define HDCP_2_2_DP_RXSTATUS_READY(x)           ((x) & BIT(0))
1405#define HDCP_2_2_DP_RXSTATUS_H_PRIME(x)         ((x) & BIT(1))
1406#define HDCP_2_2_DP_RXSTATUS_PAIRING(x)         ((x) & BIT(2))
1407#define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x)      ((x) & BIT(3))
1408#define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x)     ((x) & BIT(4))
1409
1410/* DP 1.2 Sideband message defines */
1411/* peer device type - DP 1.2a Table 2-92 */
1412#define DP_PEER_DEVICE_NONE             0x0
1413#define DP_PEER_DEVICE_SOURCE_OR_SST    0x1
1414#define DP_PEER_DEVICE_MST_BRANCHING    0x2
1415#define DP_PEER_DEVICE_SST_SINK         0x3
1416#define DP_PEER_DEVICE_DP_LEGACY_CONV   0x4
1417
1418/* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
1419#define DP_GET_MSG_TRANSACTION_VERSION  0x00 /* DP 1.3 */
1420#define DP_LINK_ADDRESS                 0x01
1421#define DP_CONNECTION_STATUS_NOTIFY     0x02
1422#define DP_ENUM_PATH_RESOURCES          0x10
1423#define DP_ALLOCATE_PAYLOAD             0x11
1424#define DP_QUERY_PAYLOAD                0x12
1425#define DP_RESOURCE_STATUS_NOTIFY       0x13
1426#define DP_CLEAR_PAYLOAD_ID_TABLE       0x14
1427#define DP_REMOTE_DPCD_READ             0x20
1428#define DP_REMOTE_DPCD_WRITE            0x21
1429#define DP_REMOTE_I2C_READ              0x22
1430#define DP_REMOTE_I2C_WRITE             0x23
1431#define DP_POWER_UP_PHY                 0x24
1432#define DP_POWER_DOWN_PHY               0x25
1433#define DP_SINK_EVENT_NOTIFY            0x30
1434#define DP_QUERY_STREAM_ENC_STATUS      0x38
1435#define  DP_QUERY_STREAM_ENC_STATUS_STATE_NO_EXIST      0
1436#define  DP_QUERY_STREAM_ENC_STATUS_STATE_INACTIVE      1
1437#define  DP_QUERY_STREAM_ENC_STATUS_STATE_ACTIVE        2
1438
1439/* DP 1.2 MST sideband reply types */
1440#define DP_SIDEBAND_REPLY_ACK           0x00
1441#define DP_SIDEBAND_REPLY_NAK           0x01
1442
1443/* DP 1.2 MST sideband nak reasons - table 2.84 */
1444#define DP_NAK_WRITE_FAILURE            0x01
1445#define DP_NAK_INVALID_READ             0x02
1446#define DP_NAK_CRC_FAILURE              0x03
1447#define DP_NAK_BAD_PARAM                0x04
1448#define DP_NAK_DEFER                    0x05
1449#define DP_NAK_LINK_FAILURE             0x06
1450#define DP_NAK_NO_RESOURCES             0x07
1451#define DP_NAK_DPCD_FAIL                0x08
1452#define DP_NAK_I2C_NAK                  0x09
1453#define DP_NAK_ALLOCATE_FAIL            0x0a
1454
1455#define MODE_I2C_START  1
1456#define MODE_I2C_WRITE  2
1457#define MODE_I2C_READ   4
1458#define MODE_I2C_STOP   8
1459
1460/* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */
1461#define DP_MST_PHYSICAL_PORT_0 0
1462#define DP_MST_LOGICAL_PORT_0 8
1463
1464#define DP_LINK_CONSTANT_N_VALUE 0x8000
1465#define DP_LINK_STATUS_SIZE        6
1466bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
1467                          int lane_count);
1468bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
1469                              int lane_count);
1470u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
1471                                     int lane);
1472u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
1473                                          int lane);
1474u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE],
1475                                         unsigned int lane);
1476
1477#define DP_BRANCH_OUI_HEADER_SIZE       0xc
1478#define DP_RECEIVER_CAP_SIZE            0xf
1479#define DP_DSC_RECEIVER_CAP_SIZE        0xf
1480#define EDP_PSR_RECEIVER_CAP_SIZE       2
1481#define EDP_DISPLAY_CTL_CAP_SIZE        3
1482#define DP_LTTPR_COMMON_CAP_SIZE        8
1483#define DP_LTTPR_PHY_CAP_SIZE           3
1484
1485void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1486void drm_dp_lttpr_link_train_clock_recovery_delay(void);
1487void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1488void drm_dp_lttpr_link_train_channel_eq_delay(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
1489
1490u8 drm_dp_link_rate_to_bw_code(int link_rate);
1491int drm_dp_bw_code_to_link_rate(u8 link_bw);
1492
1493#define DP_SDP_AUDIO_TIMESTAMP          0x01
1494#define DP_SDP_AUDIO_STREAM             0x02
1495#define DP_SDP_EXTENSION                0x04 /* DP 1.1 */
1496#define DP_SDP_AUDIO_COPYMANAGEMENT     0x05 /* DP 1.2 */
1497#define DP_SDP_ISRC                     0x06 /* DP 1.2 */
1498#define DP_SDP_VSC                      0x07 /* DP 1.2 */
1499#define DP_SDP_CAMERA_GENERIC(i)        (0x08 + (i)) /* 0-7, DP 1.3 */
1500#define DP_SDP_PPS                      0x10 /* DP 1.4 */
1501#define DP_SDP_VSC_EXT_VESA             0x20 /* DP 1.4 */
1502#define DP_SDP_VSC_EXT_CEA              0x21 /* DP 1.4 */
1503/* 0x80+ CEA-861 infoframe types */
1504
1505/**
1506 * struct dp_sdp_header - DP secondary data packet header
1507 * @HB0: Secondary Data Packet ID
1508 * @HB1: Secondary Data Packet Type
1509 * @HB2: Secondary Data Packet Specific header, Byte 0
1510 * @HB3: Secondary Data packet Specific header, Byte 1
1511 */
1512struct dp_sdp_header {
1513        u8 HB0;
1514        u8 HB1;
1515        u8 HB2;
1516        u8 HB3;
1517} __packed;
1518
1519#define EDP_SDP_HEADER_REVISION_MASK            0x1F
1520#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES      0x1F
1521#define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F
1522
1523/**
1524 * struct dp_sdp - DP secondary data packet
1525 * @sdp_header: DP secondary data packet header
1526 * @db: DP secondaray data packet data blocks
1527 * VSC SDP Payload for PSR
1528 * db[0]: Stereo Interface
1529 * db[1]: 0 - PSR State; 1 - Update RFB; 2 - CRC Valid
1530 * db[2]: CRC value bits 7:0 of the R or Cr component
1531 * db[3]: CRC value bits 15:8 of the R or Cr component
1532 * db[4]: CRC value bits 7:0 of the G or Y component
1533 * db[5]: CRC value bits 15:8 of the G or Y component
1534 * db[6]: CRC value bits 7:0 of the B or Cb component
1535 * db[7]: CRC value bits 15:8 of the B or Cb component
1536 * db[8] - db[31]: Reserved
1537 * VSC SDP Payload for Pixel Encoding/Colorimetry Format
1538 * db[0] - db[15]: Reserved
1539 * db[16]: Pixel Encoding and Colorimetry Formats
1540 * db[17]: Dynamic Range and Component Bit Depth
1541 * db[18]: Content Type
1542 * db[19] - db[31]: Reserved
1543 */
1544struct dp_sdp {
1545        struct dp_sdp_header sdp_header;
1546        u8 db[32];
1547} __packed;
1548
1549#define EDP_VSC_PSR_STATE_ACTIVE        (1<<0)
1550#define EDP_VSC_PSR_UPDATE_RFB          (1<<1)
1551#define EDP_VSC_PSR_CRC_VALUES_VALID    (1<<2)
1552
1553/**
1554 * enum dp_pixelformat - drm DP Pixel encoding formats
1555 *
1556 * This enum is used to indicate DP VSC SDP Pixel encoding formats.
1557 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1558 * DB18]
1559 *
1560 * @DP_PIXELFORMAT_RGB: RGB pixel encoding format
1561 * @DP_PIXELFORMAT_YUV444: YCbCr 4:4:4 pixel encoding format
1562 * @DP_PIXELFORMAT_YUV422: YCbCr 4:2:2 pixel encoding format
1563 * @DP_PIXELFORMAT_YUV420: YCbCr 4:2:0 pixel encoding format
1564 * @DP_PIXELFORMAT_Y_ONLY: Y Only pixel encoding format
1565 * @DP_PIXELFORMAT_RAW: RAW pixel encoding format
1566 * @DP_PIXELFORMAT_RESERVED: Reserved pixel encoding format
1567 */
1568enum dp_pixelformat {
1569        DP_PIXELFORMAT_RGB = 0,
1570        DP_PIXELFORMAT_YUV444 = 0x1,
1571        DP_PIXELFORMAT_YUV422 = 0x2,
1572        DP_PIXELFORMAT_YUV420 = 0x3,
1573        DP_PIXELFORMAT_Y_ONLY = 0x4,
1574        DP_PIXELFORMAT_RAW = 0x5,
1575        DP_PIXELFORMAT_RESERVED = 0x6,
1576};
1577
1578/**
1579 * enum dp_colorimetry - drm DP Colorimetry formats
1580 *
1581 * This enum is used to indicate DP VSC SDP Colorimetry formats.
1582 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1583 * DB18] and a name of enum member follows DRM_MODE_COLORIMETRY definition.
1584 *
1585 * @DP_COLORIMETRY_DEFAULT: sRGB (IEC 61966-2-1) or
1586 *                          ITU-R BT.601 colorimetry format
1587 * @DP_COLORIMETRY_RGB_WIDE_FIXED: RGB wide gamut fixed point colorimetry format
1588 * @DP_COLORIMETRY_BT709_YCC: ITU-R BT.709 colorimetry format
1589 * @DP_COLORIMETRY_RGB_WIDE_FLOAT: RGB wide gamut floating point
1590 *                                 (scRGB (IEC 61966-2-2)) colorimetry format
1591 * @DP_COLORIMETRY_XVYCC_601: xvYCC601 colorimetry format
1592 * @DP_COLORIMETRY_OPRGB: OpRGB colorimetry format
1593 * @DP_COLORIMETRY_XVYCC_709: xvYCC709 colorimetry format
1594 * @DP_COLORIMETRY_DCI_P3_RGB: DCI-P3 (SMPTE RP 431-2) colorimetry format
1595 * @DP_COLORIMETRY_SYCC_601: sYCC601 colorimetry format
1596 * @DP_COLORIMETRY_RGB_CUSTOM: RGB Custom Color Profile colorimetry format
1597 * @DP_COLORIMETRY_OPYCC_601: opYCC601 colorimetry format
1598 * @DP_COLORIMETRY_BT2020_RGB: ITU-R BT.2020 R' G' B' colorimetry format
1599 * @DP_COLORIMETRY_BT2020_CYCC: ITU-R BT.2020 Y'c C'bc C'rc colorimetry format
1600 * @DP_COLORIMETRY_BT2020_YCC: ITU-R BT.2020 Y' C'b C'r colorimetry format
1601 */
1602enum dp_colorimetry {
1603        DP_COLORIMETRY_DEFAULT = 0,
1604        DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
1605        DP_COLORIMETRY_BT709_YCC = 0x1,
1606        DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
1607        DP_COLORIMETRY_XVYCC_601 = 0x2,
1608        DP_COLORIMETRY_OPRGB = 0x3,
1609        DP_COLORIMETRY_XVYCC_709 = 0x3,
1610        DP_COLORIMETRY_DCI_P3_RGB = 0x4,
1611        DP_COLORIMETRY_SYCC_601 = 0x4,
1612        DP_COLORIMETRY_RGB_CUSTOM = 0x5,
1613        DP_COLORIMETRY_OPYCC_601 = 0x5,
1614        DP_COLORIMETRY_BT2020_RGB = 0x6,
1615        DP_COLORIMETRY_BT2020_CYCC = 0x6,
1616        DP_COLORIMETRY_BT2020_YCC = 0x7,
1617};
1618
1619/**
1620 * enum dp_dynamic_range - drm DP Dynamic Range
1621 *
1622 * This enum is used to indicate DP VSC SDP Dynamic Range.
1623 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1624 * DB18]
1625 *
1626 * @DP_DYNAMIC_RANGE_VESA: VESA range
1627 * @DP_DYNAMIC_RANGE_CTA: CTA range
1628 */
1629enum dp_dynamic_range {
1630        DP_DYNAMIC_RANGE_VESA = 0,
1631        DP_DYNAMIC_RANGE_CTA = 1,
1632};
1633
1634/**
1635 * enum dp_content_type - drm DP Content Type
1636 *
1637 * This enum is used to indicate DP VSC SDP Content Types.
1638 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1639 * DB18]
1640 * CTA-861-G defines content types and expected processing by a sink device
1641 *
1642 * @DP_CONTENT_TYPE_NOT_DEFINED: Not defined type
1643 * @DP_CONTENT_TYPE_GRAPHICS: Graphics type
1644 * @DP_CONTENT_TYPE_PHOTO: Photo type
1645 * @DP_CONTENT_TYPE_VIDEO: Video type
1646 * @DP_CONTENT_TYPE_GAME: Game type
1647 */
1648enum dp_content_type {
1649        DP_CONTENT_TYPE_NOT_DEFINED = 0x00,
1650        DP_CONTENT_TYPE_GRAPHICS = 0x01,
1651        DP_CONTENT_TYPE_PHOTO = 0x02,
1652        DP_CONTENT_TYPE_VIDEO = 0x03,
1653        DP_CONTENT_TYPE_GAME = 0x04,
1654};
1655
1656/**
1657 * struct drm_dp_vsc_sdp - drm DP VSC SDP
1658 *
1659 * This structure represents a DP VSC SDP of drm
1660 * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and
1661 * [Table 2-117: VSC SDP Payload for DB16 through DB18]
1662 *
1663 * @sdp_type: secondary-data packet type
1664 * @revision: revision number
1665 * @length: number of valid data bytes
1666 * @pixelformat: pixel encoding format
1667 * @colorimetry: colorimetry format
1668 * @bpc: bit per color
1669 * @dynamic_range: dynamic range information
1670 * @content_type: CTA-861-G defines content types and expected processing by a sink device
1671 */
1672struct drm_dp_vsc_sdp {
1673        unsigned char sdp_type;
1674        unsigned char revision;
1675        unsigned char length;
1676        enum dp_pixelformat pixelformat;
1677        enum dp_colorimetry colorimetry;
1678        int bpc;
1679        enum dp_dynamic_range dynamic_range;
1680        enum dp_content_type content_type;
1681};
1682
1683void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
1684                        const struct drm_dp_vsc_sdp *vsc);
1685
1686int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
1687
1688static inline int
1689drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1690{
1691        return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
1692}
1693
1694static inline u8
1695drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1696{
1697        return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
1698}
1699
1700static inline bool
1701drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1702{
1703        return dpcd[DP_DPCD_REV] >= 0x11 &&
1704                (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
1705}
1706
1707static inline bool
1708drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1709{
1710        return dpcd[DP_DPCD_REV] >= 0x11 &&
1711                (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
1712}
1713
1714static inline bool
1715drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1716{
1717        return dpcd[DP_DPCD_REV] >= 0x12 &&
1718                dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;
1719}
1720
1721static inline bool
1722drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1723{
1724        return dpcd[DP_DPCD_REV] >= 0x14 &&
1725                dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED;
1726}
1727
1728static inline u8
1729drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1730{
1731        return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 :
1732                DP_TRAINING_PATTERN_MASK;
1733}
1734
1735static inline bool
1736drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1737{
1738        return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
1739}
1740
1741/* DP/eDP DSC support */
1742u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
1743                                   bool is_edp);
1744u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
1745int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
1746                                         u8 dsc_bpc[3]);
1747
1748static inline bool
1749drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1750{
1751        return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] &
1752                DP_DSC_DECOMPRESSION_IS_SUPPORTED;
1753}
1754
1755static inline u16
1756drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1757{
1758        return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] |
1759                (dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] &
1760                 DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK <<
1761                 DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT);
1762}
1763
1764static inline u32
1765drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1766{
1767        /* Max Slicewidth = Number of Pixels * 320 */
1768        return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] *
1769                DP_DSC_SLICE_WIDTH_MULTIPLIER;
1770}
1771
1772/* Forward Error Correction Support on DP 1.4 */
1773static inline bool
1774drm_dp_sink_supports_fec(const u8 fec_capable)
1775{
1776        return fec_capable & DP_FEC_CAPABLE;
1777}
1778
1779static inline bool
1780drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1781{
1782        return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B;
1783}
1784
1785static inline bool
1786drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1787{
1788        return dpcd[DP_EDP_CONFIGURATION_CAP] &
1789                        DP_ALTERNATE_SCRAMBLER_RESET_CAP;
1790}
1791
1792/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */
1793static inline bool
1794drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1795{
1796        return dpcd[DP_DOWN_STREAM_PORT_COUNT] &
1797                DP_MSA_TIMING_PAR_IGNORED;
1798}
1799
1800/*
1801 * DisplayPort AUX channel
1802 */
1803
1804/**
1805 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
1806 * @address: address of the (first) register to access
1807 * @request: contains the type of transaction (see DP_AUX_* macros)
1808 * @reply: upon completion, contains the reply type of the transaction
1809 * @buffer: pointer to a transmission or reception buffer
1810 * @size: size of @buffer
1811 */
1812struct drm_dp_aux_msg {
1813        unsigned int address;
1814        u8 request;
1815        u8 reply;
1816        void *buffer;
1817        size_t size;
1818};
1819
1820struct cec_adapter;
1821struct edid;
1822struct drm_connector;
1823
1824/**
1825 * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX
1826 * @lock: mutex protecting this struct
1827 * @adap: the CEC adapter for CEC-Tunneling-over-AUX support.
1828 * @connector: the connector this CEC adapter is associated with
1829 * @unregister_work: unregister the CEC adapter
1830 */
1831struct drm_dp_aux_cec {
1832        struct mutex lock;
1833        struct cec_adapter *adap;
1834        struct drm_connector *connector;
1835        struct delayed_work unregister_work;
1836};
1837
1838/**
1839 * struct drm_dp_aux - DisplayPort AUX channel
1840 * @name: user-visible name of this AUX channel and the I2C-over-AUX adapter
1841 * @ddc: I2C adapter that can be used for I2C-over-AUX communication
1842 * @dev: pointer to struct device that is the parent for this AUX channel
1843 * @crtc: backpointer to the crtc that is currently using this AUX channel
1844 * @hw_mutex: internal mutex used for locking transfers
1845 * @crc_work: worker that captures CRCs for each frame
1846 * @crc_count: counter of captured frame CRCs
1847 * @transfer: transfers a message representing a single AUX transaction
1848 *
1849 * The @dev field should be set to a pointer to the device that implements the
1850 * AUX channel.
1851 *
1852 * The @name field may be used to specify the name of the I2C adapter. If set to
1853 * %NULL, dev_name() of @dev will be used.
1854 *
1855 * Drivers provide a hardware-specific implementation of how transactions are
1856 * executed via the @transfer() function. A pointer to a &drm_dp_aux_msg
1857 * structure describing the transaction is passed into this function. Upon
1858 * success, the implementation should return the number of payload bytes that
1859 * were transferred, or a negative error-code on failure. Helpers propagate
1860 * errors from the @transfer() function, with the exception of the %-EBUSY
1861 * error, which causes a transaction to be retried. On a short, helpers will
1862 * return %-EPROTO to make it simpler to check for failure.
1863 *
1864 * An AUX channel can also be used to transport I2C messages to a sink. A
1865 * typical application of that is to access an EDID that's present in the sink
1866 * device. The @transfer() function can also be used to execute such
1867 * transactions. The drm_dp_aux_register() function registers an I2C adapter
1868 * that can be passed to drm_probe_ddc(). Upon removal, drivers should call
1869 * drm_dp_aux_unregister() to remove the I2C adapter. The I2C adapter uses long
1870 * transfers by default; if a partial response is received, the adapter will
1871 * drop down to the size given by the partial response for this transaction
1872 * only.
1873 *
1874 * Note that the aux helper code assumes that the @transfer() function only
1875 * modifies the reply field of the &drm_dp_aux_msg structure. The retry logic
1876 * and i2c helpers assume this is the case.
1877 */
1878struct drm_dp_aux {
1879        const char *name;
1880        struct i2c_adapter ddc;
1881        struct device *dev;
1882        struct drm_crtc *crtc;
1883        struct mutex hw_mutex;
1884        struct work_struct crc_work;
1885        u8 crc_count;
1886        ssize_t (*transfer)(struct drm_dp_aux *aux,
1887                            struct drm_dp_aux_msg *msg);
1888        /**
1889         * @i2c_nack_count: Counts I2C NACKs, used for DP validation.
1890         */
1891        unsigned i2c_nack_count;
1892        /**
1893         * @i2c_defer_count: Counts I2C DEFERs, used for DP validation.
1894         */
1895        unsigned i2c_defer_count;
1896        /**
1897         * @cec: struct containing fields used for CEC-Tunneling-over-AUX.
1898         */
1899        struct drm_dp_aux_cec cec;
1900        /**
1901         * @is_remote: Is this AUX CH actually using sideband messaging.
1902         */
1903        bool is_remote;
1904};
1905
1906ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
1907                         void *buffer, size_t size);
1908ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
1909                          void *buffer, size_t size);
1910
1911/**
1912 * drm_dp_dpcd_readb() - read a single byte from the DPCD
1913 * @aux: DisplayPort AUX channel
1914 * @offset: address of the register to read
1915 * @valuep: location where the value of the register will be stored
1916 *
1917 * Returns the number of bytes transferred (1) on success, or a negative
1918 * error code on failure.
1919 */
1920static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
1921                                        unsigned int offset, u8 *valuep)
1922{
1923        return drm_dp_dpcd_read(aux, offset, valuep, 1);
1924}
1925
1926/**
1927 * drm_dp_dpcd_writeb() - write a single byte to the DPCD
1928 * @aux: DisplayPort AUX channel
1929 * @offset: address of the register to write
1930 * @value: value to write to the register
1931 *
1932 * Returns the number of bytes transferred (1) on success, or a negative
1933 * error code on failure.
1934 */
1935static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
1936                                         unsigned int offset, u8 value)
1937{
1938        return drm_dp_dpcd_write(aux, offset, &value, 1);
1939}
1940
1941int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
1942                          u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1943
1944int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
1945                                 u8 status[DP_LINK_STATUS_SIZE]);
1946
1947int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
1948                                     enum drm_dp_phy dp_phy,
1949                                     u8 link_status[DP_LINK_STATUS_SIZE]);
1950
1951bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
1952                                    u8 real_edid_checksum);
1953
1954int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
1955                                const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1956                                u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]);
1957bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1958                               const u8 port_cap[4], u8 type);
1959bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1960                               const u8 port_cap[4],
1961                               const struct edid *edid);
1962int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1963                                   const u8 port_cap[4]);
1964int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1965                                     const u8 port_cap[4],
1966                                     const struct edid *edid);
1967int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1968                                     const u8 port_cap[4],
1969                                     const struct edid *edid);
1970int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1971                              const u8 port_cap[4],
1972                              const struct edid *edid);
1973bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1974                                       const u8 port_cap[4]);
1975bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1976                                             const u8 port_cap[4]);
1977struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev,
1978                                                const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1979                                                const u8 port_cap[4]);
1980int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
1981void drm_dp_downstream_debug(struct seq_file *m,
1982                             const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1983                             const u8 port_cap[4],
1984                             const struct edid *edid,
1985                             struct drm_dp_aux *aux);
1986enum drm_mode_subconnector
1987drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1988                         const u8 port_cap[4]);
1989void drm_dp_set_subconnector_property(struct drm_connector *connector,
1990                                      enum drm_connector_status status,
1991                                      const u8 *dpcd,
1992                                      const u8 port_cap[4]);
1993
1994struct drm_dp_desc;
1995bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
1996                                const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1997                                const struct drm_dp_desc *desc);
1998int drm_dp_read_sink_count(struct drm_dp_aux *aux);
1999
2000int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
2001                                  u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
2002int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
2003                               enum drm_dp_phy dp_phy,
2004                               u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
2005int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]);
2006int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
2007int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
2008bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
2009bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
2010
2011void drm_dp_remote_aux_init(struct drm_dp_aux *aux);
2012void drm_dp_aux_init(struct drm_dp_aux *aux);
2013int drm_dp_aux_register(struct drm_dp_aux *aux);
2014void drm_dp_aux_unregister(struct drm_dp_aux *aux);
2015
2016int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc);
2017int drm_dp_stop_crc(struct drm_dp_aux *aux);
2018
2019struct drm_dp_dpcd_ident {
2020        u8 oui[3];
2021        u8 device_id[6];
2022        u8 hw_rev;
2023        u8 sw_major_rev;
2024        u8 sw_minor_rev;
2025} __packed;
2026
2027/**
2028 * struct drm_dp_desc - DP branch/sink device descriptor
2029 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch).
2030 * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks.
2031 */
2032struct drm_dp_desc {
2033        struct drm_dp_dpcd_ident ident;
2034        u32 quirks;
2035};
2036
2037int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
2038                     bool is_branch);
2039
2040/**
2041 * enum drm_dp_quirk - Display Port sink/branch device specific quirks
2042 *
2043 * Display Port sink and branch devices in the wild have a variety of bugs, try
2044 * to collect them here. The quirks are shared, but it's up to the drivers to
2045 * implement workarounds for them.
2046 */
2047enum drm_dp_quirk {
2048        /**
2049         * @DP_DPCD_QUIRK_CONSTANT_N:
2050         *
2051         * The device requires main link attributes Mvid and Nvid to be limited
2052         * to 16 bits. So will give a constant value (0x8000) for compatability.
2053         */
2054        DP_DPCD_QUIRK_CONSTANT_N,
2055        /**
2056         * @DP_DPCD_QUIRK_NO_PSR:
2057         *
2058         * The device does not support PSR even if reports that it supports or
2059         * driver still need to implement proper handling for such device.
2060         */
2061        DP_DPCD_QUIRK_NO_PSR,
2062        /**
2063         * @DP_DPCD_QUIRK_NO_SINK_COUNT:
2064         *
2065         * The device does not set SINK_COUNT to a non-zero value.
2066         * The driver should ignore SINK_COUNT during detection. Note that
2067         * drm_dp_read_sink_count_cap() automatically checks for this quirk.
2068         */
2069        DP_DPCD_QUIRK_NO_SINK_COUNT,
2070        /**
2071         * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD:
2072         *
2073         * The device supports MST DSC despite not supporting Virtual DPCD.
2074         * The DSC caps can be read from the physical aux instead.
2075         */
2076        DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD,
2077        /**
2078         * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS:
2079         *
2080         * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite
2081         * the DP_MAX_LINK_RATE register reporting a lower max multiplier.
2082         */
2083        DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS,
2084};
2085
2086/**
2087 * drm_dp_has_quirk() - does the DP device have a specific quirk
2088 * @desc: Device descriptor filled by drm_dp_read_desc()
2089 * @quirk: Quirk to query for
2090 *
2091 * Return true if DP device identified by @desc has @quirk.
2092 */
2093static inline bool
2094drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
2095{
2096        return desc->quirks & BIT(quirk);
2097}
2098
2099#ifdef CONFIG_DRM_DP_CEC
2100void drm_dp_cec_irq(struct drm_dp_aux *aux);
2101void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
2102                                   struct drm_connector *connector);
2103void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux);
2104void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid);
2105void drm_dp_cec_unset_edid(struct drm_dp_aux *aux);
2106#else
2107static inline void drm_dp_cec_irq(struct drm_dp_aux *aux)
2108{
2109}
2110
2111static inline void
2112drm_dp_cec_register_connector(struct drm_dp_aux *aux,
2113                              struct drm_connector *connector)
2114{
2115}
2116
2117static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux)
2118{
2119}
2120
2121static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux,
2122                                       const struct edid *edid)
2123{
2124}
2125
2126static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
2127{
2128}
2129
2130#endif
2131
2132/**
2133 * struct drm_dp_phy_test_params - DP Phy Compliance parameters
2134 * @link_rate: Requested Link rate from DPCD 0x219
2135 * @num_lanes: Number of lanes requested by sing through DPCD 0x220
2136 * @phy_pattern: DP Phy test pattern from DPCD 0x248
2137 * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B
2138 * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259
2139 * @enhanced_frame_cap: flag for enhanced frame capability.
2140 */
2141struct drm_dp_phy_test_params {
2142        int link_rate;
2143        u8 num_lanes;
2144        u8 phy_pattern;
2145        u8 hbr2_reset[2];
2146        u8 custom80[10];
2147        bool enhanced_frame_cap;
2148};
2149
2150int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
2151                                struct drm_dp_phy_test_params *data);
2152int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
2153                                struct drm_dp_phy_test_params *data, u8 dp_rev);
2154int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2155                               const u8 port_cap[4]);
2156int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd);
2157bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux);
2158int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
2159                                u8 frl_mode);
2160int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
2161                                u8 frl_type);
2162int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux);
2163int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
2164
2165bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux);
2166int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask);
2167void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
2168                                           struct drm_connector *connector);
2169bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
2170int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
2171int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
2172int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
2173int drm_dp_pcon_pps_default(struct drm_dp_aux *aux);
2174int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]);
2175int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]);
2176bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2177                                               const u8 port_cap[4], u8 color_spc);
2178int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
2179
2180#endif /* _DRM_DP_HELPER_H_ */
2181