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18#undef DEBUG
19
20#include <linux/clk.h>
21#include <linux/console.h>
22#include <linux/ctype.h>
23#include <linux/cpufreq.h>
24#include <linux/delay.h>
25#include <linux/dmaengine.h>
26#include <linux/dma-mapping.h>
27#include <linux/err.h>
28#include <linux/errno.h>
29#include <linux/init.h>
30#include <linux/interrupt.h>
31#include <linux/ioport.h>
32#include <linux/ktime.h>
33#include <linux/major.h>
34#include <linux/module.h>
35#include <linux/mm.h>
36#include <linux/of.h>
37#include <linux/of_device.h>
38#include <linux/platform_device.h>
39#include <linux/pm_runtime.h>
40#include <linux/scatterlist.h>
41#include <linux/serial.h>
42#include <linux/serial_sci.h>
43#include <linux/sh_dma.h>
44#include <linux/slab.h>
45#include <linux/string.h>
46#include <linux/sysrq.h>
47#include <linux/timer.h>
48#include <linux/tty.h>
49#include <linux/tty_flip.h>
50
51#ifdef CONFIG_SUPERH
52#include <asm/sh_bios.h>
53#include <asm/platform_early.h>
54#endif
55
56#include "serial_mctrl_gpio.h"
57#include "sh-sci.h"
58
59
60enum {
61 SCIx_ERI_IRQ,
62 SCIx_RXI_IRQ,
63 SCIx_TXI_IRQ,
64 SCIx_BRI_IRQ,
65 SCIx_DRI_IRQ,
66 SCIx_TEI_IRQ,
67 SCIx_NR_IRQS,
68
69 SCIx_MUX_IRQ = SCIx_NR_IRQS,
70};
71
72#define SCIx_IRQ_IS_MUXED(port) \
73 ((port)->irqs[SCIx_ERI_IRQ] == \
74 (port)->irqs[SCIx_RXI_IRQ]) || \
75 ((port)->irqs[SCIx_ERI_IRQ] && \
76 ((port)->irqs[SCIx_RXI_IRQ] < 0))
77
78enum SCI_CLKS {
79 SCI_FCK,
80 SCI_SCK,
81 SCI_BRG_INT,
82 SCI_SCIF_CLK,
83 SCI_NUM_CLKS
84};
85
86
87#define SCI_SR(x) BIT((x) - 1)
88#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
89
90#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
91 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
92 SCI_SR(19) | SCI_SR(27)
93
94#define min_sr(_port) ffs((_port)->sampling_rate_mask)
95#define max_sr(_port) fls((_port)->sampling_rate_mask)
96
97
98#define for_each_sr(_sr, _port) \
99 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
100 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
101
102struct plat_sci_reg {
103 u8 offset, size;
104};
105
106struct sci_port_params {
107 const struct plat_sci_reg regs[SCIx_NR_REGS];
108 unsigned int fifosize;
109 unsigned int overrun_reg;
110 unsigned int overrun_mask;
111 unsigned int sampling_rate_mask;
112 unsigned int error_mask;
113 unsigned int error_clear;
114};
115
116struct sci_port {
117 struct uart_port port;
118
119
120 const struct sci_port_params *params;
121 const struct plat_sci_port *cfg;
122 unsigned int sampling_rate_mask;
123 resource_size_t reg_size;
124 struct mctrl_gpios *gpios;
125
126
127 struct clk *clks[SCI_NUM_CLKS];
128 unsigned long clk_rates[SCI_NUM_CLKS];
129
130 int irqs[SCIx_NR_IRQS];
131 char *irqstr[SCIx_NR_IRQS];
132
133 struct dma_chan *chan_tx;
134 struct dma_chan *chan_rx;
135
136#ifdef CONFIG_SERIAL_SH_SCI_DMA
137 struct dma_chan *chan_tx_saved;
138 struct dma_chan *chan_rx_saved;
139 dma_cookie_t cookie_tx;
140 dma_cookie_t cookie_rx[2];
141 dma_cookie_t active_rx;
142 dma_addr_t tx_dma_addr;
143 unsigned int tx_dma_len;
144 struct scatterlist sg_rx[2];
145 void *rx_buf[2];
146 size_t buf_len_rx;
147 struct work_struct work_tx;
148 struct hrtimer rx_timer;
149 unsigned int rx_timeout;
150#endif
151 unsigned int rx_frame;
152 int rx_trigger;
153 struct timer_list rx_fifo_timer;
154 int rx_fifo_timeout;
155 u16 hscif_tot;
156
157 bool has_rtscts;
158 bool autorts;
159};
160
161#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
162
163static struct sci_port sci_ports[SCI_NPORTS];
164static unsigned long sci_ports_in_use;
165static struct uart_driver sci_uart_driver;
166
167static inline struct sci_port *
168to_sci_port(struct uart_port *uart)
169{
170 return container_of(uart, struct sci_port, port);
171}
172
173static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
174
175
176
177
178 [SCIx_SCI_REGTYPE] = {
179 .regs = {
180 [SCSMR] = { 0x00, 8 },
181 [SCBRR] = { 0x01, 8 },
182 [SCSCR] = { 0x02, 8 },
183 [SCxTDR] = { 0x03, 8 },
184 [SCxSR] = { 0x04, 8 },
185 [SCxRDR] = { 0x05, 8 },
186 },
187 .fifosize = 1,
188 .overrun_reg = SCxSR,
189 .overrun_mask = SCI_ORER,
190 .sampling_rate_mask = SCI_SR(32),
191 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
192 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
193 },
194
195
196
197
198 [SCIx_IRDA_REGTYPE] = {
199 .regs = {
200 [SCSMR] = { 0x00, 8 },
201 [SCBRR] = { 0x02, 8 },
202 [SCSCR] = { 0x04, 8 },
203 [SCxTDR] = { 0x06, 8 },
204 [SCxSR] = { 0x08, 16 },
205 [SCxRDR] = { 0x0a, 8 },
206 [SCFCR] = { 0x0c, 8 },
207 [SCFDR] = { 0x0e, 16 },
208 },
209 .fifosize = 1,
210 .overrun_reg = SCxSR,
211 .overrun_mask = SCI_ORER,
212 .sampling_rate_mask = SCI_SR(32),
213 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
214 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
215 },
216
217
218
219
220 [SCIx_SCIFA_REGTYPE] = {
221 .regs = {
222 [SCSMR] = { 0x00, 16 },
223 [SCBRR] = { 0x04, 8 },
224 [SCSCR] = { 0x08, 16 },
225 [SCxTDR] = { 0x20, 8 },
226 [SCxSR] = { 0x14, 16 },
227 [SCxRDR] = { 0x24, 8 },
228 [SCFCR] = { 0x18, 16 },
229 [SCFDR] = { 0x1c, 16 },
230 [SCPCR] = { 0x30, 16 },
231 [SCPDR] = { 0x34, 16 },
232 },
233 .fifosize = 64,
234 .overrun_reg = SCxSR,
235 .overrun_mask = SCIFA_ORER,
236 .sampling_rate_mask = SCI_SR_SCIFAB,
237 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
238 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
239 },
240
241
242
243
244 [SCIx_SCIFB_REGTYPE] = {
245 .regs = {
246 [SCSMR] = { 0x00, 16 },
247 [SCBRR] = { 0x04, 8 },
248 [SCSCR] = { 0x08, 16 },
249 [SCxTDR] = { 0x40, 8 },
250 [SCxSR] = { 0x14, 16 },
251 [SCxRDR] = { 0x60, 8 },
252 [SCFCR] = { 0x18, 16 },
253 [SCTFDR] = { 0x38, 16 },
254 [SCRFDR] = { 0x3c, 16 },
255 [SCPCR] = { 0x30, 16 },
256 [SCPDR] = { 0x34, 16 },
257 },
258 .fifosize = 256,
259 .overrun_reg = SCxSR,
260 .overrun_mask = SCIFA_ORER,
261 .sampling_rate_mask = SCI_SR_SCIFAB,
262 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
263 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
264 },
265
266
267
268
269
270 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
271 .regs = {
272 [SCSMR] = { 0x00, 16 },
273 [SCBRR] = { 0x04, 8 },
274 [SCSCR] = { 0x08, 16 },
275 [SCxTDR] = { 0x0c, 8 },
276 [SCxSR] = { 0x10, 16 },
277 [SCxRDR] = { 0x14, 8 },
278 [SCFCR] = { 0x18, 16 },
279 [SCFDR] = { 0x1c, 16 },
280 [SCSPTR] = { 0x20, 16 },
281 [SCLSR] = { 0x24, 16 },
282 },
283 .fifosize = 16,
284 .overrun_reg = SCLSR,
285 .overrun_mask = SCLSR_ORER,
286 .sampling_rate_mask = SCI_SR(32),
287 .error_mask = SCIF_DEFAULT_ERROR_MASK,
288 .error_clear = SCIF_ERROR_CLEAR,
289 },
290
291
292
293
294
295
296
297 [SCIx_RZ_SCIFA_REGTYPE] = {
298 .regs = {
299 [SCSMR] = { 0x00, 16 },
300 [SCBRR] = { 0x02, 8 },
301 [SCSCR] = { 0x04, 16 },
302 [SCxTDR] = { 0x06, 8 },
303 [SCxSR] = { 0x08, 16 },
304 [SCxRDR] = { 0x0A, 8 },
305 [SCFCR] = { 0x0C, 16 },
306 [SCFDR] = { 0x0E, 16 },
307 [SCSPTR] = { 0x10, 16 },
308 [SCLSR] = { 0x12, 16 },
309 },
310 .fifosize = 16,
311 .overrun_reg = SCLSR,
312 .overrun_mask = SCLSR_ORER,
313 .sampling_rate_mask = SCI_SR(32),
314 .error_mask = SCIF_DEFAULT_ERROR_MASK,
315 .error_clear = SCIF_ERROR_CLEAR,
316 },
317
318
319
320
321 [SCIx_SH3_SCIF_REGTYPE] = {
322 .regs = {
323 [SCSMR] = { 0x00, 8 },
324 [SCBRR] = { 0x02, 8 },
325 [SCSCR] = { 0x04, 8 },
326 [SCxTDR] = { 0x06, 8 },
327 [SCxSR] = { 0x08, 16 },
328 [SCxRDR] = { 0x0a, 8 },
329 [SCFCR] = { 0x0c, 8 },
330 [SCFDR] = { 0x0e, 16 },
331 },
332 .fifosize = 16,
333 .overrun_reg = SCLSR,
334 .overrun_mask = SCLSR_ORER,
335 .sampling_rate_mask = SCI_SR(32),
336 .error_mask = SCIF_DEFAULT_ERROR_MASK,
337 .error_clear = SCIF_ERROR_CLEAR,
338 },
339
340
341
342
343 [SCIx_SH4_SCIF_REGTYPE] = {
344 .regs = {
345 [SCSMR] = { 0x00, 16 },
346 [SCBRR] = { 0x04, 8 },
347 [SCSCR] = { 0x08, 16 },
348 [SCxTDR] = { 0x0c, 8 },
349 [SCxSR] = { 0x10, 16 },
350 [SCxRDR] = { 0x14, 8 },
351 [SCFCR] = { 0x18, 16 },
352 [SCFDR] = { 0x1c, 16 },
353 [SCSPTR] = { 0x20, 16 },
354 [SCLSR] = { 0x24, 16 },
355 },
356 .fifosize = 16,
357 .overrun_reg = SCLSR,
358 .overrun_mask = SCLSR_ORER,
359 .sampling_rate_mask = SCI_SR(32),
360 .error_mask = SCIF_DEFAULT_ERROR_MASK,
361 .error_clear = SCIF_ERROR_CLEAR,
362 },
363
364
365
366
367
368 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
369 .regs = {
370 [SCSMR] = { 0x00, 16 },
371 [SCBRR] = { 0x04, 8 },
372 [SCSCR] = { 0x08, 16 },
373 [SCxTDR] = { 0x0c, 8 },
374 [SCxSR] = { 0x10, 16 },
375 [SCxRDR] = { 0x14, 8 },
376 [SCFCR] = { 0x18, 16 },
377 [SCFDR] = { 0x1c, 16 },
378 [SCSPTR] = { 0x20, 16 },
379 [SCLSR] = { 0x24, 16 },
380 [SCDL] = { 0x30, 16 },
381 [SCCKS] = { 0x34, 16 },
382 },
383 .fifosize = 16,
384 .overrun_reg = SCLSR,
385 .overrun_mask = SCLSR_ORER,
386 .sampling_rate_mask = SCI_SR(32),
387 .error_mask = SCIF_DEFAULT_ERROR_MASK,
388 .error_clear = SCIF_ERROR_CLEAR,
389 },
390
391
392
393
394 [SCIx_HSCIF_REGTYPE] = {
395 .regs = {
396 [SCSMR] = { 0x00, 16 },
397 [SCBRR] = { 0x04, 8 },
398 [SCSCR] = { 0x08, 16 },
399 [SCxTDR] = { 0x0c, 8 },
400 [SCxSR] = { 0x10, 16 },
401 [SCxRDR] = { 0x14, 8 },
402 [SCFCR] = { 0x18, 16 },
403 [SCFDR] = { 0x1c, 16 },
404 [SCSPTR] = { 0x20, 16 },
405 [SCLSR] = { 0x24, 16 },
406 [HSSRR] = { 0x40, 16 },
407 [SCDL] = { 0x30, 16 },
408 [SCCKS] = { 0x34, 16 },
409 [HSRTRGR] = { 0x54, 16 },
410 [HSTTRGR] = { 0x58, 16 },
411 },
412 .fifosize = 128,
413 .overrun_reg = SCLSR,
414 .overrun_mask = SCLSR_ORER,
415 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
416 .error_mask = SCIF_DEFAULT_ERROR_MASK,
417 .error_clear = SCIF_ERROR_CLEAR,
418 },
419
420
421
422
423
424 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
425 .regs = {
426 [SCSMR] = { 0x00, 16 },
427 [SCBRR] = { 0x04, 8 },
428 [SCSCR] = { 0x08, 16 },
429 [SCxTDR] = { 0x0c, 8 },
430 [SCxSR] = { 0x10, 16 },
431 [SCxRDR] = { 0x14, 8 },
432 [SCFCR] = { 0x18, 16 },
433 [SCFDR] = { 0x1c, 16 },
434 [SCLSR] = { 0x24, 16 },
435 },
436 .fifosize = 16,
437 .overrun_reg = SCLSR,
438 .overrun_mask = SCLSR_ORER,
439 .sampling_rate_mask = SCI_SR(32),
440 .error_mask = SCIF_DEFAULT_ERROR_MASK,
441 .error_clear = SCIF_ERROR_CLEAR,
442 },
443
444
445
446
447
448 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
449 .regs = {
450 [SCSMR] = { 0x00, 16 },
451 [SCBRR] = { 0x04, 8 },
452 [SCSCR] = { 0x08, 16 },
453 [SCxTDR] = { 0x0c, 8 },
454 [SCxSR] = { 0x10, 16 },
455 [SCxRDR] = { 0x14, 8 },
456 [SCFCR] = { 0x18, 16 },
457 [SCFDR] = { 0x1c, 16 },
458 [SCTFDR] = { 0x1c, 16 },
459 [SCRFDR] = { 0x20, 16 },
460 [SCSPTR] = { 0x24, 16 },
461 [SCLSR] = { 0x28, 16 },
462 },
463 .fifosize = 16,
464 .overrun_reg = SCLSR,
465 .overrun_mask = SCLSR_ORER,
466 .sampling_rate_mask = SCI_SR(32),
467 .error_mask = SCIF_DEFAULT_ERROR_MASK,
468 .error_clear = SCIF_ERROR_CLEAR,
469 },
470
471
472
473
474
475 [SCIx_SH7705_SCIF_REGTYPE] = {
476 .regs = {
477 [SCSMR] = { 0x00, 16 },
478 [SCBRR] = { 0x04, 8 },
479 [SCSCR] = { 0x08, 16 },
480 [SCxTDR] = { 0x20, 8 },
481 [SCxSR] = { 0x14, 16 },
482 [SCxRDR] = { 0x24, 8 },
483 [SCFCR] = { 0x18, 16 },
484 [SCFDR] = { 0x1c, 16 },
485 },
486 .fifosize = 64,
487 .overrun_reg = SCxSR,
488 .overrun_mask = SCIFA_ORER,
489 .sampling_rate_mask = SCI_SR(16),
490 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
491 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
492 },
493};
494
495#define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
496
497
498
499
500
501
502
503static unsigned int sci_serial_in(struct uart_port *p, int offset)
504{
505 const struct plat_sci_reg *reg = sci_getreg(p, offset);
506
507 if (reg->size == 8)
508 return ioread8(p->membase + (reg->offset << p->regshift));
509 else if (reg->size == 16)
510 return ioread16(p->membase + (reg->offset << p->regshift));
511 else
512 WARN(1, "Invalid register access\n");
513
514 return 0;
515}
516
517static void sci_serial_out(struct uart_port *p, int offset, int value)
518{
519 const struct plat_sci_reg *reg = sci_getreg(p, offset);
520
521 if (reg->size == 8)
522 iowrite8(value, p->membase + (reg->offset << p->regshift));
523 else if (reg->size == 16)
524 iowrite16(value, p->membase + (reg->offset << p->regshift));
525 else
526 WARN(1, "Invalid register access\n");
527}
528
529static void sci_port_enable(struct sci_port *sci_port)
530{
531 unsigned int i;
532
533 if (!sci_port->port.dev)
534 return;
535
536 pm_runtime_get_sync(sci_port->port.dev);
537
538 for (i = 0; i < SCI_NUM_CLKS; i++) {
539 clk_prepare_enable(sci_port->clks[i]);
540 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
541 }
542 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
543}
544
545static void sci_port_disable(struct sci_port *sci_port)
546{
547 unsigned int i;
548
549 if (!sci_port->port.dev)
550 return;
551
552 for (i = SCI_NUM_CLKS; i-- > 0; )
553 clk_disable_unprepare(sci_port->clks[i]);
554
555 pm_runtime_put_sync(sci_port->port.dev);
556}
557
558static inline unsigned long port_rx_irq_mask(struct uart_port *port)
559{
560
561
562
563
564
565
566
567 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
568}
569
570static void sci_start_tx(struct uart_port *port)
571{
572 struct sci_port *s = to_sci_port(port);
573 unsigned short ctrl;
574
575#ifdef CONFIG_SERIAL_SH_SCI_DMA
576 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
577 u16 new, scr = serial_port_in(port, SCSCR);
578 if (s->chan_tx)
579 new = scr | SCSCR_TDRQE;
580 else
581 new = scr & ~SCSCR_TDRQE;
582 if (new != scr)
583 serial_port_out(port, SCSCR, new);
584 }
585
586 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
587 dma_submit_error(s->cookie_tx)) {
588 s->cookie_tx = 0;
589 schedule_work(&s->work_tx);
590 }
591#endif
592
593 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
594
595 ctrl = serial_port_in(port, SCSCR);
596 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
597 }
598}
599
600static void sci_stop_tx(struct uart_port *port)
601{
602 unsigned short ctrl;
603
604
605 ctrl = serial_port_in(port, SCSCR);
606
607 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
608 ctrl &= ~SCSCR_TDRQE;
609
610 ctrl &= ~SCSCR_TIE;
611
612 serial_port_out(port, SCSCR, ctrl);
613
614#ifdef CONFIG_SERIAL_SH_SCI_DMA
615 if (to_sci_port(port)->chan_tx &&
616 !dma_submit_error(to_sci_port(port)->cookie_tx)) {
617 dmaengine_terminate_async(to_sci_port(port)->chan_tx);
618 to_sci_port(port)->cookie_tx = -EINVAL;
619 }
620#endif
621}
622
623static void sci_start_rx(struct uart_port *port)
624{
625 unsigned short ctrl;
626
627 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
628
629 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
630 ctrl &= ~SCSCR_RDRQE;
631
632 serial_port_out(port, SCSCR, ctrl);
633}
634
635static void sci_stop_rx(struct uart_port *port)
636{
637 unsigned short ctrl;
638
639 ctrl = serial_port_in(port, SCSCR);
640
641 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
642 ctrl &= ~SCSCR_RDRQE;
643
644 ctrl &= ~port_rx_irq_mask(port);
645
646 serial_port_out(port, SCSCR, ctrl);
647}
648
649static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
650{
651 if (port->type == PORT_SCI) {
652
653 serial_port_out(port, SCxSR, mask);
654 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
655
656
657 serial_port_out(port, SCxSR,
658 serial_port_in(port, SCxSR) & mask);
659 } else {
660
661 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
662 }
663}
664
665#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
666 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
667
668#ifdef CONFIG_CONSOLE_POLL
669static int sci_poll_get_char(struct uart_port *port)
670{
671 unsigned short status;
672 int c;
673
674 do {
675 status = serial_port_in(port, SCxSR);
676 if (status & SCxSR_ERRORS(port)) {
677 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
678 continue;
679 }
680 break;
681 } while (1);
682
683 if (!(status & SCxSR_RDxF(port)))
684 return NO_POLL_CHAR;
685
686 c = serial_port_in(port, SCxRDR);
687
688
689 serial_port_in(port, SCxSR);
690 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
691
692 return c;
693}
694#endif
695
696static void sci_poll_put_char(struct uart_port *port, unsigned char c)
697{
698 unsigned short status;
699
700 do {
701 status = serial_port_in(port, SCxSR);
702 } while (!(status & SCxSR_TDxE(port)));
703
704 serial_port_out(port, SCxTDR, c);
705 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
706}
707#endif
708
709
710static void sci_init_pins(struct uart_port *port, unsigned int cflag)
711{
712 struct sci_port *s = to_sci_port(port);
713
714
715
716
717 if (s->cfg->ops && s->cfg->ops->init_pins) {
718 s->cfg->ops->init_pins(port, cflag);
719 return;
720 }
721
722 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
723 u16 data = serial_port_in(port, SCPDR);
724 u16 ctrl = serial_port_in(port, SCPCR);
725
726
727 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
728 if (to_sci_port(port)->has_rtscts) {
729
730 if (!(port->mctrl & TIOCM_RTS)) {
731 ctrl |= SCPCR_RTSC;
732 data |= SCPDR_RTSD;
733 } else if (!s->autorts) {
734 ctrl |= SCPCR_RTSC;
735 data &= ~SCPDR_RTSD;
736 } else {
737
738 ctrl &= ~SCPCR_RTSC;
739 }
740
741 ctrl &= ~SCPCR_CTSC;
742 }
743 serial_port_out(port, SCPDR, data);
744 serial_port_out(port, SCPCR, ctrl);
745 } else if (sci_getreg(port, SCSPTR)->size) {
746 u16 status = serial_port_in(port, SCSPTR);
747
748
749 status |= SCSPTR_RTSIO;
750 if (!(port->mctrl & TIOCM_RTS))
751 status |= SCSPTR_RTSDT;
752 else if (!s->autorts)
753 status &= ~SCSPTR_RTSDT;
754
755 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
756 serial_port_out(port, SCSPTR, status);
757 }
758}
759
760static int sci_txfill(struct uart_port *port)
761{
762 struct sci_port *s = to_sci_port(port);
763 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
764 const struct plat_sci_reg *reg;
765
766 reg = sci_getreg(port, SCTFDR);
767 if (reg->size)
768 return serial_port_in(port, SCTFDR) & fifo_mask;
769
770 reg = sci_getreg(port, SCFDR);
771 if (reg->size)
772 return serial_port_in(port, SCFDR) >> 8;
773
774 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
775}
776
777static int sci_txroom(struct uart_port *port)
778{
779 return port->fifosize - sci_txfill(port);
780}
781
782static int sci_rxfill(struct uart_port *port)
783{
784 struct sci_port *s = to_sci_port(port);
785 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
786 const struct plat_sci_reg *reg;
787
788 reg = sci_getreg(port, SCRFDR);
789 if (reg->size)
790 return serial_port_in(port, SCRFDR) & fifo_mask;
791
792 reg = sci_getreg(port, SCFDR);
793 if (reg->size)
794 return serial_port_in(port, SCFDR) & fifo_mask;
795
796 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
797}
798
799
800
801
802
803static void sci_transmit_chars(struct uart_port *port)
804{
805 struct circ_buf *xmit = &port->state->xmit;
806 unsigned int stopped = uart_tx_stopped(port);
807 unsigned short status;
808 unsigned short ctrl;
809 int count;
810
811 status = serial_port_in(port, SCxSR);
812 if (!(status & SCxSR_TDxE(port))) {
813 ctrl = serial_port_in(port, SCSCR);
814 if (uart_circ_empty(xmit))
815 ctrl &= ~SCSCR_TIE;
816 else
817 ctrl |= SCSCR_TIE;
818 serial_port_out(port, SCSCR, ctrl);
819 return;
820 }
821
822 count = sci_txroom(port);
823
824 do {
825 unsigned char c;
826
827 if (port->x_char) {
828 c = port->x_char;
829 port->x_char = 0;
830 } else if (!uart_circ_empty(xmit) && !stopped) {
831 c = xmit->buf[xmit->tail];
832 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
833 } else {
834 break;
835 }
836
837 serial_port_out(port, SCxTDR, c);
838
839 port->icount.tx++;
840 } while (--count > 0);
841
842 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
843
844 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
845 uart_write_wakeup(port);
846 if (uart_circ_empty(xmit))
847 sci_stop_tx(port);
848
849}
850
851
852#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
853
854static void sci_receive_chars(struct uart_port *port)
855{
856 struct tty_port *tport = &port->state->port;
857 int i, count, copied = 0;
858 unsigned short status;
859 unsigned char flag;
860
861 status = serial_port_in(port, SCxSR);
862 if (!(status & SCxSR_RDxF(port)))
863 return;
864
865 while (1) {
866
867 count = tty_buffer_request_room(tport, sci_rxfill(port));
868
869
870 if (count == 0)
871 break;
872
873 if (port->type == PORT_SCI) {
874 char c = serial_port_in(port, SCxRDR);
875 if (uart_handle_sysrq_char(port, c))
876 count = 0;
877 else
878 tty_insert_flip_char(tport, c, TTY_NORMAL);
879 } else {
880 for (i = 0; i < count; i++) {
881 char c;
882
883 if (port->type == PORT_SCIF ||
884 port->type == PORT_HSCIF) {
885 status = serial_port_in(port, SCxSR);
886 c = serial_port_in(port, SCxRDR);
887 } else {
888 c = serial_port_in(port, SCxRDR);
889 status = serial_port_in(port, SCxSR);
890 }
891 if (uart_handle_sysrq_char(port, c)) {
892 count--; i--;
893 continue;
894 }
895
896
897 if (status & SCxSR_FER(port)) {
898 flag = TTY_FRAME;
899 port->icount.frame++;
900 dev_notice(port->dev, "frame error\n");
901 } else if (status & SCxSR_PER(port)) {
902 flag = TTY_PARITY;
903 port->icount.parity++;
904 dev_notice(port->dev, "parity error\n");
905 } else
906 flag = TTY_NORMAL;
907
908 tty_insert_flip_char(tport, c, flag);
909 }
910 }
911
912 serial_port_in(port, SCxSR);
913 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
914
915 copied += count;
916 port->icount.rx += count;
917 }
918
919 if (copied) {
920
921 tty_flip_buffer_push(tport);
922 } else {
923
924 serial_port_in(port, SCxRDR);
925 serial_port_in(port, SCxSR);
926 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
927 }
928}
929
930static int sci_handle_errors(struct uart_port *port)
931{
932 int copied = 0;
933 unsigned short status = serial_port_in(port, SCxSR);
934 struct tty_port *tport = &port->state->port;
935 struct sci_port *s = to_sci_port(port);
936
937
938 if (status & s->params->overrun_mask) {
939 port->icount.overrun++;
940
941
942 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
943 copied++;
944
945 dev_notice(port->dev, "overrun error\n");
946 }
947
948 if (status & SCxSR_FER(port)) {
949
950 port->icount.frame++;
951
952 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
953 copied++;
954
955 dev_notice(port->dev, "frame error\n");
956 }
957
958 if (status & SCxSR_PER(port)) {
959
960 port->icount.parity++;
961
962 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
963 copied++;
964
965 dev_notice(port->dev, "parity error\n");
966 }
967
968 if (copied)
969 tty_flip_buffer_push(tport);
970
971 return copied;
972}
973
974static int sci_handle_fifo_overrun(struct uart_port *port)
975{
976 struct tty_port *tport = &port->state->port;
977 struct sci_port *s = to_sci_port(port);
978 const struct plat_sci_reg *reg;
979 int copied = 0;
980 u16 status;
981
982 reg = sci_getreg(port, s->params->overrun_reg);
983 if (!reg->size)
984 return 0;
985
986 status = serial_port_in(port, s->params->overrun_reg);
987 if (status & s->params->overrun_mask) {
988 status &= ~s->params->overrun_mask;
989 serial_port_out(port, s->params->overrun_reg, status);
990
991 port->icount.overrun++;
992
993 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
994 tty_flip_buffer_push(tport);
995
996 dev_dbg(port->dev, "overrun error\n");
997 copied++;
998 }
999
1000 return copied;
1001}
1002
1003static int sci_handle_breaks(struct uart_port *port)
1004{
1005 int copied = 0;
1006 unsigned short status = serial_port_in(port, SCxSR);
1007 struct tty_port *tport = &port->state->port;
1008
1009 if (uart_handle_break(port))
1010 return 0;
1011
1012 if (status & SCxSR_BRK(port)) {
1013 port->icount.brk++;
1014
1015
1016 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1017 copied++;
1018
1019 dev_dbg(port->dev, "BREAK detected\n");
1020 }
1021
1022 if (copied)
1023 tty_flip_buffer_push(tport);
1024
1025 copied += sci_handle_fifo_overrun(port);
1026
1027 return copied;
1028}
1029
1030static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1031{
1032 unsigned int bits;
1033
1034 if (rx_trig >= port->fifosize)
1035 rx_trig = port->fifosize - 1;
1036 if (rx_trig < 1)
1037 rx_trig = 1;
1038
1039
1040 if (sci_getreg(port, HSRTRGR)->size) {
1041 serial_port_out(port, HSRTRGR, rx_trig);
1042 return rx_trig;
1043 }
1044
1045 switch (port->type) {
1046 case PORT_SCIF:
1047 if (rx_trig < 4) {
1048 bits = 0;
1049 rx_trig = 1;
1050 } else if (rx_trig < 8) {
1051 bits = SCFCR_RTRG0;
1052 rx_trig = 4;
1053 } else if (rx_trig < 14) {
1054 bits = SCFCR_RTRG1;
1055 rx_trig = 8;
1056 } else {
1057 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1058 rx_trig = 14;
1059 }
1060 break;
1061 case PORT_SCIFA:
1062 case PORT_SCIFB:
1063 if (rx_trig < 16) {
1064 bits = 0;
1065 rx_trig = 1;
1066 } else if (rx_trig < 32) {
1067 bits = SCFCR_RTRG0;
1068 rx_trig = 16;
1069 } else if (rx_trig < 48) {
1070 bits = SCFCR_RTRG1;
1071 rx_trig = 32;
1072 } else {
1073 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1074 rx_trig = 48;
1075 }
1076 break;
1077 default:
1078 WARN(1, "unknown FIFO configuration");
1079 return 1;
1080 }
1081
1082 serial_port_out(port, SCFCR,
1083 (serial_port_in(port, SCFCR) &
1084 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1085
1086 return rx_trig;
1087}
1088
1089static int scif_rtrg_enabled(struct uart_port *port)
1090{
1091 if (sci_getreg(port, HSRTRGR)->size)
1092 return serial_port_in(port, HSRTRGR) != 0;
1093 else
1094 return (serial_port_in(port, SCFCR) &
1095 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1096}
1097
1098static void rx_fifo_timer_fn(struct timer_list *t)
1099{
1100 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
1101 struct uart_port *port = &s->port;
1102
1103 dev_dbg(port->dev, "Rx timed out\n");
1104 scif_set_rtrg(port, 1);
1105}
1106
1107static ssize_t rx_fifo_trigger_show(struct device *dev,
1108 struct device_attribute *attr, char *buf)
1109{
1110 struct uart_port *port = dev_get_drvdata(dev);
1111 struct sci_port *sci = to_sci_port(port);
1112
1113 return sprintf(buf, "%d\n", sci->rx_trigger);
1114}
1115
1116static ssize_t rx_fifo_trigger_store(struct device *dev,
1117 struct device_attribute *attr,
1118 const char *buf, size_t count)
1119{
1120 struct uart_port *port = dev_get_drvdata(dev);
1121 struct sci_port *sci = to_sci_port(port);
1122 int ret;
1123 long r;
1124
1125 ret = kstrtol(buf, 0, &r);
1126 if (ret)
1127 return ret;
1128
1129 sci->rx_trigger = scif_set_rtrg(port, r);
1130 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1131 scif_set_rtrg(port, 1);
1132
1133 return count;
1134}
1135
1136static DEVICE_ATTR_RW(rx_fifo_trigger);
1137
1138static ssize_t rx_fifo_timeout_show(struct device *dev,
1139 struct device_attribute *attr,
1140 char *buf)
1141{
1142 struct uart_port *port = dev_get_drvdata(dev);
1143 struct sci_port *sci = to_sci_port(port);
1144 int v;
1145
1146 if (port->type == PORT_HSCIF)
1147 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1148 else
1149 v = sci->rx_fifo_timeout;
1150
1151 return sprintf(buf, "%d\n", v);
1152}
1153
1154static ssize_t rx_fifo_timeout_store(struct device *dev,
1155 struct device_attribute *attr,
1156 const char *buf,
1157 size_t count)
1158{
1159 struct uart_port *port = dev_get_drvdata(dev);
1160 struct sci_port *sci = to_sci_port(port);
1161 int ret;
1162 long r;
1163
1164 ret = kstrtol(buf, 0, &r);
1165 if (ret)
1166 return ret;
1167
1168 if (port->type == PORT_HSCIF) {
1169 if (r < 0 || r > 3)
1170 return -EINVAL;
1171 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1172 } else {
1173 sci->rx_fifo_timeout = r;
1174 scif_set_rtrg(port, 1);
1175 if (r > 0)
1176 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1177 }
1178
1179 return count;
1180}
1181
1182static DEVICE_ATTR_RW(rx_fifo_timeout);
1183
1184
1185#ifdef CONFIG_SERIAL_SH_SCI_DMA
1186static void sci_dma_tx_complete(void *arg)
1187{
1188 struct sci_port *s = arg;
1189 struct uart_port *port = &s->port;
1190 struct circ_buf *xmit = &port->state->xmit;
1191 unsigned long flags;
1192
1193 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1194
1195 spin_lock_irqsave(&port->lock, flags);
1196
1197 xmit->tail += s->tx_dma_len;
1198 xmit->tail &= UART_XMIT_SIZE - 1;
1199
1200 port->icount.tx += s->tx_dma_len;
1201
1202 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1203 uart_write_wakeup(port);
1204
1205 if (!uart_circ_empty(xmit)) {
1206 s->cookie_tx = 0;
1207 schedule_work(&s->work_tx);
1208 } else {
1209 s->cookie_tx = -EINVAL;
1210 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1211 u16 ctrl = serial_port_in(port, SCSCR);
1212 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1213 }
1214 }
1215
1216 spin_unlock_irqrestore(&port->lock, flags);
1217}
1218
1219
1220static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1221{
1222 struct uart_port *port = &s->port;
1223 struct tty_port *tport = &port->state->port;
1224 int copied;
1225
1226 copied = tty_insert_flip_string(tport, buf, count);
1227 if (copied < count)
1228 port->icount.buf_overrun++;
1229
1230 port->icount.rx += copied;
1231
1232 return copied;
1233}
1234
1235static int sci_dma_rx_find_active(struct sci_port *s)
1236{
1237 unsigned int i;
1238
1239 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1240 if (s->active_rx == s->cookie_rx[i])
1241 return i;
1242
1243 return -1;
1244}
1245
1246static void sci_dma_rx_chan_invalidate(struct sci_port *s)
1247{
1248 unsigned int i;
1249
1250 s->chan_rx = NULL;
1251 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1252 s->cookie_rx[i] = -EINVAL;
1253 s->active_rx = 0;
1254}
1255
1256static void sci_dma_rx_release(struct sci_port *s)
1257{
1258 struct dma_chan *chan = s->chan_rx_saved;
1259
1260 s->chan_rx_saved = NULL;
1261 sci_dma_rx_chan_invalidate(s);
1262 dmaengine_terminate_sync(chan);
1263 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1264 sg_dma_address(&s->sg_rx[0]));
1265 dma_release_channel(chan);
1266}
1267
1268static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1269{
1270 long sec = usec / 1000000;
1271 long nsec = (usec % 1000000) * 1000;
1272 ktime_t t = ktime_set(sec, nsec);
1273
1274 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1275}
1276
1277static void sci_dma_rx_reenable_irq(struct sci_port *s)
1278{
1279 struct uart_port *port = &s->port;
1280 u16 scr;
1281
1282
1283 scr = serial_port_in(port, SCSCR);
1284 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1285 scr &= ~SCSCR_RDRQE;
1286 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1287 }
1288 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1289}
1290
1291static void sci_dma_rx_complete(void *arg)
1292{
1293 struct sci_port *s = arg;
1294 struct dma_chan *chan = s->chan_rx;
1295 struct uart_port *port = &s->port;
1296 struct dma_async_tx_descriptor *desc;
1297 unsigned long flags;
1298 int active, count = 0;
1299
1300 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1301 s->active_rx);
1302
1303 spin_lock_irqsave(&port->lock, flags);
1304
1305 active = sci_dma_rx_find_active(s);
1306 if (active >= 0)
1307 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1308
1309 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1310
1311 if (count)
1312 tty_flip_buffer_push(&port->state->port);
1313
1314 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1315 DMA_DEV_TO_MEM,
1316 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1317 if (!desc)
1318 goto fail;
1319
1320 desc->callback = sci_dma_rx_complete;
1321 desc->callback_param = s;
1322 s->cookie_rx[active] = dmaengine_submit(desc);
1323 if (dma_submit_error(s->cookie_rx[active]))
1324 goto fail;
1325
1326 s->active_rx = s->cookie_rx[!active];
1327
1328 dma_async_issue_pending(chan);
1329
1330 spin_unlock_irqrestore(&port->lock, flags);
1331 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1332 __func__, s->cookie_rx[active], active, s->active_rx);
1333 return;
1334
1335fail:
1336 spin_unlock_irqrestore(&port->lock, flags);
1337 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1338
1339 spin_lock_irqsave(&port->lock, flags);
1340 dmaengine_terminate_async(chan);
1341 sci_dma_rx_chan_invalidate(s);
1342 sci_dma_rx_reenable_irq(s);
1343 spin_unlock_irqrestore(&port->lock, flags);
1344}
1345
1346static void sci_dma_tx_release(struct sci_port *s)
1347{
1348 struct dma_chan *chan = s->chan_tx_saved;
1349
1350 cancel_work_sync(&s->work_tx);
1351 s->chan_tx_saved = s->chan_tx = NULL;
1352 s->cookie_tx = -EINVAL;
1353 dmaengine_terminate_sync(chan);
1354 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1355 DMA_TO_DEVICE);
1356 dma_release_channel(chan);
1357}
1358
1359static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held)
1360{
1361 struct dma_chan *chan = s->chan_rx;
1362 struct uart_port *port = &s->port;
1363 unsigned long flags;
1364 int i;
1365
1366 for (i = 0; i < 2; i++) {
1367 struct scatterlist *sg = &s->sg_rx[i];
1368 struct dma_async_tx_descriptor *desc;
1369
1370 desc = dmaengine_prep_slave_sg(chan,
1371 sg, 1, DMA_DEV_TO_MEM,
1372 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1373 if (!desc)
1374 goto fail;
1375
1376 desc->callback = sci_dma_rx_complete;
1377 desc->callback_param = s;
1378 s->cookie_rx[i] = dmaengine_submit(desc);
1379 if (dma_submit_error(s->cookie_rx[i]))
1380 goto fail;
1381
1382 }
1383
1384 s->active_rx = s->cookie_rx[0];
1385
1386 dma_async_issue_pending(chan);
1387 return 0;
1388
1389fail:
1390
1391 if (!port_lock_held)
1392 spin_lock_irqsave(&port->lock, flags);
1393 if (i)
1394 dmaengine_terminate_async(chan);
1395 sci_dma_rx_chan_invalidate(s);
1396 sci_start_rx(port);
1397 if (!port_lock_held)
1398 spin_unlock_irqrestore(&port->lock, flags);
1399 return -EAGAIN;
1400}
1401
1402static void sci_dma_tx_work_fn(struct work_struct *work)
1403{
1404 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1405 struct dma_async_tx_descriptor *desc;
1406 struct dma_chan *chan = s->chan_tx;
1407 struct uart_port *port = &s->port;
1408 struct circ_buf *xmit = &port->state->xmit;
1409 unsigned long flags;
1410 dma_addr_t buf;
1411 int head, tail;
1412
1413
1414
1415
1416
1417
1418
1419
1420 spin_lock_irq(&port->lock);
1421 head = xmit->head;
1422 tail = xmit->tail;
1423 buf = s->tx_dma_addr + (tail & (UART_XMIT_SIZE - 1));
1424 s->tx_dma_len = min_t(unsigned int,
1425 CIRC_CNT(head, tail, UART_XMIT_SIZE),
1426 CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE));
1427 if (!s->tx_dma_len) {
1428
1429 spin_unlock_irq(&port->lock);
1430 return;
1431 }
1432
1433 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1434 DMA_MEM_TO_DEV,
1435 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1436 if (!desc) {
1437 spin_unlock_irq(&port->lock);
1438 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1439 goto switch_to_pio;
1440 }
1441
1442 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1443 DMA_TO_DEVICE);
1444
1445 desc->callback = sci_dma_tx_complete;
1446 desc->callback_param = s;
1447 s->cookie_tx = dmaengine_submit(desc);
1448 if (dma_submit_error(s->cookie_tx)) {
1449 spin_unlock_irq(&port->lock);
1450 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1451 goto switch_to_pio;
1452 }
1453
1454 spin_unlock_irq(&port->lock);
1455 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1456 __func__, xmit->buf, tail, head, s->cookie_tx);
1457
1458 dma_async_issue_pending(chan);
1459 return;
1460
1461switch_to_pio:
1462 spin_lock_irqsave(&port->lock, flags);
1463 s->chan_tx = NULL;
1464 sci_start_tx(port);
1465 spin_unlock_irqrestore(&port->lock, flags);
1466 return;
1467}
1468
1469static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t)
1470{
1471 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1472 struct dma_chan *chan = s->chan_rx;
1473 struct uart_port *port = &s->port;
1474 struct dma_tx_state state;
1475 enum dma_status status;
1476 unsigned long flags;
1477 unsigned int read;
1478 int active, count;
1479
1480 dev_dbg(port->dev, "DMA Rx timed out\n");
1481
1482 spin_lock_irqsave(&port->lock, flags);
1483
1484 active = sci_dma_rx_find_active(s);
1485 if (active < 0) {
1486 spin_unlock_irqrestore(&port->lock, flags);
1487 return HRTIMER_NORESTART;
1488 }
1489
1490 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1491 if (status == DMA_COMPLETE) {
1492 spin_unlock_irqrestore(&port->lock, flags);
1493 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1494 s->active_rx, active);
1495
1496
1497 return HRTIMER_NORESTART;
1498 }
1499
1500 dmaengine_pause(chan);
1501
1502
1503
1504
1505
1506
1507
1508 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1509 if (status == DMA_COMPLETE) {
1510 spin_unlock_irqrestore(&port->lock, flags);
1511 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1512 return HRTIMER_NORESTART;
1513 }
1514
1515
1516 dmaengine_terminate_async(s->chan_rx);
1517 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1518
1519 if (read) {
1520 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1521 if (count)
1522 tty_flip_buffer_push(&port->state->port);
1523 }
1524
1525 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1526 sci_dma_rx_submit(s, true);
1527
1528 sci_dma_rx_reenable_irq(s);
1529
1530 spin_unlock_irqrestore(&port->lock, flags);
1531
1532 return HRTIMER_NORESTART;
1533}
1534
1535static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1536 enum dma_transfer_direction dir)
1537{
1538 struct dma_chan *chan;
1539 struct dma_slave_config cfg;
1540 int ret;
1541
1542 chan = dma_request_slave_channel(port->dev,
1543 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1544 if (!chan) {
1545 dev_dbg(port->dev, "dma_request_slave_channel failed\n");
1546 return NULL;
1547 }
1548
1549 memset(&cfg, 0, sizeof(cfg));
1550 cfg.direction = dir;
1551 if (dir == DMA_MEM_TO_DEV) {
1552 cfg.dst_addr = port->mapbase +
1553 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1554 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1555 } else {
1556 cfg.src_addr = port->mapbase +
1557 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1558 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1559 }
1560
1561 ret = dmaengine_slave_config(chan, &cfg);
1562 if (ret) {
1563 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1564 dma_release_channel(chan);
1565 return NULL;
1566 }
1567
1568 return chan;
1569}
1570
1571static void sci_request_dma(struct uart_port *port)
1572{
1573 struct sci_port *s = to_sci_port(port);
1574 struct dma_chan *chan;
1575
1576 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1577
1578
1579
1580
1581
1582 if (uart_console(port))
1583 return;
1584
1585 if (!port->dev->of_node)
1586 return;
1587
1588 s->cookie_tx = -EINVAL;
1589
1590
1591
1592
1593
1594 if (!of_find_property(port->dev->of_node, "dmas", NULL))
1595 return;
1596
1597 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1598 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1599 if (chan) {
1600
1601 s->tx_dma_addr = dma_map_single(chan->device->dev,
1602 port->state->xmit.buf,
1603 UART_XMIT_SIZE,
1604 DMA_TO_DEVICE);
1605 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1606 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1607 dma_release_channel(chan);
1608 } else {
1609 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1610 __func__, UART_XMIT_SIZE,
1611 port->state->xmit.buf, &s->tx_dma_addr);
1612
1613 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn);
1614 s->chan_tx_saved = s->chan_tx = chan;
1615 }
1616 }
1617
1618 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1619 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1620 if (chan) {
1621 unsigned int i;
1622 dma_addr_t dma;
1623 void *buf;
1624
1625 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1626 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1627 &dma, GFP_KERNEL);
1628 if (!buf) {
1629 dev_warn(port->dev,
1630 "Failed to allocate Rx dma buffer, using PIO\n");
1631 dma_release_channel(chan);
1632 return;
1633 }
1634
1635 for (i = 0; i < 2; i++) {
1636 struct scatterlist *sg = &s->sg_rx[i];
1637
1638 sg_init_table(sg, 1);
1639 s->rx_buf[i] = buf;
1640 sg_dma_address(sg) = dma;
1641 sg_dma_len(sg) = s->buf_len_rx;
1642
1643 buf += s->buf_len_rx;
1644 dma += s->buf_len_rx;
1645 }
1646
1647 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1648 s->rx_timer.function = sci_dma_rx_timer_fn;
1649
1650 s->chan_rx_saved = s->chan_rx = chan;
1651
1652 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1653 sci_dma_rx_submit(s, false);
1654 }
1655}
1656
1657static void sci_free_dma(struct uart_port *port)
1658{
1659 struct sci_port *s = to_sci_port(port);
1660
1661 if (s->chan_tx_saved)
1662 sci_dma_tx_release(s);
1663 if (s->chan_rx_saved)
1664 sci_dma_rx_release(s);
1665}
1666
1667static void sci_flush_buffer(struct uart_port *port)
1668{
1669 struct sci_port *s = to_sci_port(port);
1670
1671
1672
1673
1674
1675
1676 s->tx_dma_len = 0;
1677 if (s->chan_tx) {
1678 dmaengine_terminate_async(s->chan_tx);
1679 s->cookie_tx = -EINVAL;
1680 }
1681}
1682#else
1683static inline void sci_request_dma(struct uart_port *port)
1684{
1685}
1686
1687static inline void sci_free_dma(struct uart_port *port)
1688{
1689}
1690
1691#define sci_flush_buffer NULL
1692#endif
1693
1694static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1695{
1696 struct uart_port *port = ptr;
1697 struct sci_port *s = to_sci_port(port);
1698
1699#ifdef CONFIG_SERIAL_SH_SCI_DMA
1700 if (s->chan_rx) {
1701 u16 scr = serial_port_in(port, SCSCR);
1702 u16 ssr = serial_port_in(port, SCxSR);
1703
1704
1705 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1706 disable_irq_nosync(irq);
1707 scr |= SCSCR_RDRQE;
1708 } else {
1709 if (sci_dma_rx_submit(s, false) < 0)
1710 goto handle_pio;
1711
1712 scr &= ~SCSCR_RIE;
1713 }
1714 serial_port_out(port, SCSCR, scr);
1715
1716 serial_port_out(port, SCxSR,
1717 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1718 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1719 jiffies, s->rx_timeout);
1720 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1721
1722 return IRQ_HANDLED;
1723 }
1724
1725handle_pio:
1726#endif
1727
1728 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1729 if (!scif_rtrg_enabled(port))
1730 scif_set_rtrg(port, s->rx_trigger);
1731
1732 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1733 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1734 }
1735
1736
1737
1738
1739
1740 sci_receive_chars(port);
1741
1742 return IRQ_HANDLED;
1743}
1744
1745static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1746{
1747 struct uart_port *port = ptr;
1748 unsigned long flags;
1749
1750 spin_lock_irqsave(&port->lock, flags);
1751 sci_transmit_chars(port);
1752 spin_unlock_irqrestore(&port->lock, flags);
1753
1754 return IRQ_HANDLED;
1755}
1756
1757static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1758{
1759 struct uart_port *port = ptr;
1760
1761
1762 sci_handle_breaks(port);
1763
1764
1765 serial_port_in(port, SCxRDR);
1766
1767 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1768
1769 return IRQ_HANDLED;
1770}
1771
1772static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1773{
1774 struct uart_port *port = ptr;
1775 struct sci_port *s = to_sci_port(port);
1776
1777 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
1778
1779 unsigned short ssr_status = serial_port_in(port, SCxSR);
1780
1781
1782 if (ssr_status & SCxSR_BRK(port))
1783 sci_br_interrupt(irq, ptr);
1784
1785
1786 if (!(ssr_status & SCxSR_ERRORS(port)))
1787 return IRQ_HANDLED;
1788 }
1789
1790
1791 if (port->type == PORT_SCI) {
1792 if (sci_handle_errors(port)) {
1793
1794 serial_port_in(port, SCxSR);
1795 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1796 }
1797 } else {
1798 sci_handle_fifo_overrun(port);
1799 if (!s->chan_rx)
1800 sci_receive_chars(port);
1801 }
1802
1803 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1804
1805
1806 if (!s->chan_tx)
1807 sci_tx_interrupt(irq, ptr);
1808
1809 return IRQ_HANDLED;
1810}
1811
1812static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1813{
1814 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1815 struct uart_port *port = ptr;
1816 struct sci_port *s = to_sci_port(port);
1817 irqreturn_t ret = IRQ_NONE;
1818
1819 ssr_status = serial_port_in(port, SCxSR);
1820 scr_status = serial_port_in(port, SCSCR);
1821 if (s->params->overrun_reg == SCxSR)
1822 orer_status = ssr_status;
1823 else if (sci_getreg(port, s->params->overrun_reg)->size)
1824 orer_status = serial_port_in(port, s->params->overrun_reg);
1825
1826 err_enabled = scr_status & port_rx_irq_mask(port);
1827
1828
1829 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1830 !s->chan_tx)
1831 ret = sci_tx_interrupt(irq, ptr);
1832
1833
1834
1835
1836
1837 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1838 (scr_status & SCSCR_RIE))
1839 ret = sci_rx_interrupt(irq, ptr);
1840
1841
1842 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1843 ret = sci_er_interrupt(irq, ptr);
1844
1845
1846 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] &&
1847 (ssr_status & SCxSR_BRK(port)) && err_enabled)
1848 ret = sci_br_interrupt(irq, ptr);
1849
1850
1851 if (orer_status & s->params->overrun_mask) {
1852 sci_handle_fifo_overrun(port);
1853 ret = IRQ_HANDLED;
1854 }
1855
1856 return ret;
1857}
1858
1859static const struct sci_irq_desc {
1860 const char *desc;
1861 irq_handler_t handler;
1862} sci_irq_desc[] = {
1863
1864
1865
1866 [SCIx_ERI_IRQ] = {
1867 .desc = "rx err",
1868 .handler = sci_er_interrupt,
1869 },
1870
1871 [SCIx_RXI_IRQ] = {
1872 .desc = "rx full",
1873 .handler = sci_rx_interrupt,
1874 },
1875
1876 [SCIx_TXI_IRQ] = {
1877 .desc = "tx empty",
1878 .handler = sci_tx_interrupt,
1879 },
1880
1881 [SCIx_BRI_IRQ] = {
1882 .desc = "break",
1883 .handler = sci_br_interrupt,
1884 },
1885
1886 [SCIx_DRI_IRQ] = {
1887 .desc = "rx ready",
1888 .handler = sci_rx_interrupt,
1889 },
1890
1891 [SCIx_TEI_IRQ] = {
1892 .desc = "tx end",
1893 .handler = sci_tx_interrupt,
1894 },
1895
1896
1897
1898
1899 [SCIx_MUX_IRQ] = {
1900 .desc = "mux",
1901 .handler = sci_mpxed_interrupt,
1902 },
1903};
1904
1905static int sci_request_irq(struct sci_port *port)
1906{
1907 struct uart_port *up = &port->port;
1908 int i, j, w, ret = 0;
1909
1910 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1911 const struct sci_irq_desc *desc;
1912 int irq;
1913
1914
1915 for (w = 0; w < i; w++)
1916 if (port->irqs[w] == port->irqs[i])
1917 w = i + 1;
1918 if (w > i)
1919 continue;
1920
1921 if (SCIx_IRQ_IS_MUXED(port)) {
1922 i = SCIx_MUX_IRQ;
1923 irq = up->irq;
1924 } else {
1925 irq = port->irqs[i];
1926
1927
1928
1929
1930
1931 if (unlikely(irq < 0))
1932 continue;
1933 }
1934
1935 desc = sci_irq_desc + i;
1936 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1937 dev_name(up->dev), desc->desc);
1938 if (!port->irqstr[j]) {
1939 ret = -ENOMEM;
1940 goto out_nomem;
1941 }
1942
1943 ret = request_irq(irq, desc->handler, up->irqflags,
1944 port->irqstr[j], port);
1945 if (unlikely(ret)) {
1946 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1947 goto out_noirq;
1948 }
1949 }
1950
1951 return 0;
1952
1953out_noirq:
1954 while (--i >= 0)
1955 free_irq(port->irqs[i], port);
1956
1957out_nomem:
1958 while (--j >= 0)
1959 kfree(port->irqstr[j]);
1960
1961 return ret;
1962}
1963
1964static void sci_free_irq(struct sci_port *port)
1965{
1966 int i, j;
1967
1968
1969
1970
1971
1972 for (i = 0; i < SCIx_NR_IRQS; i++) {
1973 int irq = port->irqs[i];
1974
1975
1976
1977
1978
1979 if (unlikely(irq < 0))
1980 continue;
1981
1982
1983 for (j = 0; j < i; j++)
1984 if (port->irqs[j] == irq)
1985 j = i + 1;
1986 if (j > i)
1987 continue;
1988
1989 free_irq(port->irqs[i], port);
1990 kfree(port->irqstr[i]);
1991
1992 if (SCIx_IRQ_IS_MUXED(port)) {
1993
1994 return;
1995 }
1996 }
1997}
1998
1999static unsigned int sci_tx_empty(struct uart_port *port)
2000{
2001 unsigned short status = serial_port_in(port, SCxSR);
2002 unsigned short in_tx_fifo = sci_txfill(port);
2003
2004 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
2005}
2006
2007static void sci_set_rts(struct uart_port *port, bool state)
2008{
2009 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2010 u16 data = serial_port_in(port, SCPDR);
2011
2012
2013 if (state)
2014 data &= ~SCPDR_RTSD;
2015 else
2016 data |= SCPDR_RTSD;
2017 serial_port_out(port, SCPDR, data);
2018
2019
2020 serial_port_out(port, SCPCR,
2021 serial_port_in(port, SCPCR) | SCPCR_RTSC);
2022 } else if (sci_getreg(port, SCSPTR)->size) {
2023 u16 ctrl = serial_port_in(port, SCSPTR);
2024
2025
2026 if (state)
2027 ctrl &= ~SCSPTR_RTSDT;
2028 else
2029 ctrl |= SCSPTR_RTSDT;
2030 serial_port_out(port, SCSPTR, ctrl);
2031 }
2032}
2033
2034static bool sci_get_cts(struct uart_port *port)
2035{
2036 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2037
2038 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
2039 } else if (sci_getreg(port, SCSPTR)->size) {
2040
2041 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
2042 }
2043
2044 return true;
2045}
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2060{
2061 struct sci_port *s = to_sci_port(port);
2062
2063 if (mctrl & TIOCM_LOOP) {
2064 const struct plat_sci_reg *reg;
2065
2066
2067
2068
2069 reg = sci_getreg(port, SCFCR);
2070 if (reg->size)
2071 serial_port_out(port, SCFCR,
2072 serial_port_in(port, SCFCR) |
2073 SCFCR_LOOP);
2074 }
2075
2076 mctrl_gpio_set(s->gpios, mctrl);
2077
2078 if (!s->has_rtscts)
2079 return;
2080
2081 if (!(mctrl & TIOCM_RTS)) {
2082
2083 serial_port_out(port, SCFCR,
2084 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
2085
2086
2087 sci_set_rts(port, 0);
2088 } else if (s->autorts) {
2089 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2090
2091 serial_port_out(port, SCPCR,
2092 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
2093 }
2094
2095
2096 serial_port_out(port, SCFCR,
2097 serial_port_in(port, SCFCR) | SCFCR_MCE);
2098 } else {
2099
2100 sci_set_rts(port, 1);
2101 }
2102}
2103
2104static unsigned int sci_get_mctrl(struct uart_port *port)
2105{
2106 struct sci_port *s = to_sci_port(port);
2107 struct mctrl_gpios *gpios = s->gpios;
2108 unsigned int mctrl = 0;
2109
2110 mctrl_gpio_get(gpios, &mctrl);
2111
2112
2113
2114
2115
2116 if (s->autorts) {
2117 if (sci_get_cts(port))
2118 mctrl |= TIOCM_CTS;
2119 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) {
2120 mctrl |= TIOCM_CTS;
2121 }
2122 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
2123 mctrl |= TIOCM_DSR;
2124 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
2125 mctrl |= TIOCM_CAR;
2126
2127 return mctrl;
2128}
2129
2130static void sci_enable_ms(struct uart_port *port)
2131{
2132 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2133}
2134
2135static void sci_break_ctl(struct uart_port *port, int break_state)
2136{
2137 unsigned short scscr, scsptr;
2138 unsigned long flags;
2139
2140
2141 if (!sci_getreg(port, SCSPTR)->size) {
2142
2143
2144
2145
2146 return;
2147 }
2148
2149 spin_lock_irqsave(&port->lock, flags);
2150 scsptr = serial_port_in(port, SCSPTR);
2151 scscr = serial_port_in(port, SCSCR);
2152
2153 if (break_state == -1) {
2154 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2155 scscr &= ~SCSCR_TE;
2156 } else {
2157 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2158 scscr |= SCSCR_TE;
2159 }
2160
2161 serial_port_out(port, SCSPTR, scsptr);
2162 serial_port_out(port, SCSCR, scscr);
2163 spin_unlock_irqrestore(&port->lock, flags);
2164}
2165
2166static int sci_startup(struct uart_port *port)
2167{
2168 struct sci_port *s = to_sci_port(port);
2169 int ret;
2170
2171 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2172
2173 sci_request_dma(port);
2174
2175 ret = sci_request_irq(s);
2176 if (unlikely(ret < 0)) {
2177 sci_free_dma(port);
2178 return ret;
2179 }
2180
2181 return 0;
2182}
2183
2184static void sci_shutdown(struct uart_port *port)
2185{
2186 struct sci_port *s = to_sci_port(port);
2187 unsigned long flags;
2188 u16 scr;
2189
2190 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2191
2192 s->autorts = false;
2193 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2194
2195 spin_lock_irqsave(&port->lock, flags);
2196 sci_stop_rx(port);
2197 sci_stop_tx(port);
2198
2199
2200
2201
2202 scr = serial_port_in(port, SCSCR);
2203 serial_port_out(port, SCSCR, scr &
2204 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2205 spin_unlock_irqrestore(&port->lock, flags);
2206
2207#ifdef CONFIG_SERIAL_SH_SCI_DMA
2208 if (s->chan_rx_saved) {
2209 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2210 port->line);
2211 hrtimer_cancel(&s->rx_timer);
2212 }
2213#endif
2214
2215 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2216 del_timer_sync(&s->rx_fifo_timer);
2217 sci_free_irq(s);
2218 sci_free_dma(port);
2219}
2220
2221static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2222 unsigned int *srr)
2223{
2224 unsigned long freq = s->clk_rates[SCI_SCK];
2225 int err, min_err = INT_MAX;
2226 unsigned int sr;
2227
2228 if (s->port.type != PORT_HSCIF)
2229 freq *= 2;
2230
2231 for_each_sr(sr, s) {
2232 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2233 if (abs(err) >= abs(min_err))
2234 continue;
2235
2236 min_err = err;
2237 *srr = sr - 1;
2238
2239 if (!err)
2240 break;
2241 }
2242
2243 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2244 *srr + 1);
2245 return min_err;
2246}
2247
2248static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2249 unsigned long freq, unsigned int *dlr,
2250 unsigned int *srr)
2251{
2252 int err, min_err = INT_MAX;
2253 unsigned int sr, dl;
2254
2255 if (s->port.type != PORT_HSCIF)
2256 freq *= 2;
2257
2258 for_each_sr(sr, s) {
2259 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2260 dl = clamp(dl, 1U, 65535U);
2261
2262 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2263 if (abs(err) >= abs(min_err))
2264 continue;
2265
2266 min_err = err;
2267 *dlr = dl;
2268 *srr = sr - 1;
2269
2270 if (!err)
2271 break;
2272 }
2273
2274 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2275 min_err, *dlr, *srr + 1);
2276 return min_err;
2277}
2278
2279
2280static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2281 unsigned int *brr, unsigned int *srr,
2282 unsigned int *cks)
2283{
2284 unsigned long freq = s->clk_rates[SCI_FCK];
2285 unsigned int sr, br, prediv, scrate, c;
2286 int err, min_err = INT_MAX;
2287
2288 if (s->port.type != PORT_HSCIF)
2289 freq *= 2;
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306 for_each_sr(sr, s) {
2307 for (c = 0; c <= 3; c++) {
2308
2309 prediv = sr * (1 << (2 * c + 1));
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320 if (bps > UINT_MAX / prediv)
2321 break;
2322
2323 scrate = prediv * bps;
2324 br = DIV_ROUND_CLOSEST(freq, scrate);
2325 br = clamp(br, 1U, 256U);
2326
2327 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2328 if (abs(err) >= abs(min_err))
2329 continue;
2330
2331 min_err = err;
2332 *brr = br - 1;
2333 *srr = sr - 1;
2334 *cks = c;
2335
2336 if (!err)
2337 goto found;
2338 }
2339 }
2340
2341found:
2342 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2343 min_err, *brr, *srr + 1, *cks);
2344 return min_err;
2345}
2346
2347static void sci_reset(struct uart_port *port)
2348{
2349 const struct plat_sci_reg *reg;
2350 unsigned int status;
2351 struct sci_port *s = to_sci_port(port);
2352
2353 serial_port_out(port, SCSCR, s->hscif_tot);
2354
2355 reg = sci_getreg(port, SCFCR);
2356 if (reg->size)
2357 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2358
2359 sci_clear_SCxSR(port,
2360 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2361 SCxSR_BREAK_CLEAR(port));
2362 if (sci_getreg(port, SCLSR)->size) {
2363 status = serial_port_in(port, SCLSR);
2364 status &= ~(SCLSR_TO | SCLSR_ORER);
2365 serial_port_out(port, SCLSR, status);
2366 }
2367
2368 if (s->rx_trigger > 1) {
2369 if (s->rx_fifo_timeout) {
2370 scif_set_rtrg(port, 1);
2371 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2372 } else {
2373 if (port->type == PORT_SCIFA ||
2374 port->type == PORT_SCIFB)
2375 scif_set_rtrg(port, 1);
2376 else
2377 scif_set_rtrg(port, s->rx_trigger);
2378 }
2379 }
2380}
2381
2382static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2383 struct ktermios *old)
2384{
2385 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2386 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2387 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2388 struct sci_port *s = to_sci_port(port);
2389 const struct plat_sci_reg *reg;
2390 int min_err = INT_MAX, err;
2391 unsigned long max_freq = 0;
2392 int best_clk = -1;
2393 unsigned long flags;
2394
2395 if ((termios->c_cflag & CSIZE) == CS7)
2396 smr_val |= SCSMR_CHR;
2397 if (termios->c_cflag & PARENB)
2398 smr_val |= SCSMR_PE;
2399 if (termios->c_cflag & PARODD)
2400 smr_val |= SCSMR_PE | SCSMR_ODD;
2401 if (termios->c_cflag & CSTOPB)
2402 smr_val |= SCSMR_STOP;
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412 if (!port->uartclk) {
2413 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2414 goto done;
2415 }
2416
2417 for (i = 0; i < SCI_NUM_CLKS; i++)
2418 max_freq = max(max_freq, s->clk_rates[i]);
2419
2420 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2421 if (!baud)
2422 goto done;
2423
2424
2425
2426
2427
2428
2429
2430 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2431 port->type != PORT_SCIFB) {
2432 err = sci_sck_calc(s, baud, &srr1);
2433 if (abs(err) < abs(min_err)) {
2434 best_clk = SCI_SCK;
2435 scr_val = SCSCR_CKE1;
2436 sccks = SCCKS_CKS;
2437 min_err = err;
2438 srr = srr1;
2439 if (!err)
2440 goto done;
2441 }
2442 }
2443
2444
2445 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2446 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2447 &srr1);
2448 if (abs(err) < abs(min_err)) {
2449 best_clk = SCI_SCIF_CLK;
2450 scr_val = SCSCR_CKE1;
2451 sccks = 0;
2452 min_err = err;
2453 dl = dl1;
2454 srr = srr1;
2455 if (!err)
2456 goto done;
2457 }
2458 }
2459
2460
2461 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2462 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2463 &srr1);
2464 if (abs(err) < abs(min_err)) {
2465 best_clk = SCI_BRG_INT;
2466 scr_val = SCSCR_CKE1;
2467 sccks = SCCKS_XIN;
2468 min_err = err;
2469 dl = dl1;
2470 srr = srr1;
2471 if (!min_err)
2472 goto done;
2473 }
2474 }
2475
2476
2477 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2478 if (abs(err) < abs(min_err)) {
2479 best_clk = SCI_FCK;
2480 scr_val = 0;
2481 min_err = err;
2482 brr = brr1;
2483 srr = srr1;
2484 cks = cks1;
2485 }
2486
2487done:
2488 if (best_clk >= 0)
2489 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2490 s->clks[best_clk], baud, min_err);
2491
2492 sci_port_enable(s);
2493
2494
2495
2496
2497
2498 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2499 serial_port_out(port, SCDL, dl);
2500 serial_port_out(port, SCCKS, sccks);
2501 }
2502
2503 spin_lock_irqsave(&port->lock, flags);
2504
2505 sci_reset(port);
2506
2507 uart_update_timeout(port, termios->c_cflag, baud);
2508
2509
2510 switch (termios->c_cflag & CSIZE) {
2511 case CS5:
2512 bits = 7;
2513 break;
2514 case CS6:
2515 bits = 8;
2516 break;
2517 case CS7:
2518 bits = 9;
2519 break;
2520 default:
2521 bits = 10;
2522 break;
2523 }
2524
2525 if (termios->c_cflag & CSTOPB)
2526 bits++;
2527 if (termios->c_cflag & PARENB)
2528 bits++;
2529
2530 if (best_clk >= 0) {
2531 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2532 switch (srr + 1) {
2533 case 5: smr_val |= SCSMR_SRC_5; break;
2534 case 7: smr_val |= SCSMR_SRC_7; break;
2535 case 11: smr_val |= SCSMR_SRC_11; break;
2536 case 13: smr_val |= SCSMR_SRC_13; break;
2537 case 16: smr_val |= SCSMR_SRC_16; break;
2538 case 17: smr_val |= SCSMR_SRC_17; break;
2539 case 19: smr_val |= SCSMR_SRC_19; break;
2540 case 27: smr_val |= SCSMR_SRC_27; break;
2541 }
2542 smr_val |= cks;
2543 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2544 serial_port_out(port, SCSMR, smr_val);
2545 serial_port_out(port, SCBRR, brr);
2546 if (sci_getreg(port, HSSRR)->size) {
2547 unsigned int hssrr = srr | HSCIF_SRE;
2548
2549
2550
2551 int last_stop = bits * 2 - 1;
2552 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop *
2553 (int)(srr + 1),
2554 2 * (int)baud);
2555
2556 if (abs(deviation) >= 2) {
2557
2558
2559
2560
2561 int shift = clamp(deviation / 2, -8, 7);
2562
2563 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2564 HSCIF_SRHP_MASK;
2565 hssrr |= HSCIF_SRDE;
2566 }
2567 serial_port_out(port, HSSRR, hssrr);
2568 }
2569
2570
2571 udelay((1000000 + (baud - 1)) / baud);
2572 } else {
2573
2574 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2575 smr_val |= serial_port_in(port, SCSMR) &
2576 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2577 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2578 serial_port_out(port, SCSMR, smr_val);
2579 }
2580
2581 sci_init_pins(port, termios->c_cflag);
2582
2583 port->status &= ~UPSTAT_AUTOCTS;
2584 s->autorts = false;
2585 reg = sci_getreg(port, SCFCR);
2586 if (reg->size) {
2587 unsigned short ctrl = serial_port_in(port, SCFCR);
2588
2589 if ((port->flags & UPF_HARD_FLOW) &&
2590 (termios->c_cflag & CRTSCTS)) {
2591
2592 port->status |= UPSTAT_AUTOCTS;
2593
2594 s->autorts = true;
2595 }
2596
2597
2598
2599
2600
2601
2602 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2603
2604 serial_port_out(port, SCFCR, ctrl);
2605 }
2606 if (port->flags & UPF_HARD_FLOW) {
2607
2608 sci_set_mctrl(port, port->mctrl);
2609 }
2610
2611 scr_val |= SCSCR_RE | SCSCR_TE |
2612 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2613 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2614 if ((srr + 1 == 5) &&
2615 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2616
2617
2618
2619
2620
2621
2622 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2623 }
2624
2625
2626 s->rx_frame = (10000 * bits) / (baud / 100);
2627#ifdef CONFIG_SERIAL_SH_SCI_DMA
2628 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2629#endif
2630
2631 if ((termios->c_cflag & CREAD) != 0)
2632 sci_start_rx(port);
2633
2634 spin_unlock_irqrestore(&port->lock, flags);
2635
2636 sci_port_disable(s);
2637
2638 if (UART_ENABLE_MS(port, termios->c_cflag))
2639 sci_enable_ms(port);
2640}
2641
2642static void sci_pm(struct uart_port *port, unsigned int state,
2643 unsigned int oldstate)
2644{
2645 struct sci_port *sci_port = to_sci_port(port);
2646
2647 switch (state) {
2648 case UART_PM_STATE_OFF:
2649 sci_port_disable(sci_port);
2650 break;
2651 default:
2652 sci_port_enable(sci_port);
2653 break;
2654 }
2655}
2656
2657static const char *sci_type(struct uart_port *port)
2658{
2659 switch (port->type) {
2660 case PORT_IRDA:
2661 return "irda";
2662 case PORT_SCI:
2663 return "sci";
2664 case PORT_SCIF:
2665 return "scif";
2666 case PORT_SCIFA:
2667 return "scifa";
2668 case PORT_SCIFB:
2669 return "scifb";
2670 case PORT_HSCIF:
2671 return "hscif";
2672 }
2673
2674 return NULL;
2675}
2676
2677static int sci_remap_port(struct uart_port *port)
2678{
2679 struct sci_port *sport = to_sci_port(port);
2680
2681
2682
2683
2684 if (port->membase)
2685 return 0;
2686
2687 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2688 port->membase = ioremap(port->mapbase, sport->reg_size);
2689 if (unlikely(!port->membase)) {
2690 dev_err(port->dev, "can't remap port#%d\n", port->line);
2691 return -ENXIO;
2692 }
2693 } else {
2694
2695
2696
2697
2698
2699 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2700 }
2701
2702 return 0;
2703}
2704
2705static void sci_release_port(struct uart_port *port)
2706{
2707 struct sci_port *sport = to_sci_port(port);
2708
2709 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2710 iounmap(port->membase);
2711 port->membase = NULL;
2712 }
2713
2714 release_mem_region(port->mapbase, sport->reg_size);
2715}
2716
2717static int sci_request_port(struct uart_port *port)
2718{
2719 struct resource *res;
2720 struct sci_port *sport = to_sci_port(port);
2721 int ret;
2722
2723 res = request_mem_region(port->mapbase, sport->reg_size,
2724 dev_name(port->dev));
2725 if (unlikely(res == NULL)) {
2726 dev_err(port->dev, "request_mem_region failed.");
2727 return -EBUSY;
2728 }
2729
2730 ret = sci_remap_port(port);
2731 if (unlikely(ret != 0)) {
2732 release_resource(res);
2733 return ret;
2734 }
2735
2736 return 0;
2737}
2738
2739static void sci_config_port(struct uart_port *port, int flags)
2740{
2741 if (flags & UART_CONFIG_TYPE) {
2742 struct sci_port *sport = to_sci_port(port);
2743
2744 port->type = sport->cfg->type;
2745 sci_request_port(port);
2746 }
2747}
2748
2749static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2750{
2751 if (ser->baud_base < 2400)
2752
2753 return -EINVAL;
2754
2755 return 0;
2756}
2757
2758static const struct uart_ops sci_uart_ops = {
2759 .tx_empty = sci_tx_empty,
2760 .set_mctrl = sci_set_mctrl,
2761 .get_mctrl = sci_get_mctrl,
2762 .start_tx = sci_start_tx,
2763 .stop_tx = sci_stop_tx,
2764 .stop_rx = sci_stop_rx,
2765 .enable_ms = sci_enable_ms,
2766 .break_ctl = sci_break_ctl,
2767 .startup = sci_startup,
2768 .shutdown = sci_shutdown,
2769 .flush_buffer = sci_flush_buffer,
2770 .set_termios = sci_set_termios,
2771 .pm = sci_pm,
2772 .type = sci_type,
2773 .release_port = sci_release_port,
2774 .request_port = sci_request_port,
2775 .config_port = sci_config_port,
2776 .verify_port = sci_verify_port,
2777#ifdef CONFIG_CONSOLE_POLL
2778 .poll_get_char = sci_poll_get_char,
2779 .poll_put_char = sci_poll_put_char,
2780#endif
2781};
2782
2783static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2784{
2785 const char *clk_names[] = {
2786 [SCI_FCK] = "fck",
2787 [SCI_SCK] = "sck",
2788 [SCI_BRG_INT] = "brg_int",
2789 [SCI_SCIF_CLK] = "scif_clk",
2790 };
2791 struct clk *clk;
2792 unsigned int i;
2793
2794 if (sci_port->cfg->type == PORT_HSCIF)
2795 clk_names[SCI_SCK] = "hsck";
2796
2797 for (i = 0; i < SCI_NUM_CLKS; i++) {
2798 clk = devm_clk_get(dev, clk_names[i]);
2799 if (PTR_ERR(clk) == -EPROBE_DEFER)
2800 return -EPROBE_DEFER;
2801
2802 if (IS_ERR(clk) && i == SCI_FCK) {
2803
2804
2805
2806
2807 clk = devm_clk_get(dev, "sci_ick");
2808 if (PTR_ERR(clk) == -EPROBE_DEFER)
2809 return -EPROBE_DEFER;
2810
2811 if (!IS_ERR(clk))
2812 goto found;
2813
2814
2815
2816
2817
2818
2819 clk = devm_clk_get(dev, "peripheral_clk");
2820 if (!IS_ERR(clk))
2821 goto found;
2822
2823 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2824 PTR_ERR(clk));
2825 return PTR_ERR(clk);
2826 }
2827
2828found:
2829 if (IS_ERR(clk))
2830 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2831 PTR_ERR(clk));
2832 else
2833 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2834 clk, clk_get_rate(clk));
2835 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2836 }
2837 return 0;
2838}
2839
2840static const struct sci_port_params *
2841sci_probe_regmap(const struct plat_sci_port *cfg)
2842{
2843 unsigned int regtype;
2844
2845 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2846 return &sci_port_params[cfg->regtype];
2847
2848 switch (cfg->type) {
2849 case PORT_SCI:
2850 regtype = SCIx_SCI_REGTYPE;
2851 break;
2852 case PORT_IRDA:
2853 regtype = SCIx_IRDA_REGTYPE;
2854 break;
2855 case PORT_SCIFA:
2856 regtype = SCIx_SCIFA_REGTYPE;
2857 break;
2858 case PORT_SCIFB:
2859 regtype = SCIx_SCIFB_REGTYPE;
2860 break;
2861 case PORT_SCIF:
2862
2863
2864
2865
2866
2867
2868 regtype = SCIx_SH4_SCIF_REGTYPE;
2869 break;
2870 case PORT_HSCIF:
2871 regtype = SCIx_HSCIF_REGTYPE;
2872 break;
2873 default:
2874 pr_err("Can't probe register map for given port\n");
2875 return NULL;
2876 }
2877
2878 return &sci_port_params[regtype];
2879}
2880
2881static int sci_init_single(struct platform_device *dev,
2882 struct sci_port *sci_port, unsigned int index,
2883 const struct plat_sci_port *p, bool early)
2884{
2885 struct uart_port *port = &sci_port->port;
2886 const struct resource *res;
2887 unsigned int i;
2888 int ret;
2889
2890 sci_port->cfg = p;
2891
2892 port->ops = &sci_uart_ops;
2893 port->iotype = UPIO_MEM;
2894 port->line = index;
2895 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE);
2896
2897 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2898 if (res == NULL)
2899 return -ENOMEM;
2900
2901 port->mapbase = res->start;
2902 sci_port->reg_size = resource_size(res);
2903
2904 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) {
2905 if (i)
2906 sci_port->irqs[i] = platform_get_irq_optional(dev, i);
2907 else
2908 sci_port->irqs[i] = platform_get_irq(dev, i);
2909 }
2910
2911
2912
2913
2914
2915
2916
2917
2918 if (sci_port->irqs[0] < 0)
2919 return -ENXIO;
2920
2921 if (sci_port->irqs[1] < 0)
2922 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
2923 sci_port->irqs[i] = sci_port->irqs[0];
2924
2925 sci_port->params = sci_probe_regmap(p);
2926 if (unlikely(sci_port->params == NULL))
2927 return -EINVAL;
2928
2929 switch (p->type) {
2930 case PORT_SCIFB:
2931 sci_port->rx_trigger = 48;
2932 break;
2933 case PORT_HSCIF:
2934 sci_port->rx_trigger = 64;
2935 break;
2936 case PORT_SCIFA:
2937 sci_port->rx_trigger = 32;
2938 break;
2939 case PORT_SCIF:
2940 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2941
2942 sci_port->rx_trigger = 1;
2943 else
2944 sci_port->rx_trigger = 8;
2945 break;
2946 default:
2947 sci_port->rx_trigger = 1;
2948 break;
2949 }
2950
2951 sci_port->rx_fifo_timeout = 0;
2952 sci_port->hscif_tot = 0;
2953
2954
2955
2956
2957
2958 sci_port->sampling_rate_mask = p->sampling_rate
2959 ? SCI_SR(p->sampling_rate)
2960 : sci_port->params->sampling_rate_mask;
2961
2962 if (!early) {
2963 ret = sci_init_clocks(sci_port, &dev->dev);
2964 if (ret < 0)
2965 return ret;
2966
2967 port->dev = &dev->dev;
2968
2969 pm_runtime_enable(&dev->dev);
2970 }
2971
2972 port->type = p->type;
2973 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
2974 port->fifosize = sci_port->params->fifosize;
2975
2976 if (port->type == PORT_SCI) {
2977 if (sci_port->reg_size >= 0x20)
2978 port->regshift = 2;
2979 else
2980 port->regshift = 1;
2981 }
2982
2983
2984
2985
2986
2987
2988
2989
2990 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2991 port->irqflags = 0;
2992
2993 port->serial_in = sci_serial_in;
2994 port->serial_out = sci_serial_out;
2995
2996 return 0;
2997}
2998
2999static void sci_cleanup_single(struct sci_port *port)
3000{
3001 pm_runtime_disable(port->port.dev);
3002}
3003
3004#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
3005 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
3006static void serial_console_putchar(struct uart_port *port, int ch)
3007{
3008 sci_poll_put_char(port, ch);
3009}
3010
3011
3012
3013
3014
3015static void serial_console_write(struct console *co, const char *s,
3016 unsigned count)
3017{
3018 struct sci_port *sci_port = &sci_ports[co->index];
3019 struct uart_port *port = &sci_port->port;
3020 unsigned short bits, ctrl, ctrl_temp;
3021 unsigned long flags;
3022 int locked = 1;
3023
3024 if (port->sysrq)
3025 locked = 0;
3026 else if (oops_in_progress)
3027 locked = spin_trylock_irqsave(&port->lock, flags);
3028 else
3029 spin_lock_irqsave(&port->lock, flags);
3030
3031
3032 ctrl = serial_port_in(port, SCSCR);
3033 ctrl_temp = SCSCR_RE | SCSCR_TE |
3034 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
3035 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
3036 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
3037
3038 uart_console_write(port, s, count, serial_console_putchar);
3039
3040
3041 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
3042 while ((serial_port_in(port, SCxSR) & bits) != bits)
3043 cpu_relax();
3044
3045
3046 serial_port_out(port, SCSCR, ctrl);
3047
3048 if (locked)
3049 spin_unlock_irqrestore(&port->lock, flags);
3050}
3051
3052static int serial_console_setup(struct console *co, char *options)
3053{
3054 struct sci_port *sci_port;
3055 struct uart_port *port;
3056 int baud = 115200;
3057 int bits = 8;
3058 int parity = 'n';
3059 int flow = 'n';
3060 int ret;
3061
3062
3063
3064
3065 if (co->index < 0 || co->index >= SCI_NPORTS)
3066 return -ENODEV;
3067
3068 sci_port = &sci_ports[co->index];
3069 port = &sci_port->port;
3070
3071
3072
3073
3074 if (!port->ops)
3075 return -ENODEV;
3076
3077 ret = sci_remap_port(port);
3078 if (unlikely(ret != 0))
3079 return ret;
3080
3081 if (options)
3082 uart_parse_options(options, &baud, &parity, &bits, &flow);
3083
3084 return uart_set_options(port, co, baud, parity, bits, flow);
3085}
3086
3087static struct console serial_console = {
3088 .name = "ttySC",
3089 .device = uart_console_device,
3090 .write = serial_console_write,
3091 .setup = serial_console_setup,
3092 .flags = CON_PRINTBUFFER,
3093 .index = -1,
3094 .data = &sci_uart_driver,
3095};
3096
3097#ifdef CONFIG_SUPERH
3098static struct console early_serial_console = {
3099 .name = "early_ttySC",
3100 .write = serial_console_write,
3101 .flags = CON_PRINTBUFFER,
3102 .index = -1,
3103};
3104
3105static char early_serial_buf[32];
3106
3107static int sci_probe_earlyprintk(struct platform_device *pdev)
3108{
3109 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
3110
3111 if (early_serial_console.data)
3112 return -EEXIST;
3113
3114 early_serial_console.index = pdev->id;
3115
3116 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
3117
3118 serial_console_setup(&early_serial_console, early_serial_buf);
3119
3120 if (!strstr(early_serial_buf, "keep"))
3121 early_serial_console.flags |= CON_BOOT;
3122
3123 register_console(&early_serial_console);
3124 return 0;
3125}
3126#endif
3127
3128#define SCI_CONSOLE (&serial_console)
3129
3130#else
3131static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3132{
3133 return -EINVAL;
3134}
3135
3136#define SCI_CONSOLE NULL
3137
3138#endif
3139
3140static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3141
3142static DEFINE_MUTEX(sci_uart_registration_lock);
3143static struct uart_driver sci_uart_driver = {
3144 .owner = THIS_MODULE,
3145 .driver_name = "sci",
3146 .dev_name = "ttySC",
3147 .major = SCI_MAJOR,
3148 .minor = SCI_MINOR_START,
3149 .nr = SCI_NPORTS,
3150 .cons = SCI_CONSOLE,
3151};
3152
3153static int sci_remove(struct platform_device *dev)
3154{
3155 struct sci_port *port = platform_get_drvdata(dev);
3156 unsigned int type = port->port.type;
3157
3158 sci_ports_in_use &= ~BIT(port->port.line);
3159 uart_remove_one_port(&sci_uart_driver, &port->port);
3160
3161 sci_cleanup_single(port);
3162
3163 if (port->port.fifosize > 1)
3164 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3165 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF)
3166 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3167
3168 return 0;
3169}
3170
3171
3172#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3173#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3174#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
3175
3176static const struct of_device_id of_sci_match[] = {
3177
3178 {
3179 .compatible = "renesas,scif-r7s72100",
3180 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3181 },
3182 {
3183 .compatible = "renesas,scif-r7s9210",
3184 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3185 },
3186
3187 {
3188 .compatible = "renesas,rcar-gen1-scif",
3189 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3190 }, {
3191 .compatible = "renesas,rcar-gen2-scif",
3192 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3193 }, {
3194 .compatible = "renesas,rcar-gen3-scif",
3195 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3196 },
3197
3198 {
3199 .compatible = "renesas,scif",
3200 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
3201 }, {
3202 .compatible = "renesas,scifa",
3203 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
3204 }, {
3205 .compatible = "renesas,scifb",
3206 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3207 }, {
3208 .compatible = "renesas,hscif",
3209 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3210 }, {
3211 .compatible = "renesas,sci",
3212 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3213 }, {
3214
3215 },
3216};
3217MODULE_DEVICE_TABLE(of, of_sci_match);
3218
3219static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3220 unsigned int *dev_id)
3221{
3222 struct device_node *np = pdev->dev.of_node;
3223 struct plat_sci_port *p;
3224 struct sci_port *sp;
3225 const void *data;
3226 int id;
3227
3228 if (!IS_ENABLED(CONFIG_OF) || !np)
3229 return NULL;
3230
3231 data = of_device_get_match_data(&pdev->dev);
3232
3233 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3234 if (!p)
3235 return NULL;
3236
3237
3238 id = of_alias_get_id(np, "serial");
3239 if (id < 0 && ~sci_ports_in_use)
3240 id = ffz(sci_ports_in_use);
3241 if (id < 0) {
3242 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3243 return NULL;
3244 }
3245 if (id >= ARRAY_SIZE(sci_ports)) {
3246 dev_err(&pdev->dev, "serial%d out of range\n", id);
3247 return NULL;
3248 }
3249
3250 sp = &sci_ports[id];
3251 *dev_id = id;
3252
3253 p->type = SCI_OF_TYPE(data);
3254 p->regtype = SCI_OF_REGTYPE(data);
3255
3256 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3257
3258 return p;
3259}
3260
3261static int sci_probe_single(struct platform_device *dev,
3262 unsigned int index,
3263 struct plat_sci_port *p,
3264 struct sci_port *sciport)
3265{
3266 int ret;
3267
3268
3269 if (unlikely(index >= SCI_NPORTS)) {
3270 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3271 index+1, SCI_NPORTS);
3272 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3273 return -EINVAL;
3274 }
3275 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3276 if (sci_ports_in_use & BIT(index))
3277 return -EBUSY;
3278
3279 mutex_lock(&sci_uart_registration_lock);
3280 if (!sci_uart_driver.state) {
3281 ret = uart_register_driver(&sci_uart_driver);
3282 if (ret) {
3283 mutex_unlock(&sci_uart_registration_lock);
3284 return ret;
3285 }
3286 }
3287 mutex_unlock(&sci_uart_registration_lock);
3288
3289 ret = sci_init_single(dev, sciport, index, p, false);
3290 if (ret)
3291 return ret;
3292
3293 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3294 if (IS_ERR(sciport->gpios))
3295 return PTR_ERR(sciport->gpios);
3296
3297 if (sciport->has_rtscts) {
3298 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) ||
3299 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) {
3300 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3301 return -EINVAL;
3302 }
3303 sciport->port.flags |= UPF_HARD_FLOW;
3304 }
3305
3306 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3307 if (ret) {
3308 sci_cleanup_single(sciport);
3309 return ret;
3310 }
3311
3312 return 0;
3313}
3314
3315static int sci_probe(struct platform_device *dev)
3316{
3317 struct plat_sci_port *p;
3318 struct sci_port *sp;
3319 unsigned int dev_id;
3320 int ret;
3321
3322
3323
3324
3325
3326
3327#ifdef CONFIG_SUPERH
3328 if (is_sh_early_platform_device(dev))
3329 return sci_probe_earlyprintk(dev);
3330#endif
3331
3332 if (dev->dev.of_node) {
3333 p = sci_parse_dt(dev, &dev_id);
3334 if (p == NULL)
3335 return -EINVAL;
3336 } else {
3337 p = dev->dev.platform_data;
3338 if (p == NULL) {
3339 dev_err(&dev->dev, "no platform data supplied\n");
3340 return -EINVAL;
3341 }
3342
3343 dev_id = dev->id;
3344 }
3345
3346 sp = &sci_ports[dev_id];
3347 platform_set_drvdata(dev, sp);
3348
3349 ret = sci_probe_single(dev, dev_id, p, sp);
3350 if (ret)
3351 return ret;
3352
3353 if (sp->port.fifosize > 1) {
3354 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3355 if (ret)
3356 return ret;
3357 }
3358 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3359 sp->port.type == PORT_HSCIF) {
3360 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3361 if (ret) {
3362 if (sp->port.fifosize > 1) {
3363 device_remove_file(&dev->dev,
3364 &dev_attr_rx_fifo_trigger);
3365 }
3366 return ret;
3367 }
3368 }
3369
3370#ifdef CONFIG_SH_STANDARD_BIOS
3371 sh_bios_gdb_detach();
3372#endif
3373
3374 sci_ports_in_use |= BIT(dev_id);
3375 return 0;
3376}
3377
3378static __maybe_unused int sci_suspend(struct device *dev)
3379{
3380 struct sci_port *sport = dev_get_drvdata(dev);
3381
3382 if (sport)
3383 uart_suspend_port(&sci_uart_driver, &sport->port);
3384
3385 return 0;
3386}
3387
3388static __maybe_unused int sci_resume(struct device *dev)
3389{
3390 struct sci_port *sport = dev_get_drvdata(dev);
3391
3392 if (sport)
3393 uart_resume_port(&sci_uart_driver, &sport->port);
3394
3395 return 0;
3396}
3397
3398static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3399
3400static struct platform_driver sci_driver = {
3401 .probe = sci_probe,
3402 .remove = sci_remove,
3403 .driver = {
3404 .name = "sh-sci",
3405 .pm = &sci_dev_pm_ops,
3406 .of_match_table = of_match_ptr(of_sci_match),
3407 },
3408};
3409
3410static int __init sci_init(void)
3411{
3412 pr_info("%s\n", banner);
3413
3414 return platform_driver_register(&sci_driver);
3415}
3416
3417static void __exit sci_exit(void)
3418{
3419 platform_driver_unregister(&sci_driver);
3420
3421 if (sci_uart_driver.state)
3422 uart_unregister_driver(&sci_uart_driver);
3423}
3424
3425#if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
3426sh_early_platform_init_buffer("earlyprintk", &sci_driver,
3427 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3428#endif
3429#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3430static struct plat_sci_port port_cfg __initdata;
3431
3432static int __init early_console_setup(struct earlycon_device *device,
3433 int type)
3434{
3435 if (!device->port.membase)
3436 return -ENODEV;
3437
3438 device->port.serial_in = sci_serial_in;
3439 device->port.serial_out = sci_serial_out;
3440 device->port.type = type;
3441 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3442 port_cfg.type = type;
3443 sci_ports[0].cfg = &port_cfg;
3444 sci_ports[0].params = sci_probe_regmap(&port_cfg);
3445 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3446 sci_serial_out(&sci_ports[0].port, SCSCR,
3447 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3448
3449 device->con->write = serial_console_write;
3450 return 0;
3451}
3452static int __init sci_early_console_setup(struct earlycon_device *device,
3453 const char *opt)
3454{
3455 return early_console_setup(device, PORT_SCI);
3456}
3457static int __init scif_early_console_setup(struct earlycon_device *device,
3458 const char *opt)
3459{
3460 return early_console_setup(device, PORT_SCIF);
3461}
3462static int __init rzscifa_early_console_setup(struct earlycon_device *device,
3463 const char *opt)
3464{
3465 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
3466 return early_console_setup(device, PORT_SCIF);
3467}
3468static int __init scifa_early_console_setup(struct earlycon_device *device,
3469 const char *opt)
3470{
3471 return early_console_setup(device, PORT_SCIFA);
3472}
3473static int __init scifb_early_console_setup(struct earlycon_device *device,
3474 const char *opt)
3475{
3476 return early_console_setup(device, PORT_SCIFB);
3477}
3478static int __init hscif_early_console_setup(struct earlycon_device *device,
3479 const char *opt)
3480{
3481 return early_console_setup(device, PORT_HSCIF);
3482}
3483
3484OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3485OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3486OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
3487OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3488OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3489OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3490#endif
3491
3492module_init(sci_init);
3493module_exit(sci_exit);
3494
3495MODULE_LICENSE("GPL");
3496MODULE_ALIAS("platform:sh-sci");
3497MODULE_AUTHOR("Paul Mundt");
3498MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
3499
