linux/drivers/tty/serial/sccnxp.c
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   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 *  NXP (Philips) SCC+++(SCN+++) serial driver
   4 *
   5 *  Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
   6 *
   7 *  Based on sc26xx.c, by Thomas Bogend\xC3\xB6rfer (tsbogend@alpha.franken.de)
   8 */
   9
  10#include <linux/clk.h>
  11#include <linux/delay.h>
  12#include <linux/err.h>
  13#include <linux/module.h>
  14#include <linux/mod_devicetable.h>
  15#include <linux/device.h>
  16#include <linux/console.h>
  17#include <linux/serial_core.h>
  18#include <linux/serial.h>
  19#include <linux/io.h>
  20#include <linux/tty.h>
  21#include <linux/tty_flip.h>
  22#include <linux/spinlock.h>
  23#include <linux/platform_device.h>
  24#include <linux/platform_data/serial-sccnxp.h>
  25#include <linux/regulator/consumer.h>
  26
  27#define SCCNXP_NAME                     "uart-sccnxp"
  28#define SCCNXP_MAJOR                    204
  29#define SCCNXP_MINOR                    205
  30
  31#define SCCNXP_MR_REG                   (0x00)
  32#       define MR0_BAUD_NORMAL          (0 << 0)
  33#       define MR0_BAUD_EXT1            (1 << 0)
  34#       define MR0_BAUD_EXT2            (5 << 0)
  35#       define MR0_FIFO                 (1 << 3)
  36#       define MR0_TXLVL                (1 << 4)
  37#       define MR1_BITS_5               (0 << 0)
  38#       define MR1_BITS_6               (1 << 0)
  39#       define MR1_BITS_7               (2 << 0)
  40#       define MR1_BITS_8               (3 << 0)
  41#       define MR1_PAR_EVN              (0 << 2)
  42#       define MR1_PAR_ODD              (1 << 2)
  43#       define MR1_PAR_NO               (4 << 2)
  44#       define MR2_STOP1                (7 << 0)
  45#       define MR2_STOP2                (0xf << 0)
  46#define SCCNXP_SR_REG                   (0x01)
  47#       define SR_RXRDY                 (1 << 0)
  48#       define SR_FULL                  (1 << 1)
  49#       define SR_TXRDY                 (1 << 2)
  50#       define SR_TXEMT                 (1 << 3)
  51#       define SR_OVR                   (1 << 4)
  52#       define SR_PE                    (1 << 5)
  53#       define SR_FE                    (1 << 6)
  54#       define SR_BRK                   (1 << 7)
  55#define SCCNXP_CSR_REG                  (SCCNXP_SR_REG)
  56#       define CSR_TIMER_MODE           (0x0d)
  57#define SCCNXP_CR_REG                   (0x02)
  58#       define CR_RX_ENABLE             (1 << 0)
  59#       define CR_RX_DISABLE            (1 << 1)
  60#       define CR_TX_ENABLE             (1 << 2)
  61#       define CR_TX_DISABLE            (1 << 3)
  62#       define CR_CMD_MRPTR1            (0x01 << 4)
  63#       define CR_CMD_RX_RESET          (0x02 << 4)
  64#       define CR_CMD_TX_RESET          (0x03 << 4)
  65#       define CR_CMD_STATUS_RESET      (0x04 << 4)
  66#       define CR_CMD_BREAK_RESET       (0x05 << 4)
  67#       define CR_CMD_START_BREAK       (0x06 << 4)
  68#       define CR_CMD_STOP_BREAK        (0x07 << 4)
  69#       define CR_CMD_MRPTR0            (0x0b << 4)
  70#define SCCNXP_RHR_REG                  (0x03)
  71#define SCCNXP_THR_REG                  SCCNXP_RHR_REG
  72#define SCCNXP_IPCR_REG                 (0x04)
  73#define SCCNXP_ACR_REG                  SCCNXP_IPCR_REG
  74#       define ACR_BAUD0                (0 << 7)
  75#       define ACR_BAUD1                (1 << 7)
  76#       define ACR_TIMER_MODE           (6 << 4)
  77#define SCCNXP_ISR_REG                  (0x05)
  78#define SCCNXP_IMR_REG                  SCCNXP_ISR_REG
  79#       define IMR_TXRDY                (1 << 0)
  80#       define IMR_RXRDY                (1 << 1)
  81#       define ISR_TXRDY(x)             (1 << ((x * 4) + 0))
  82#       define ISR_RXRDY(x)             (1 << ((x * 4) + 1))
  83#define SCCNXP_CTPU_REG                 (0x06)
  84#define SCCNXP_CTPL_REG                 (0x07)
  85#define SCCNXP_IPR_REG                  (0x0d)
  86#define SCCNXP_OPCR_REG                 SCCNXP_IPR_REG
  87#define SCCNXP_SOP_REG                  (0x0e)
  88#define SCCNXP_START_COUNTER_REG        SCCNXP_SOP_REG
  89#define SCCNXP_ROP_REG                  (0x0f)
  90
  91/* Route helpers */
  92#define MCTRL_MASK(sig)                 (0xf << (sig))
  93#define MCTRL_IBIT(cfg, sig)            ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
  94#define MCTRL_OBIT(cfg, sig)            ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
  95
  96#define SCCNXP_HAVE_IO          0x00000001
  97#define SCCNXP_HAVE_MR0         0x00000002
  98
  99struct sccnxp_chip {
 100        const char              *name;
 101        unsigned int            nr;
 102        unsigned long           freq_min;
 103        unsigned long           freq_std;
 104        unsigned long           freq_max;
 105        unsigned int            flags;
 106        unsigned int            fifosize;
 107        /* Time between read/write cycles */
 108        unsigned int            trwd;
 109};
 110
 111struct sccnxp_port {
 112        struct uart_driver      uart;
 113        struct uart_port        port[SCCNXP_MAX_UARTS];
 114        bool                    opened[SCCNXP_MAX_UARTS];
 115
 116        int                     irq;
 117        u8                      imr;
 118
 119        struct sccnxp_chip      *chip;
 120
 121#ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
 122        struct console          console;
 123#endif
 124
 125        spinlock_t              lock;
 126
 127        bool                    poll;
 128        struct timer_list       timer;
 129
 130        struct sccnxp_pdata     pdata;
 131
 132        struct regulator        *regulator;
 133};
 134
 135static const struct sccnxp_chip sc2681 = {
 136        .name           = "SC2681",
 137        .nr             = 2,
 138        .freq_min       = 1000000,
 139        .freq_std       = 3686400,
 140        .freq_max       = 4000000,
 141        .flags          = SCCNXP_HAVE_IO,
 142        .fifosize       = 3,
 143        .trwd           = 200,
 144};
 145
 146static const struct sccnxp_chip sc2691 = {
 147        .name           = "SC2691",
 148        .nr             = 1,
 149        .freq_min       = 1000000,
 150        .freq_std       = 3686400,
 151        .freq_max       = 4000000,
 152        .flags          = 0,
 153        .fifosize       = 3,
 154        .trwd           = 150,
 155};
 156
 157static const struct sccnxp_chip sc2692 = {
 158        .name           = "SC2692",
 159        .nr             = 2,
 160        .freq_min       = 1000000,
 161        .freq_std       = 3686400,
 162        .freq_max       = 4000000,
 163        .flags          = SCCNXP_HAVE_IO,
 164        .fifosize       = 3,
 165        .trwd           = 30,
 166};
 167
 168static const struct sccnxp_chip sc2891 = {
 169        .name           = "SC2891",
 170        .nr             = 1,
 171        .freq_min       = 100000,
 172        .freq_std       = 3686400,
 173        .freq_max       = 8000000,
 174        .flags          = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
 175        .fifosize       = 16,
 176        .trwd           = 27,
 177};
 178
 179static const struct sccnxp_chip sc2892 = {
 180        .name           = "SC2892",
 181        .nr             = 2,
 182        .freq_min       = 100000,
 183        .freq_std       = 3686400,
 184        .freq_max       = 8000000,
 185        .flags          = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
 186        .fifosize       = 16,
 187        .trwd           = 17,
 188};
 189
 190static const struct sccnxp_chip sc28202 = {
 191        .name           = "SC28202",
 192        .nr             = 2,
 193        .freq_min       = 1000000,
 194        .freq_std       = 14745600,
 195        .freq_max       = 50000000,
 196        .flags          = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
 197        .fifosize       = 256,
 198        .trwd           = 10,
 199};
 200
 201static const struct sccnxp_chip sc68681 = {
 202        .name           = "SC68681",
 203        .nr             = 2,
 204        .freq_min       = 1000000,
 205        .freq_std       = 3686400,
 206        .freq_max       = 4000000,
 207        .flags          = SCCNXP_HAVE_IO,
 208        .fifosize       = 3,
 209        .trwd           = 200,
 210};
 211
 212static const struct sccnxp_chip sc68692 = {
 213        .name           = "SC68692",
 214        .nr             = 2,
 215        .freq_min       = 1000000,
 216        .freq_std       = 3686400,
 217        .freq_max       = 4000000,
 218        .flags          = SCCNXP_HAVE_IO,
 219        .fifosize       = 3,
 220        .trwd           = 200,
 221};
 222
 223static u8 sccnxp_read(struct uart_port *port, u8 reg)
 224{
 225        struct sccnxp_port *s = dev_get_drvdata(port->dev);
 226        u8 ret;
 227
 228        ret = readb(port->membase + (reg << port->regshift));
 229
 230        ndelay(s->chip->trwd);
 231
 232        return ret;
 233}
 234
 235static void sccnxp_write(struct uart_port *port, u8 reg, u8 v)
 236{
 237        struct sccnxp_port *s = dev_get_drvdata(port->dev);
 238
 239        writeb(v, port->membase + (reg << port->regshift));
 240
 241        ndelay(s->chip->trwd);
 242}
 243
 244static u8 sccnxp_port_read(struct uart_port *port, u8 reg)
 245{
 246        return sccnxp_read(port, (port->line << 3) + reg);
 247}
 248
 249static void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v)
 250{
 251        sccnxp_write(port, (port->line << 3) + reg, v);
 252}
 253
 254static int sccnxp_update_best_err(int a, int b, int *besterr)
 255{
 256        int err = abs(a - b);
 257
 258        if (*besterr > err) {
 259                *besterr = err;
 260                return 0;
 261        }
 262
 263        return 1;
 264}
 265
 266static const struct {
 267        u8      csr;
 268        u8      acr;
 269        u8      mr0;
 270        int     baud;
 271} baud_std[] = {
 272        { 0,    ACR_BAUD0,      MR0_BAUD_NORMAL,        50, },
 273        { 0,    ACR_BAUD1,      MR0_BAUD_NORMAL,        75, },
 274        { 1,    ACR_BAUD0,      MR0_BAUD_NORMAL,        110, },
 275        { 2,    ACR_BAUD0,      MR0_BAUD_NORMAL,        134, },
 276        { 3,    ACR_BAUD1,      MR0_BAUD_NORMAL,        150, },
 277        { 3,    ACR_BAUD0,      MR0_BAUD_NORMAL,        200, },
 278        { 4,    ACR_BAUD0,      MR0_BAUD_NORMAL,        300, },
 279        { 0,    ACR_BAUD1,      MR0_BAUD_EXT1,          450, },
 280        { 1,    ACR_BAUD0,      MR0_BAUD_EXT2,          880, },
 281        { 3,    ACR_BAUD1,      MR0_BAUD_EXT1,          900, },
 282        { 5,    ACR_BAUD0,      MR0_BAUD_NORMAL,        600, },
 283        { 7,    ACR_BAUD0,      MR0_BAUD_NORMAL,        1050, },
 284        { 2,    ACR_BAUD0,      MR0_BAUD_EXT2,          1076, },
 285        { 6,    ACR_BAUD0,      MR0_BAUD_NORMAL,        1200, },
 286        { 10,   ACR_BAUD1,      MR0_BAUD_NORMAL,        1800, },
 287        { 7,    ACR_BAUD1,      MR0_BAUD_NORMAL,        2000, },
 288        { 8,    ACR_BAUD0,      MR0_BAUD_NORMAL,        2400, },
 289        { 5,    ACR_BAUD1,      MR0_BAUD_EXT1,          3600, },
 290        { 9,    ACR_BAUD0,      MR0_BAUD_NORMAL,        4800, },
 291        { 10,   ACR_BAUD0,      MR0_BAUD_NORMAL,        7200, },
 292        { 11,   ACR_BAUD0,      MR0_BAUD_NORMAL,        9600, },
 293        { 8,    ACR_BAUD0,      MR0_BAUD_EXT1,          14400, },
 294        { 12,   ACR_BAUD1,      MR0_BAUD_NORMAL,        19200, },
 295        { 9,    ACR_BAUD0,      MR0_BAUD_EXT1,          28800, },
 296        { 12,   ACR_BAUD0,      MR0_BAUD_NORMAL,        38400, },
 297        { 11,   ACR_BAUD0,      MR0_BAUD_EXT1,          57600, },
 298        { 12,   ACR_BAUD1,      MR0_BAUD_EXT1,          115200, },
 299        { 12,   ACR_BAUD0,      MR0_BAUD_EXT1,          230400, },
 300        { 0, 0, 0, 0 }
 301};
 302
 303static int sccnxp_set_baud(struct uart_port *port, int baud)
 304{
 305        struct sccnxp_port *s = dev_get_drvdata(port->dev);
 306        int div_std, tmp_baud, bestbaud = INT_MAX, besterr = INT_MAX;
 307        struct sccnxp_chip *chip = s->chip;
 308        u8 i, acr = 0, csr = 0, mr0 = 0;
 309
 310        /* Find divisor to load to the timer preset registers */
 311        div_std = DIV_ROUND_CLOSEST(port->uartclk, 2 * 16 * baud);
 312        if ((div_std >= 2) && (div_std <= 0xffff)) {
 313                bestbaud = DIV_ROUND_CLOSEST(port->uartclk, 2 * 16 * div_std);
 314                sccnxp_update_best_err(baud, bestbaud, &besterr);
 315                csr = CSR_TIMER_MODE;
 316                sccnxp_port_write(port, SCCNXP_CTPU_REG, div_std >> 8);
 317                sccnxp_port_write(port, SCCNXP_CTPL_REG, div_std);
 318                /* Issue start timer/counter command */
 319                sccnxp_port_read(port, SCCNXP_START_COUNTER_REG);
 320        }
 321
 322        /* Find best baud from table */
 323        for (i = 0; baud_std[i].baud && besterr; i++) {
 324                if (baud_std[i].mr0 && !(chip->flags & SCCNXP_HAVE_MR0))
 325                        continue;
 326                div_std = DIV_ROUND_CLOSEST(chip->freq_std, baud_std[i].baud);
 327                tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std);
 328                if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) {
 329                        acr = baud_std[i].acr;
 330                        csr = baud_std[i].csr;
 331                        mr0 = baud_std[i].mr0;
 332                        bestbaud = tmp_baud;
 333                }
 334        }
 335
 336        if (chip->flags & SCCNXP_HAVE_MR0) {
 337                /* Enable FIFO, set half level for TX */
 338                mr0 |= MR0_FIFO | MR0_TXLVL;
 339                /* Update MR0 */
 340                sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0);
 341                sccnxp_port_write(port, SCCNXP_MR_REG, mr0);
 342        }
 343
 344        sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE);
 345        sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr);
 346
 347        if (baud != bestbaud)
 348                dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n",
 349                        baud, bestbaud);
 350
 351        return bestbaud;
 352}
 353
 354static void sccnxp_enable_irq(struct uart_port *port, int mask)
 355{
 356        struct sccnxp_port *s = dev_get_drvdata(port->dev);
 357
 358        s->imr |= mask << (port->line * 4);
 359        sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
 360}
 361
 362static void sccnxp_disable_irq(struct uart_port *port, int mask)
 363{
 364        struct sccnxp_port *s = dev_get_drvdata(port->dev);
 365
 366        s->imr &= ~(mask << (port->line * 4));
 367        sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
 368}
 369
 370static void sccnxp_set_bit(struct uart_port *port, int sig, int state)
 371{
 372        u8 bitmask;
 373        struct sccnxp_port *s = dev_get_drvdata(port->dev);
 374
 375        if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) {
 376                bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig);
 377                if (state)
 378                        sccnxp_write(port, SCCNXP_SOP_REG, bitmask);
 379                else
 380                        sccnxp_write(port, SCCNXP_ROP_REG, bitmask);
 381        }
 382}
 383
 384static void sccnxp_handle_rx(struct uart_port *port)
 385{
 386        u8 sr;
 387        unsigned int ch, flag;
 388
 389        for (;;) {
 390                sr = sccnxp_port_read(port, SCCNXP_SR_REG);
 391                if (!(sr & SR_RXRDY))
 392                        break;
 393                sr &= SR_PE | SR_FE | SR_OVR | SR_BRK;
 394
 395                ch = sccnxp_port_read(port, SCCNXP_RHR_REG);
 396
 397                port->icount.rx++;
 398                flag = TTY_NORMAL;
 399
 400                if (unlikely(sr)) {
 401                        if (sr & SR_BRK) {
 402                                port->icount.brk++;
 403                                sccnxp_port_write(port, SCCNXP_CR_REG,
 404                                                  CR_CMD_BREAK_RESET);
 405                                if (uart_handle_break(port))
 406                                        continue;
 407                        } else if (sr & SR_PE)
 408                                port->icount.parity++;
 409                        else if (sr & SR_FE)
 410                                port->icount.frame++;
 411                        else if (sr & SR_OVR) {
 412                                port->icount.overrun++;
 413                                sccnxp_port_write(port, SCCNXP_CR_REG,
 414                                                  CR_CMD_STATUS_RESET);
 415                        }
 416
 417                        sr &= port->read_status_mask;
 418                        if (sr & SR_BRK)
 419                                flag = TTY_BREAK;
 420                        else if (sr & SR_PE)
 421                                flag = TTY_PARITY;
 422                        else if (sr & SR_FE)
 423                                flag = TTY_FRAME;
 424                        else if (sr & SR_OVR)
 425                                flag = TTY_OVERRUN;
 426                }
 427
 428                if (uart_handle_sysrq_char(port, ch))
 429                        continue;
 430
 431                if (sr & port->ignore_status_mask)
 432                        continue;
 433
 434                uart_insert_char(port, sr, SR_OVR, ch, flag);
 435        }
 436
 437        tty_flip_buffer_push(&port->state->port);
 438}
 439
 440static void sccnxp_handle_tx(struct uart_port *port)
 441{
 442        u8 sr;
 443        struct circ_buf *xmit = &port->state->xmit;
 444        struct sccnxp_port *s = dev_get_drvdata(port->dev);
 445
 446        if (unlikely(port->x_char)) {
 447                sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char);
 448                port->icount.tx++;
 449                port->x_char = 0;
 450                return;
 451        }
 452
 453        if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 454                /* Disable TX if FIFO is empty */
 455                if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) {
 456                        sccnxp_disable_irq(port, IMR_TXRDY);
 457
 458                        /* Set direction to input */
 459                        if (s->chip->flags & SCCNXP_HAVE_IO)
 460                                sccnxp_set_bit(port, DIR_OP, 0);
 461                }
 462                return;
 463        }
 464
 465        while (!uart_circ_empty(xmit)) {
 466                sr = sccnxp_port_read(port, SCCNXP_SR_REG);
 467                if (!(sr & SR_TXRDY))
 468                        break;
 469
 470                sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]);
 471                xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 472                port->icount.tx++;
 473        }
 474
 475        if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 476                uart_write_wakeup(port);
 477}
 478
 479static void sccnxp_handle_events(struct sccnxp_port *s)
 480{
 481        int i;
 482        u8 isr;
 483
 484        do {
 485                isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG);
 486                isr &= s->imr;
 487                if (!isr)
 488                        break;
 489
 490                for (i = 0; i < s->uart.nr; i++) {
 491                        if (s->opened[i] && (isr & ISR_RXRDY(i)))
 492                                sccnxp_handle_rx(&s->port[i]);
 493                        if (s->opened[i] && (isr & ISR_TXRDY(i)))
 494                                sccnxp_handle_tx(&s->port[i]);
 495                }
 496        } while (1);
 497}
 498
 499static void sccnxp_timer(struct timer_list *t)
 500{
 501        struct sccnxp_port *s = from_timer(s, t, timer);
 502        unsigned long flags;
 503
 504        spin_lock_irqsave(&s->lock, flags);
 505        sccnxp_handle_events(s);
 506        spin_unlock_irqrestore(&s->lock, flags);
 507
 508        mod_timer(&s->timer, jiffies + usecs_to_jiffies(s->pdata.poll_time_us));
 509}
 510
 511static irqreturn_t sccnxp_ist(int irq, void *dev_id)
 512{
 513        struct sccnxp_port *s = (struct sccnxp_port *)dev_id;
 514        unsigned long flags;
 515
 516        spin_lock_irqsave(&s->lock, flags);
 517        sccnxp_handle_events(s);
 518        spin_unlock_irqrestore(&s->lock, flags);
 519
 520        return IRQ_HANDLED;
 521}
 522
 523static void sccnxp_start_tx(struct uart_port *port)
 524{
 525        struct sccnxp_port *s = dev_get_drvdata(port->dev);
 526        unsigned long flags;
 527
 528        spin_lock_irqsave(&s->lock, flags);
 529
 530        /* Set direction to output */
 531        if (s->chip->flags & SCCNXP_HAVE_IO)
 532                sccnxp_set_bit(port, DIR_OP, 1);
 533
 534        sccnxp_enable_irq(port, IMR_TXRDY);
 535
 536        spin_unlock_irqrestore(&s->lock, flags);
 537}
 538
 539static void sccnxp_stop_tx(struct uart_port *port)
 540{
 541        /* Do nothing */
 542}
 543
 544static void sccnxp_stop_rx(struct uart_port *port)
 545{
 546        struct sccnxp_port *s = dev_get_drvdata(port->dev);
 547        unsigned long flags;
 548
 549        spin_lock_irqsave(&s->lock, flags);
 550        sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE);
 551        spin_unlock_irqrestore(&s->lock, flags);
 552}
 553
 554static unsigned int sccnxp_tx_empty(struct uart_port *port)
 555{
 556        u8 val;
 557        unsigned long flags;
 558        struct sccnxp_port *s = dev_get_drvdata(port->dev);
 559
 560        spin_lock_irqsave(&s->lock, flags);
 561        val = sccnxp_port_read(port, SCCNXP_SR_REG);
 562        spin_unlock_irqrestore(&s->lock, flags);
 563
 564        return (val & SR_TXEMT) ? TIOCSER_TEMT : 0;
 565}
 566
 567static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl)
 568{
 569        struct sccnxp_port *s = dev_get_drvdata(port->dev);
 570        unsigned long flags;
 571
 572        if (!(s->chip->flags & SCCNXP_HAVE_IO))
 573                return;
 574
 575        spin_lock_irqsave(&s->lock, flags);
 576
 577        sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR);
 578        sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS);
 579
 580        spin_unlock_irqrestore(&s->lock, flags);
 581}
 582
 583static unsigned int sccnxp_get_mctrl(struct uart_port *port)
 584{
 585        u8 bitmask, ipr;
 586        unsigned long flags;
 587        struct sccnxp_port *s = dev_get_drvdata(port->dev);
 588        unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
 589
 590        if (!(s->chip->flags & SCCNXP_HAVE_IO))
 591                return mctrl;
 592
 593        spin_lock_irqsave(&s->lock, flags);
 594
 595        ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG);
 596
 597        if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) {
 598                bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
 599                                          DSR_IP);
 600                mctrl &= ~TIOCM_DSR;
 601                mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0;
 602        }
 603        if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) {
 604                bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
 605                                          CTS_IP);
 606                mctrl &= ~TIOCM_CTS;
 607                mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0;
 608        }
 609        if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) {
 610                bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
 611                                          DCD_IP);
 612                mctrl &= ~TIOCM_CAR;
 613                mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0;
 614        }
 615        if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) {
 616                bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
 617                                          RNG_IP);
 618                mctrl &= ~TIOCM_RNG;
 619                mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0;
 620        }
 621
 622        spin_unlock_irqrestore(&s->lock, flags);
 623
 624        return mctrl;
 625}
 626
 627static void sccnxp_break_ctl(struct uart_port *port, int break_state)
 628{
 629        struct sccnxp_port *s = dev_get_drvdata(port->dev);
 630        unsigned long flags;
 631
 632        spin_lock_irqsave(&s->lock, flags);
 633        sccnxp_port_write(port, SCCNXP_CR_REG, break_state ?
 634                          CR_CMD_START_BREAK : CR_CMD_STOP_BREAK);
 635        spin_unlock_irqrestore(&s->lock, flags);
 636}
 637
 638static void sccnxp_set_termios(struct uart_port *port,
 639                               struct ktermios *termios, struct ktermios *old)
 640{
 641        struct sccnxp_port *s = dev_get_drvdata(port->dev);
 642        unsigned long flags;
 643        u8 mr1, mr2;
 644        int baud;
 645
 646        spin_lock_irqsave(&s->lock, flags);
 647
 648        /* Mask termios capabilities we don't support */
 649        termios->c_cflag &= ~CMSPAR;
 650
 651        /* Disable RX & TX, reset break condition, status and FIFOs */
 652        sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET |
 653                                               CR_RX_DISABLE | CR_TX_DISABLE);
 654        sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
 655        sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
 656        sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
 657
 658        /* Word size */
 659        switch (termios->c_cflag & CSIZE) {
 660        case CS5:
 661                mr1 = MR1_BITS_5;
 662                break;
 663        case CS6:
 664                mr1 = MR1_BITS_6;
 665                break;
 666        case CS7:
 667                mr1 = MR1_BITS_7;
 668                break;
 669        case CS8:
 670        default:
 671                mr1 = MR1_BITS_8;
 672                break;
 673        }
 674
 675        /* Parity */
 676        if (termios->c_cflag & PARENB) {
 677                if (termios->c_cflag & PARODD)
 678                        mr1 |= MR1_PAR_ODD;
 679        } else
 680                mr1 |= MR1_PAR_NO;
 681
 682        /* Stop bits */
 683        mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1;
 684
 685        /* Update desired format */
 686        sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1);
 687        sccnxp_port_write(port, SCCNXP_MR_REG, mr1);
 688        sccnxp_port_write(port, SCCNXP_MR_REG, mr2);
 689
 690        /* Set read status mask */
 691        port->read_status_mask = SR_OVR;
 692        if (termios->c_iflag & INPCK)
 693                port->read_status_mask |= SR_PE | SR_FE;
 694        if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
 695                port->read_status_mask |= SR_BRK;
 696
 697        /* Set status ignore mask */
 698        port->ignore_status_mask = 0;
 699        if (termios->c_iflag & IGNBRK)
 700                port->ignore_status_mask |= SR_BRK;
 701        if (termios->c_iflag & IGNPAR)
 702                port->ignore_status_mask |= SR_PE;
 703        if (!(termios->c_cflag & CREAD))
 704                port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK;
 705
 706        /* Setup baudrate */
 707        baud = uart_get_baud_rate(port, termios, old, 50,
 708                                  (s->chip->flags & SCCNXP_HAVE_MR0) ?
 709                                  230400 : 38400);
 710        baud = sccnxp_set_baud(port, baud);
 711
 712        /* Update timeout according to new baud rate */
 713        uart_update_timeout(port, termios->c_cflag, baud);
 714
 715        /* Report actual baudrate back to core */
 716        if (tty_termios_baud_rate(termios))
 717                tty_termios_encode_baud_rate(termios, baud, baud);
 718
 719        /* Enable RX & TX */
 720        sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
 721
 722        spin_unlock_irqrestore(&s->lock, flags);
 723}
 724
 725static int sccnxp_startup(struct uart_port *port)
 726{
 727        struct sccnxp_port *s = dev_get_drvdata(port->dev);
 728        unsigned long flags;
 729
 730        spin_lock_irqsave(&s->lock, flags);
 731
 732        if (s->chip->flags & SCCNXP_HAVE_IO) {
 733                /* Outputs are controlled manually */
 734                sccnxp_write(port, SCCNXP_OPCR_REG, 0);
 735        }
 736
 737        /* Reset break condition, status and FIFOs */
 738        sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET);
 739        sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
 740        sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
 741        sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
 742
 743        /* Enable RX & TX */
 744        sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
 745
 746        /* Enable RX interrupt */
 747        sccnxp_enable_irq(port, IMR_RXRDY);
 748
 749        s->opened[port->line] = 1;
 750
 751        spin_unlock_irqrestore(&s->lock, flags);
 752
 753        return 0;
 754}
 755
 756static void sccnxp_shutdown(struct uart_port *port)
 757{
 758        struct sccnxp_port *s = dev_get_drvdata(port->dev);
 759        unsigned long flags;
 760
 761        spin_lock_irqsave(&s->lock, flags);
 762
 763        s->opened[port->line] = 0;
 764
 765        /* Disable interrupts */
 766        sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
 767
 768        /* Disable TX & RX */
 769        sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE);
 770
 771        /* Leave direction to input */
 772        if (s->chip->flags & SCCNXP_HAVE_IO)
 773                sccnxp_set_bit(port, DIR_OP, 0);
 774
 775        spin_unlock_irqrestore(&s->lock, flags);
 776}
 777
 778static const char *sccnxp_type(struct uart_port *port)
 779{
 780        struct sccnxp_port *s = dev_get_drvdata(port->dev);
 781
 782        return (port->type == PORT_SC26XX) ? s->chip->name : NULL;
 783}
 784
 785static void sccnxp_release_port(struct uart_port *port)
 786{
 787        /* Do nothing */
 788}
 789
 790static int sccnxp_request_port(struct uart_port *port)
 791{
 792        /* Do nothing */
 793        return 0;
 794}
 795
 796static void sccnxp_config_port(struct uart_port *port, int flags)
 797{
 798        if (flags & UART_CONFIG_TYPE)
 799                port->type = PORT_SC26XX;
 800}
 801
 802static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s)
 803{
 804        if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX))
 805                return 0;
 806        if (s->irq == port->irq)
 807                return 0;
 808
 809        return -EINVAL;
 810}
 811
 812static const struct uart_ops sccnxp_ops = {
 813        .tx_empty       = sccnxp_tx_empty,
 814        .set_mctrl      = sccnxp_set_mctrl,
 815        .get_mctrl      = sccnxp_get_mctrl,
 816        .stop_tx        = sccnxp_stop_tx,
 817        .start_tx       = sccnxp_start_tx,
 818        .stop_rx        = sccnxp_stop_rx,
 819        .break_ctl      = sccnxp_break_ctl,
 820        .startup        = sccnxp_startup,
 821        .shutdown       = sccnxp_shutdown,
 822        .set_termios    = sccnxp_set_termios,
 823        .type           = sccnxp_type,
 824        .release_port   = sccnxp_release_port,
 825        .request_port   = sccnxp_request_port,
 826        .config_port    = sccnxp_config_port,
 827        .verify_port    = sccnxp_verify_port,
 828};
 829
 830#ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
 831static void sccnxp_console_putchar(struct uart_port *port, int c)
 832{
 833        int tryes = 100000;
 834
 835        while (tryes--) {
 836                if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) {
 837                        sccnxp_port_write(port, SCCNXP_THR_REG, c);
 838                        break;
 839                }
 840                barrier();
 841        }
 842}
 843
 844static void sccnxp_console_write(struct console *co, const char *c, unsigned n)
 845{
 846        struct sccnxp_port *s = (struct sccnxp_port *)co->data;
 847        struct uart_port *port = &s->port[co->index];
 848        unsigned long flags;
 849
 850        spin_lock_irqsave(&s->lock, flags);
 851        uart_console_write(port, c, n, sccnxp_console_putchar);
 852        spin_unlock_irqrestore(&s->lock, flags);
 853}
 854
 855static int sccnxp_console_setup(struct console *co, char *options)
 856{
 857        struct sccnxp_port *s = (struct sccnxp_port *)co->data;
 858        struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0];
 859        int baud = 9600, bits = 8, parity = 'n', flow = 'n';
 860
 861        if (options)
 862                uart_parse_options(options, &baud, &parity, &bits, &flow);
 863
 864        return uart_set_options(port, co, baud, parity, bits, flow);
 865}
 866#endif
 867
 868static const struct platform_device_id sccnxp_id_table[] = {
 869        { .name = "sc2681",     .driver_data = (kernel_ulong_t)&sc2681, },
 870        { .name = "sc2691",     .driver_data = (kernel_ulong_t)&sc2691, },
 871        { .name = "sc2692",     .driver_data = (kernel_ulong_t)&sc2692, },
 872        { .name = "sc2891",     .driver_data = (kernel_ulong_t)&sc2891, },
 873        { .name = "sc2892",     .driver_data = (kernel_ulong_t)&sc2892, },
 874        { .name = "sc28202",    .driver_data = (kernel_ulong_t)&sc28202, },
 875        { .name = "sc68681",    .driver_data = (kernel_ulong_t)&sc68681, },
 876        { .name = "sc68692",    .driver_data = (kernel_ulong_t)&sc68692, },
 877        { }
 878};
 879MODULE_DEVICE_TABLE(platform, sccnxp_id_table);
 880
 881static int sccnxp_probe(struct platform_device *pdev)
 882{
 883        struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 884        struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev);
 885        int i, ret, uartclk;
 886        struct sccnxp_port *s;
 887        void __iomem *membase;
 888        struct clk *clk;
 889
 890        membase = devm_ioremap_resource(&pdev->dev, res);
 891        if (IS_ERR(membase))
 892                return PTR_ERR(membase);
 893
 894        s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL);
 895        if (!s) {
 896                dev_err(&pdev->dev, "Error allocating port structure\n");
 897                return -ENOMEM;
 898        }
 899        platform_set_drvdata(pdev, s);
 900
 901        spin_lock_init(&s->lock);
 902
 903        s->chip = (struct sccnxp_chip *)pdev->id_entry->driver_data;
 904
 905        s->regulator = devm_regulator_get(&pdev->dev, "vcc");
 906        if (!IS_ERR(s->regulator)) {
 907                ret = regulator_enable(s->regulator);
 908                if (ret) {
 909                        dev_err(&pdev->dev,
 910                                "Failed to enable regulator: %i\n", ret);
 911                        return ret;
 912                }
 913        } else if (PTR_ERR(s->regulator) == -EPROBE_DEFER)
 914                return -EPROBE_DEFER;
 915
 916        clk = devm_clk_get(&pdev->dev, NULL);
 917        if (IS_ERR(clk)) {
 918                ret = PTR_ERR(clk);
 919                if (ret == -EPROBE_DEFER)
 920                        goto err_out;
 921                uartclk = 0;
 922        } else {
 923                ret = clk_prepare_enable(clk);
 924                if (ret)
 925                        goto err_out;
 926
 927                ret = devm_add_action_or_reset(&pdev->dev,
 928                                (void(*)(void *))clk_disable_unprepare,
 929                                clk);
 930                if (ret)
 931                        goto err_out;
 932
 933                uartclk = clk_get_rate(clk);
 934        }
 935
 936        if (!uartclk) {
 937                dev_notice(&pdev->dev, "Using default clock frequency\n");
 938                uartclk = s->chip->freq_std;
 939        }
 940
 941        /* Check input frequency */
 942        if ((uartclk < s->chip->freq_min) || (uartclk > s->chip->freq_max)) {
 943                dev_err(&pdev->dev, "Frequency out of bounds\n");
 944                ret = -EINVAL;
 945                goto err_out;
 946        }
 947
 948        if (pdata)
 949                memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata));
 950
 951        if (s->pdata.poll_time_us) {
 952                dev_info(&pdev->dev, "Using poll mode, resolution %u usecs\n",
 953                         s->pdata.poll_time_us);
 954                s->poll = 1;
 955        }
 956
 957        if (!s->poll) {
 958                s->irq = platform_get_irq(pdev, 0);
 959                if (s->irq < 0) {
 960                        ret = -ENXIO;
 961                        goto err_out;
 962                }
 963        }
 964
 965        s->uart.owner           = THIS_MODULE;
 966        s->uart.dev_name        = "ttySC";
 967        s->uart.major           = SCCNXP_MAJOR;
 968        s->uart.minor           = SCCNXP_MINOR;
 969        s->uart.nr              = s->chip->nr;
 970#ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
 971        s->uart.cons            = &s->console;
 972        s->uart.cons->device    = uart_console_device;
 973        s->uart.cons->write     = sccnxp_console_write;
 974        s->uart.cons->setup     = sccnxp_console_setup;
 975        s->uart.cons->flags     = CON_PRINTBUFFER;
 976        s->uart.cons->index     = -1;
 977        s->uart.cons->data      = s;
 978        strcpy(s->uart.cons->name, "ttySC");
 979#endif
 980        ret = uart_register_driver(&s->uart);
 981        if (ret) {
 982                dev_err(&pdev->dev, "Registering UART driver failed\n");
 983                goto err_out;
 984        }
 985
 986        for (i = 0; i < s->uart.nr; i++) {
 987                s->port[i].line         = i;
 988                s->port[i].dev          = &pdev->dev;
 989                s->port[i].irq          = s->irq;
 990                s->port[i].type         = PORT_SC26XX;
 991                s->port[i].fifosize     = s->chip->fifosize;
 992                s->port[i].flags        = UPF_SKIP_TEST | UPF_FIXED_TYPE;
 993                s->port[i].iotype       = UPIO_MEM;
 994                s->port[i].mapbase      = res->start;
 995                s->port[i].membase      = membase;
 996                s->port[i].regshift     = s->pdata.reg_shift;
 997                s->port[i].uartclk      = uartclk;
 998                s->port[i].ops          = &sccnxp_ops;
 999                s->port[i].has_sysrq = IS_ENABLED(CONFIG_SERIAL_SCCNXP_CONSOLE);
1000                uart_add_one_port(&s->uart, &s->port[i]);
1001                /* Set direction to input */
1002                if (s->chip->flags & SCCNXP_HAVE_IO)
1003                        sccnxp_set_bit(&s->port[i], DIR_OP, 0);
1004        }
1005
1006        /* Disable interrupts */
1007        s->imr = 0;
1008        sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0);
1009
1010        if (!s->poll) {
1011                ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL,
1012                                                sccnxp_ist,
1013                                                IRQF_TRIGGER_FALLING |
1014                                                IRQF_ONESHOT,
1015                                                dev_name(&pdev->dev), s);
1016                if (!ret)
1017                        return 0;
1018
1019                dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq);
1020        } else {
1021                timer_setup(&s->timer, sccnxp_timer, 0);
1022                mod_timer(&s->timer, jiffies +
1023                          usecs_to_jiffies(s->pdata.poll_time_us));
1024                return 0;
1025        }
1026
1027        uart_unregister_driver(&s->uart);
1028err_out:
1029        if (!IS_ERR(s->regulator))
1030                regulator_disable(s->regulator);
1031
1032        return ret;
1033}
1034
1035static int sccnxp_remove(struct platform_device *pdev)
1036{
1037        int i;
1038        struct sccnxp_port *s = platform_get_drvdata(pdev);
1039
1040        if (!s->poll)
1041                devm_free_irq(&pdev->dev, s->irq, s);
1042        else
1043                del_timer_sync(&s->timer);
1044
1045        for (i = 0; i < s->uart.nr; i++)
1046                uart_remove_one_port(&s->uart, &s->port[i]);
1047
1048        uart_unregister_driver(&s->uart);
1049
1050        if (!IS_ERR(s->regulator))
1051                return regulator_disable(s->regulator);
1052
1053        return 0;
1054}
1055
1056static struct platform_driver sccnxp_uart_driver = {
1057        .driver = {
1058                .name   = SCCNXP_NAME,
1059        },
1060        .probe          = sccnxp_probe,
1061        .remove         = sccnxp_remove,
1062        .id_table       = sccnxp_id_table,
1063};
1064module_platform_driver(sccnxp_uart_driver);
1065
1066MODULE_LICENSE("GPL v2");
1067MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1068MODULE_DESCRIPTION("SCCNXP serial driver");
1069