linux/drivers/tty/serial/qcom_geni_serial.c
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   1// SPDX-License-Identifier: GPL-2.0
   2// Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
   3
   4#include <linux/clk.h>
   5#include <linux/console.h>
   6#include <linux/io.h>
   7#include <linux/iopoll.h>
   8#include <linux/irq.h>
   9#include <linux/module.h>
  10#include <linux/of.h>
  11#include <linux/of_device.h>
  12#include <linux/pm_opp.h>
  13#include <linux/platform_device.h>
  14#include <linux/pm_runtime.h>
  15#include <linux/pm_wakeirq.h>
  16#include <linux/qcom-geni-se.h>
  17#include <linux/serial.h>
  18#include <linux/serial_core.h>
  19#include <linux/slab.h>
  20#include <linux/tty.h>
  21#include <linux/tty_flip.h>
  22
  23/* UART specific GENI registers */
  24#define SE_UART_LOOPBACK_CFG            0x22c
  25#define SE_UART_IO_MACRO_CTRL           0x240
  26#define SE_UART_TX_TRANS_CFG            0x25c
  27#define SE_UART_TX_WORD_LEN             0x268
  28#define SE_UART_TX_STOP_BIT_LEN         0x26c
  29#define SE_UART_TX_TRANS_LEN            0x270
  30#define SE_UART_RX_TRANS_CFG            0x280
  31#define SE_UART_RX_WORD_LEN             0x28c
  32#define SE_UART_RX_STALE_CNT            0x294
  33#define SE_UART_TX_PARITY_CFG           0x2a4
  34#define SE_UART_RX_PARITY_CFG           0x2a8
  35#define SE_UART_MANUAL_RFR              0x2ac
  36
  37/* SE_UART_TRANS_CFG */
  38#define UART_TX_PAR_EN          BIT(0)
  39#define UART_CTS_MASK           BIT(1)
  40
  41/* SE_UART_TX_WORD_LEN */
  42#define TX_WORD_LEN_MSK         GENMASK(9, 0)
  43
  44/* SE_UART_TX_STOP_BIT_LEN */
  45#define TX_STOP_BIT_LEN_MSK     GENMASK(23, 0)
  46#define TX_STOP_BIT_LEN_1       0
  47#define TX_STOP_BIT_LEN_1_5     1
  48#define TX_STOP_BIT_LEN_2       2
  49
  50/* SE_UART_TX_TRANS_LEN */
  51#define TX_TRANS_LEN_MSK        GENMASK(23, 0)
  52
  53/* SE_UART_RX_TRANS_CFG */
  54#define UART_RX_INS_STATUS_BIT  BIT(2)
  55#define UART_RX_PAR_EN          BIT(3)
  56
  57/* SE_UART_RX_WORD_LEN */
  58#define RX_WORD_LEN_MASK        GENMASK(9, 0)
  59
  60/* SE_UART_RX_STALE_CNT */
  61#define RX_STALE_CNT            GENMASK(23, 0)
  62
  63/* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
  64#define PAR_CALC_EN             BIT(0)
  65#define PAR_MODE_MSK            GENMASK(2, 1)
  66#define PAR_MODE_SHFT           1
  67#define PAR_EVEN                0x00
  68#define PAR_ODD                 0x01
  69#define PAR_SPACE               0x10
  70#define PAR_MARK                0x11
  71
  72/* SE_UART_MANUAL_RFR register fields */
  73#define UART_MANUAL_RFR_EN      BIT(31)
  74#define UART_RFR_NOT_READY      BIT(1)
  75#define UART_RFR_READY          BIT(0)
  76
  77/* UART M_CMD OP codes */
  78#define UART_START_TX           0x1
  79#define UART_START_BREAK        0x4
  80#define UART_STOP_BREAK         0x5
  81/* UART S_CMD OP codes */
  82#define UART_START_READ         0x1
  83#define UART_PARAM              0x1
  84
  85#define UART_OVERSAMPLING       32
  86#define STALE_TIMEOUT           16
  87#define DEFAULT_BITS_PER_CHAR   10
  88#define GENI_UART_CONS_PORTS    1
  89#define GENI_UART_PORTS         3
  90#define DEF_FIFO_DEPTH_WORDS    16
  91#define DEF_TX_WM               2
  92#define DEF_FIFO_WIDTH_BITS     32
  93#define UART_RX_WM              2
  94
  95/* SE_UART_LOOPBACK_CFG */
  96#define RX_TX_SORTED    BIT(0)
  97#define CTS_RTS_SORTED  BIT(1)
  98#define RX_TX_CTS_RTS_SORTED    (RX_TX_SORTED | CTS_RTS_SORTED)
  99
 100/* UART pin swap value */
 101#define DEFAULT_IO_MACRO_IO0_IO1_MASK           GENMASK(3, 0)
 102#define IO_MACRO_IO0_SEL                0x3
 103#define DEFAULT_IO_MACRO_IO2_IO3_MASK           GENMASK(15, 4)
 104#define IO_MACRO_IO2_IO3_SWAP           0x4640
 105
 106/* We always configure 4 bytes per FIFO word */
 107#define BYTES_PER_FIFO_WORD             4
 108
 109struct qcom_geni_private_data {
 110        /* NOTE: earlycon port will have NULL here */
 111        struct uart_driver *drv;
 112
 113        u32 poll_cached_bytes;
 114        unsigned int poll_cached_bytes_cnt;
 115
 116        u32 write_cached_bytes;
 117        unsigned int write_cached_bytes_cnt;
 118};
 119
 120struct qcom_geni_serial_port {
 121        struct uart_port uport;
 122        struct geni_se se;
 123        const char *name;
 124        u32 tx_fifo_depth;
 125        u32 tx_fifo_width;
 126        u32 rx_fifo_depth;
 127        bool setup;
 128        int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
 129        unsigned int baud;
 130        void *rx_fifo;
 131        u32 loopback;
 132        bool brk;
 133
 134        unsigned int tx_remaining;
 135        int wakeup_irq;
 136        bool rx_tx_swap;
 137        bool cts_rts_swap;
 138
 139        struct qcom_geni_private_data private_data;
 140};
 141
 142static const struct uart_ops qcom_geni_console_pops;
 143static const struct uart_ops qcom_geni_uart_pops;
 144static struct uart_driver qcom_geni_console_driver;
 145static struct uart_driver qcom_geni_uart_driver;
 146static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
 147static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop);
 148static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
 149static void qcom_geni_serial_stop_rx(struct uart_port *uport);
 150static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop);
 151
 152static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
 153                                        32000000, 48000000, 51200000, 64000000,
 154                                        80000000, 96000000, 100000000,
 155                                        102400000, 112000000, 120000000,
 156                                        128000000};
 157
 158#define to_dev_port(ptr, member) \
 159                container_of(ptr, struct qcom_geni_serial_port, member)
 160
 161static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = {
 162        [0] = {
 163                .uport = {
 164                                .iotype = UPIO_MEM,
 165                                .ops = &qcom_geni_uart_pops,
 166                                .flags = UPF_BOOT_AUTOCONF,
 167                                .line = 0,
 168                },
 169        },
 170        [1] = {
 171                .uport = {
 172                                .iotype = UPIO_MEM,
 173                                .ops = &qcom_geni_uart_pops,
 174                                .flags = UPF_BOOT_AUTOCONF,
 175                                .line = 1,
 176                },
 177        },
 178        [2] = {
 179                .uport = {
 180                                .iotype = UPIO_MEM,
 181                                .ops = &qcom_geni_uart_pops,
 182                                .flags = UPF_BOOT_AUTOCONF,
 183                                .line = 2,
 184                },
 185        },
 186};
 187
 188static struct qcom_geni_serial_port qcom_geni_console_port = {
 189        .uport = {
 190                .iotype = UPIO_MEM,
 191                .ops = &qcom_geni_console_pops,
 192                .flags = UPF_BOOT_AUTOCONF,
 193                .line = 0,
 194        },
 195};
 196
 197static int qcom_geni_serial_request_port(struct uart_port *uport)
 198{
 199        struct platform_device *pdev = to_platform_device(uport->dev);
 200        struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 201
 202        uport->membase = devm_platform_ioremap_resource(pdev, 0);
 203        if (IS_ERR(uport->membase))
 204                return PTR_ERR(uport->membase);
 205        port->se.base = uport->membase;
 206        return 0;
 207}
 208
 209static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
 210{
 211        if (cfg_flags & UART_CONFIG_TYPE) {
 212                uport->type = PORT_MSM;
 213                qcom_geni_serial_request_port(uport);
 214        }
 215}
 216
 217static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
 218{
 219        unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
 220        u32 geni_ios;
 221
 222        if (uart_console(uport)) {
 223                mctrl |= TIOCM_CTS;
 224        } else {
 225                geni_ios = readl(uport->membase + SE_GENI_IOS);
 226                if (!(geni_ios & IO2_DATA_IN))
 227                        mctrl |= TIOCM_CTS;
 228        }
 229
 230        return mctrl;
 231}
 232
 233static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
 234                                                        unsigned int mctrl)
 235{
 236        u32 uart_manual_rfr = 0;
 237        struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 238
 239        if (uart_console(uport))
 240                return;
 241
 242        if (mctrl & TIOCM_LOOP)
 243                port->loopback = RX_TX_CTS_RTS_SORTED;
 244
 245        if (!(mctrl & TIOCM_RTS) && !uport->suspended)
 246                uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY;
 247        writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
 248}
 249
 250static const char *qcom_geni_serial_get_type(struct uart_port *uport)
 251{
 252        return "MSM";
 253}
 254
 255static struct qcom_geni_serial_port *get_port_from_line(int line, bool console)
 256{
 257        struct qcom_geni_serial_port *port;
 258        int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS;
 259
 260        if (line < 0 || line >= nr_ports)
 261                return ERR_PTR(-ENXIO);
 262
 263        port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line];
 264        return port;
 265}
 266
 267static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
 268                                int offset, int field, bool set)
 269{
 270        u32 reg;
 271        struct qcom_geni_serial_port *port;
 272        unsigned int baud;
 273        unsigned int fifo_bits;
 274        unsigned long timeout_us = 20000;
 275        struct qcom_geni_private_data *private_data = uport->private_data;
 276
 277        if (private_data->drv) {
 278                port = to_dev_port(uport, uport);
 279                baud = port->baud;
 280                if (!baud)
 281                        baud = 115200;
 282                fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
 283                /*
 284                 * Total polling iterations based on FIFO worth of bytes to be
 285                 * sent at current baud. Add a little fluff to the wait.
 286                 */
 287                timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
 288        }
 289
 290        /*
 291         * Use custom implementation instead of readl_poll_atomic since ktimer
 292         * is not ready at the time of early console.
 293         */
 294        timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
 295        while (timeout_us) {
 296                reg = readl(uport->membase + offset);
 297                if ((bool)(reg & field) == set)
 298                        return true;
 299                udelay(10);
 300                timeout_us -= 10;
 301        }
 302        return false;
 303}
 304
 305static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
 306{
 307        u32 m_cmd;
 308
 309        writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
 310        m_cmd = UART_START_TX << M_OPCODE_SHFT;
 311        writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
 312}
 313
 314static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
 315{
 316        int done;
 317        u32 irq_clear = M_CMD_DONE_EN;
 318
 319        done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 320                                                M_CMD_DONE_EN, true);
 321        if (!done) {
 322                writel(M_GENI_CMD_ABORT, uport->membase +
 323                                                SE_GENI_M_CMD_CTRL_REG);
 324                irq_clear |= M_CMD_ABORT_EN;
 325                qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 326                                                        M_CMD_ABORT_EN, true);
 327        }
 328        writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
 329}
 330
 331static void qcom_geni_serial_abort_rx(struct uart_port *uport)
 332{
 333        u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
 334
 335        writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
 336        qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
 337                                        S_GENI_CMD_ABORT, false);
 338        writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
 339        writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
 340}
 341
 342#ifdef CONFIG_CONSOLE_POLL
 343
 344static int qcom_geni_serial_get_char(struct uart_port *uport)
 345{
 346        struct qcom_geni_private_data *private_data = uport->private_data;
 347        u32 status;
 348        u32 word_cnt;
 349        int ret;
 350
 351        if (!private_data->poll_cached_bytes_cnt) {
 352                status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
 353                writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
 354
 355                status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
 356                writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
 357
 358                status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
 359                word_cnt = status & RX_FIFO_WC_MSK;
 360                if (!word_cnt)
 361                        return NO_POLL_CHAR;
 362
 363                if (word_cnt == 1 && (status & RX_LAST))
 364                        /*
 365                         * NOTE: If RX_LAST_BYTE_VALID is 0 it needs to be
 366                         * treated as if it was BYTES_PER_FIFO_WORD.
 367                         */
 368                        private_data->poll_cached_bytes_cnt =
 369                                (status & RX_LAST_BYTE_VALID_MSK) >>
 370                                RX_LAST_BYTE_VALID_SHFT;
 371
 372                if (private_data->poll_cached_bytes_cnt == 0)
 373                        private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD;
 374
 375                private_data->poll_cached_bytes =
 376                        readl(uport->membase + SE_GENI_RX_FIFOn);
 377        }
 378
 379        private_data->poll_cached_bytes_cnt--;
 380        ret = private_data->poll_cached_bytes & 0xff;
 381        private_data->poll_cached_bytes >>= 8;
 382
 383        return ret;
 384}
 385
 386static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
 387                                                        unsigned char c)
 388{
 389        writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
 390        qcom_geni_serial_setup_tx(uport, 1);
 391        WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 392                                                M_TX_FIFO_WATERMARK_EN, true));
 393        writel(c, uport->membase + SE_GENI_TX_FIFOn);
 394        writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 395        qcom_geni_serial_poll_tx_done(uport);
 396}
 397#endif
 398
 399#ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
 400static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch)
 401{
 402        struct qcom_geni_private_data *private_data = uport->private_data;
 403
 404        private_data->write_cached_bytes =
 405                (private_data->write_cached_bytes >> 8) | (ch << 24);
 406        private_data->write_cached_bytes_cnt++;
 407
 408        if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) {
 409                writel(private_data->write_cached_bytes,
 410                       uport->membase + SE_GENI_TX_FIFOn);
 411                private_data->write_cached_bytes_cnt = 0;
 412        }
 413}
 414
 415static void
 416__qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
 417                                 unsigned int count)
 418{
 419        struct qcom_geni_private_data *private_data = uport->private_data;
 420
 421        int i;
 422        u32 bytes_to_send = count;
 423
 424        for (i = 0; i < count; i++) {
 425                /*
 426                 * uart_console_write() adds a carriage return for each newline.
 427                 * Account for additional bytes to be written.
 428                 */
 429                if (s[i] == '\n')
 430                        bytes_to_send++;
 431        }
 432
 433        writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
 434        qcom_geni_serial_setup_tx(uport, bytes_to_send);
 435        for (i = 0; i < count; ) {
 436                size_t chars_to_write = 0;
 437                size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
 438
 439                /*
 440                 * If the WM bit never set, then the Tx state machine is not
 441                 * in a valid state, so break, cancel/abort any existing
 442                 * command. Unfortunately the current data being written is
 443                 * lost.
 444                 */
 445                if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 446                                                M_TX_FIFO_WATERMARK_EN, true))
 447                        break;
 448                chars_to_write = min_t(size_t, count - i, avail / 2);
 449                uart_console_write(uport, s + i, chars_to_write,
 450                                                qcom_geni_serial_wr_char);
 451                writel(M_TX_FIFO_WATERMARK_EN, uport->membase +
 452                                                        SE_GENI_M_IRQ_CLEAR);
 453                i += chars_to_write;
 454        }
 455
 456        if (private_data->write_cached_bytes_cnt) {
 457                private_data->write_cached_bytes >>= BITS_PER_BYTE *
 458                        (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt);
 459                writel(private_data->write_cached_bytes,
 460                       uport->membase + SE_GENI_TX_FIFOn);
 461                private_data->write_cached_bytes_cnt = 0;
 462        }
 463
 464        qcom_geni_serial_poll_tx_done(uport);
 465}
 466
 467static void qcom_geni_serial_console_write(struct console *co, const char *s,
 468                              unsigned int count)
 469{
 470        struct uart_port *uport;
 471        struct qcom_geni_serial_port *port;
 472        bool locked = true;
 473        unsigned long flags;
 474        u32 geni_status;
 475        u32 irq_en;
 476
 477        WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
 478
 479        port = get_port_from_line(co->index, true);
 480        if (IS_ERR(port))
 481                return;
 482
 483        uport = &port->uport;
 484        if (oops_in_progress)
 485                locked = spin_trylock_irqsave(&uport->lock, flags);
 486        else
 487                spin_lock_irqsave(&uport->lock, flags);
 488
 489        geni_status = readl(uport->membase + SE_GENI_STATUS);
 490
 491        /* Cancel the current write to log the fault */
 492        if (!locked) {
 493                geni_se_cancel_m_cmd(&port->se);
 494                if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 495                                                M_CMD_CANCEL_EN, true)) {
 496                        geni_se_abort_m_cmd(&port->se);
 497                        qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 498                                                        M_CMD_ABORT_EN, true);
 499                        writel(M_CMD_ABORT_EN, uport->membase +
 500                                                        SE_GENI_M_IRQ_CLEAR);
 501                }
 502                writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 503        } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) {
 504                /*
 505                 * It seems we can't interrupt existing transfers if all data
 506                 * has been sent, in which case we need to look for done first.
 507                 */
 508                qcom_geni_serial_poll_tx_done(uport);
 509
 510                if (uart_circ_chars_pending(&uport->state->xmit)) {
 511                        irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 512                        writel(irq_en | M_TX_FIFO_WATERMARK_EN,
 513                                        uport->membase + SE_GENI_M_IRQ_EN);
 514                }
 515        }
 516
 517        __qcom_geni_serial_console_write(uport, s, count);
 518
 519        if (port->tx_remaining)
 520                qcom_geni_serial_setup_tx(uport, port->tx_remaining);
 521
 522        if (locked)
 523                spin_unlock_irqrestore(&uport->lock, flags);
 524}
 525
 526static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
 527{
 528        u32 i;
 529        unsigned char buf[sizeof(u32)];
 530        struct tty_port *tport;
 531        struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 532
 533        tport = &uport->state->port;
 534        for (i = 0; i < bytes; ) {
 535                int c;
 536                int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD);
 537
 538                ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
 539                i += chunk;
 540                if (drop)
 541                        continue;
 542
 543                for (c = 0; c < chunk; c++) {
 544                        int sysrq;
 545
 546                        uport->icount.rx++;
 547                        if (port->brk && buf[c] == 0) {
 548                                port->brk = false;
 549                                if (uart_handle_break(uport))
 550                                        continue;
 551                        }
 552
 553                        sysrq = uart_prepare_sysrq_char(uport, buf[c]);
 554
 555                        if (!sysrq)
 556                                tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
 557                }
 558        }
 559        if (!drop)
 560                tty_flip_buffer_push(tport);
 561        return 0;
 562}
 563#else
 564static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
 565{
 566        return -EPERM;
 567}
 568
 569#endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
 570
 571static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
 572{
 573        struct tty_port *tport;
 574        struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 575        u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE;
 576        u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw;
 577        int ret;
 578
 579        tport = &uport->state->port;
 580        ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words);
 581        if (drop)
 582                return 0;
 583
 584        ret = tty_insert_flip_string(tport, port->rx_fifo, bytes);
 585        if (ret != bytes) {
 586                dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
 587                                __func__, ret, bytes);
 588                WARN_ON_ONCE(1);
 589        }
 590        uport->icount.rx += ret;
 591        tty_flip_buffer_push(tport);
 592        return ret;
 593}
 594
 595static void qcom_geni_serial_start_tx(struct uart_port *uport)
 596{
 597        u32 irq_en;
 598        u32 status;
 599
 600        status = readl(uport->membase + SE_GENI_STATUS);
 601        if (status & M_GENI_CMD_ACTIVE)
 602                return;
 603
 604        if (!qcom_geni_serial_tx_empty(uport))
 605                return;
 606
 607        irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 608        irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
 609
 610        writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
 611        writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 612}
 613
 614static void qcom_geni_serial_stop_tx(struct uart_port *uport)
 615{
 616        u32 irq_en;
 617        u32 status;
 618        struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 619
 620        irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 621        irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
 622        writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
 623        writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 624        status = readl(uport->membase + SE_GENI_STATUS);
 625        /* Possible stop tx is called multiple times. */
 626        if (!(status & M_GENI_CMD_ACTIVE))
 627                return;
 628
 629        geni_se_cancel_m_cmd(&port->se);
 630        if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 631                                                M_CMD_CANCEL_EN, true)) {
 632                geni_se_abort_m_cmd(&port->se);
 633                qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 634                                                M_CMD_ABORT_EN, true);
 635                writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 636        }
 637        writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 638}
 639
 640static void qcom_geni_serial_start_rx(struct uart_port *uport)
 641{
 642        u32 irq_en;
 643        u32 status;
 644        struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 645
 646        status = readl(uport->membase + SE_GENI_STATUS);
 647        if (status & S_GENI_CMD_ACTIVE)
 648                qcom_geni_serial_stop_rx(uport);
 649
 650        geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
 651
 652        irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
 653        irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
 654        writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
 655
 656        irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 657        irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
 658        writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 659}
 660
 661static void qcom_geni_serial_stop_rx(struct uart_port *uport)
 662{
 663        u32 irq_en;
 664        u32 status;
 665        struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 666        u32 s_irq_status;
 667
 668        irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
 669        irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
 670        writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
 671
 672        irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 673        irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
 674        writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 675
 676        status = readl(uport->membase + SE_GENI_STATUS);
 677        /* Possible stop rx is called multiple times. */
 678        if (!(status & S_GENI_CMD_ACTIVE))
 679                return;
 680
 681        geni_se_cancel_s_cmd(&port->se);
 682        qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS,
 683                                        S_CMD_CANCEL_EN, true);
 684        /*
 685         * If timeout occurs secondary engine remains active
 686         * and Abort sequence is executed.
 687         */
 688        s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
 689        /* Flush the Rx buffer */
 690        if (s_irq_status & S_RX_FIFO_LAST_EN)
 691                qcom_geni_serial_handle_rx(uport, true);
 692        writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
 693
 694        status = readl(uport->membase + SE_GENI_STATUS);
 695        if (status & S_GENI_CMD_ACTIVE)
 696                qcom_geni_serial_abort_rx(uport);
 697}
 698
 699static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
 700{
 701        u32 status;
 702        u32 word_cnt;
 703        u32 last_word_byte_cnt;
 704        u32 last_word_partial;
 705        u32 total_bytes;
 706        struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 707
 708        status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
 709        word_cnt = status & RX_FIFO_WC_MSK;
 710        last_word_partial = status & RX_LAST;
 711        last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
 712                                                RX_LAST_BYTE_VALID_SHFT;
 713
 714        if (!word_cnt)
 715                return;
 716        total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1);
 717        if (last_word_partial && last_word_byte_cnt)
 718                total_bytes += last_word_byte_cnt;
 719        else
 720                total_bytes += BYTES_PER_FIFO_WORD;
 721        port->handle_rx(uport, total_bytes, drop);
 722}
 723
 724static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done,
 725                bool active)
 726{
 727        struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 728        struct circ_buf *xmit = &uport->state->xmit;
 729        size_t avail;
 730        size_t remaining;
 731        size_t pending;
 732        int i;
 733        u32 status;
 734        u32 irq_en;
 735        unsigned int chunk;
 736        int tail;
 737
 738        status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
 739
 740        /* Complete the current tx command before taking newly added data */
 741        if (active)
 742                pending = port->tx_remaining;
 743        else
 744                pending = uart_circ_chars_pending(xmit);
 745
 746        /* All data has been transmitted and acknowledged as received */
 747        if (!pending && !status && done) {
 748                qcom_geni_serial_stop_tx(uport);
 749                goto out_write_wakeup;
 750        }
 751
 752        avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
 753        avail *= BYTES_PER_FIFO_WORD;
 754
 755        tail = xmit->tail;
 756        chunk = min(avail, pending);
 757        if (!chunk)
 758                goto out_write_wakeup;
 759
 760        if (!port->tx_remaining) {
 761                qcom_geni_serial_setup_tx(uport, pending);
 762                port->tx_remaining = pending;
 763
 764                irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 765                if (!(irq_en & M_TX_FIFO_WATERMARK_EN))
 766                        writel(irq_en | M_TX_FIFO_WATERMARK_EN,
 767                                        uport->membase + SE_GENI_M_IRQ_EN);
 768        }
 769
 770        remaining = chunk;
 771        for (i = 0; i < chunk; ) {
 772                unsigned int tx_bytes;
 773                u8 buf[sizeof(u32)];
 774                int c;
 775
 776                memset(buf, 0, sizeof(buf));
 777                tx_bytes = min_t(size_t, remaining, BYTES_PER_FIFO_WORD);
 778
 779                for (c = 0; c < tx_bytes ; c++) {
 780                        buf[c] = xmit->buf[tail++];
 781                        tail &= UART_XMIT_SIZE - 1;
 782                }
 783
 784                iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
 785
 786                i += tx_bytes;
 787                uport->icount.tx += tx_bytes;
 788                remaining -= tx_bytes;
 789                port->tx_remaining -= tx_bytes;
 790        }
 791
 792        xmit->tail = tail;
 793
 794        /*
 795         * The tx fifo watermark is level triggered and latched. Though we had
 796         * cleared it in qcom_geni_serial_isr it will have already reasserted
 797         * so we must clear it again here after our writes.
 798         */
 799        writel(M_TX_FIFO_WATERMARK_EN,
 800                        uport->membase + SE_GENI_M_IRQ_CLEAR);
 801
 802out_write_wakeup:
 803        if (!port->tx_remaining) {
 804                irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 805                if (irq_en & M_TX_FIFO_WATERMARK_EN)
 806                        writel(irq_en & ~M_TX_FIFO_WATERMARK_EN,
 807                                        uport->membase + SE_GENI_M_IRQ_EN);
 808        }
 809
 810        if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 811                uart_write_wakeup(uport);
 812}
 813
 814static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
 815{
 816        u32 m_irq_en;
 817        u32 m_irq_status;
 818        u32 s_irq_status;
 819        u32 geni_status;
 820        struct uart_port *uport = dev;
 821        bool drop_rx = false;
 822        struct tty_port *tport = &uport->state->port;
 823        struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 824
 825        if (uport->suspended)
 826                return IRQ_NONE;
 827
 828        spin_lock(&uport->lock);
 829
 830        m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
 831        s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
 832        geni_status = readl(uport->membase + SE_GENI_STATUS);
 833        m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 834        writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
 835        writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
 836
 837        if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
 838                goto out_unlock;
 839
 840        if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
 841                uport->icount.overrun++;
 842                tty_insert_flip_char(tport, 0, TTY_OVERRUN);
 843        }
 844
 845        if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
 846                qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN,
 847                                        geni_status & M_GENI_CMD_ACTIVE);
 848
 849        if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
 850                if (s_irq_status & S_GP_IRQ_0_EN)
 851                        uport->icount.parity++;
 852                drop_rx = true;
 853        } else if (s_irq_status & S_GP_IRQ_2_EN ||
 854                                        s_irq_status & S_GP_IRQ_3_EN) {
 855                uport->icount.brk++;
 856                port->brk = true;
 857        }
 858
 859        if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
 860                                        s_irq_status & S_RX_FIFO_LAST_EN)
 861                qcom_geni_serial_handle_rx(uport, drop_rx);
 862
 863out_unlock:
 864        uart_unlock_and_check_sysrq(uport);
 865
 866        return IRQ_HANDLED;
 867}
 868
 869static void get_tx_fifo_size(struct qcom_geni_serial_port *port)
 870{
 871        struct uart_port *uport;
 872
 873        uport = &port->uport;
 874        port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
 875        port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
 876        port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
 877        uport->fifosize =
 878                (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
 879}
 880
 881
 882static void qcom_geni_serial_shutdown(struct uart_port *uport)
 883{
 884        disable_irq(uport->irq);
 885}
 886
 887static int qcom_geni_serial_port_setup(struct uart_port *uport)
 888{
 889        struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 890        u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
 891        u32 proto;
 892        u32 pin_swap;
 893
 894        proto = geni_se_read_proto(&port->se);
 895        if (proto != GENI_SE_UART) {
 896                dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
 897                return -ENXIO;
 898        }
 899
 900        qcom_geni_serial_stop_rx(uport);
 901
 902        get_tx_fifo_size(port);
 903
 904        writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
 905
 906        pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL);
 907        if (port->rx_tx_swap) {
 908                pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK;
 909                pin_swap |= IO_MACRO_IO2_IO3_SWAP;
 910        }
 911        if (port->cts_rts_swap) {
 912                pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK;
 913                pin_swap |= IO_MACRO_IO0_SEL;
 914        }
 915        /* Configure this register if RX-TX, CTS-RTS pins are swapped */
 916        if (port->rx_tx_swap || port->cts_rts_swap)
 917                writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL);
 918
 919        /*
 920         * Make an unconditional cancel on the main sequencer to reset
 921         * it else we could end up in data loss scenarios.
 922         */
 923        if (uart_console(uport))
 924                qcom_geni_serial_poll_tx_done(uport);
 925        geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
 926                               false, true, true);
 927        geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);
 928        geni_se_select_mode(&port->se, GENI_SE_FIFO);
 929        port->setup = true;
 930
 931        return 0;
 932}
 933
 934static int qcom_geni_serial_startup(struct uart_port *uport)
 935{
 936        int ret;
 937        struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 938
 939        if (!port->setup) {
 940                ret = qcom_geni_serial_port_setup(uport);
 941                if (ret)
 942                        return ret;
 943        }
 944        enable_irq(uport->irq);
 945
 946        return 0;
 947}
 948
 949static unsigned long get_clk_cfg(unsigned long clk_freq)
 950{
 951        int i;
 952
 953        for (i = 0; i < ARRAY_SIZE(root_freq); i++) {
 954                if (!(root_freq[i] % clk_freq))
 955                        return root_freq[i];
 956        }
 957        return 0;
 958}
 959
 960static unsigned long get_clk_div_rate(unsigned int baud,
 961                        unsigned int sampling_rate, unsigned int *clk_div)
 962{
 963        unsigned long ser_clk;
 964        unsigned long desired_clk;
 965
 966        desired_clk = baud * sampling_rate;
 967        ser_clk = get_clk_cfg(desired_clk);
 968        if (!ser_clk) {
 969                pr_err("%s: Can't find matching DFS entry for baud %d\n",
 970                                                                __func__, baud);
 971                return ser_clk;
 972        }
 973
 974        *clk_div = ser_clk / desired_clk;
 975        return ser_clk;
 976}
 977
 978static void qcom_geni_serial_set_termios(struct uart_port *uport,
 979                                struct ktermios *termios, struct ktermios *old)
 980{
 981        unsigned int baud;
 982        u32 bits_per_char;
 983        u32 tx_trans_cfg;
 984        u32 tx_parity_cfg;
 985        u32 rx_trans_cfg;
 986        u32 rx_parity_cfg;
 987        u32 stop_bit_len;
 988        unsigned int clk_div;
 989        u32 ser_clk_cfg;
 990        struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 991        unsigned long clk_rate;
 992        u32 ver, sampling_rate;
 993        unsigned int avg_bw_core;
 994
 995        qcom_geni_serial_stop_rx(uport);
 996        /* baud rate */
 997        baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
 998        port->baud = baud;
 999
1000        sampling_rate = UART_OVERSAMPLING;
1001        /* Sampling rate is halved for IP versions >= 2.5 */
1002        ver = geni_se_get_qup_hw_version(&port->se);
1003        if (ver >= QUP_SE_VERSION_2_5)
1004                sampling_rate /= 2;
1005
1006        clk_rate = get_clk_div_rate(baud, sampling_rate, &clk_div);
1007        if (!clk_rate)
1008                goto out_restart_rx;
1009
1010        uport->uartclk = clk_rate;
1011        dev_pm_opp_set_rate(uport->dev, clk_rate);
1012        ser_clk_cfg = SER_CLK_EN;
1013        ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
1014
1015        /*
1016         * Bump up BW vote on CPU and CORE path as driver supports FIFO mode
1017         * only.
1018         */
1019        avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ)
1020                                                : GENI_DEFAULT_BW;
1021        port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core;
1022        port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud);
1023        geni_icc_set_bw(&port->se);
1024
1025        /* parity */
1026        tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
1027        tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
1028        rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG);
1029        rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG);
1030        if (termios->c_cflag & PARENB) {
1031                tx_trans_cfg |= UART_TX_PAR_EN;
1032                rx_trans_cfg |= UART_RX_PAR_EN;
1033                tx_parity_cfg |= PAR_CALC_EN;
1034                rx_parity_cfg |= PAR_CALC_EN;
1035                if (termios->c_cflag & PARODD) {
1036                        tx_parity_cfg |= PAR_ODD;
1037                        rx_parity_cfg |= PAR_ODD;
1038                } else if (termios->c_cflag & CMSPAR) {
1039                        tx_parity_cfg |= PAR_SPACE;
1040                        rx_parity_cfg |= PAR_SPACE;
1041                } else {
1042                        tx_parity_cfg |= PAR_EVEN;
1043                        rx_parity_cfg |= PAR_EVEN;
1044                }
1045        } else {
1046                tx_trans_cfg &= ~UART_TX_PAR_EN;
1047                rx_trans_cfg &= ~UART_RX_PAR_EN;
1048                tx_parity_cfg &= ~PAR_CALC_EN;
1049                rx_parity_cfg &= ~PAR_CALC_EN;
1050        }
1051
1052        /* bits per char */
1053        switch (termios->c_cflag & CSIZE) {
1054        case CS5:
1055                bits_per_char = 5;
1056                break;
1057        case CS6:
1058                bits_per_char = 6;
1059                break;
1060        case CS7:
1061                bits_per_char = 7;
1062                break;
1063        case CS8:
1064        default:
1065                bits_per_char = 8;
1066                break;
1067        }
1068
1069        /* stop bits */
1070        if (termios->c_cflag & CSTOPB)
1071                stop_bit_len = TX_STOP_BIT_LEN_2;
1072        else
1073                stop_bit_len = TX_STOP_BIT_LEN_1;
1074
1075        /* flow control, clear the CTS_MASK bit if using flow control. */
1076        if (termios->c_cflag & CRTSCTS)
1077                tx_trans_cfg &= ~UART_CTS_MASK;
1078        else
1079                tx_trans_cfg |= UART_CTS_MASK;
1080
1081        if (baud)
1082                uart_update_timeout(uport, termios->c_cflag, baud);
1083
1084        if (!uart_console(uport))
1085                writel(port->loopback,
1086                                uport->membase + SE_UART_LOOPBACK_CFG);
1087        writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1088        writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1089        writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1090        writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1091        writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1092        writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1093        writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1094        writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1095        writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1096out_restart_rx:
1097        qcom_geni_serial_start_rx(uport);
1098}
1099
1100static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
1101{
1102        return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
1103}
1104
1105#ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
1106static int qcom_geni_console_setup(struct console *co, char *options)
1107{
1108        struct uart_port *uport;
1109        struct qcom_geni_serial_port *port;
1110        int baud = 115200;
1111        int bits = 8;
1112        int parity = 'n';
1113        int flow = 'n';
1114        int ret;
1115
1116        if (co->index >= GENI_UART_CONS_PORTS  || co->index < 0)
1117                return -ENXIO;
1118
1119        port = get_port_from_line(co->index, true);
1120        if (IS_ERR(port)) {
1121                pr_err("Invalid line %d\n", co->index);
1122                return PTR_ERR(port);
1123        }
1124
1125        uport = &port->uport;
1126
1127        if (unlikely(!uport->membase))
1128                return -ENXIO;
1129
1130        if (!port->setup) {
1131                ret = qcom_geni_serial_port_setup(uport);
1132                if (ret)
1133                        return ret;
1134        }
1135
1136        if (options)
1137                uart_parse_options(options, &baud, &parity, &bits, &flow);
1138
1139        return uart_set_options(uport, co, baud, parity, bits, flow);
1140}
1141
1142static void qcom_geni_serial_earlycon_write(struct console *con,
1143                                        const char *s, unsigned int n)
1144{
1145        struct earlycon_device *dev = con->data;
1146
1147        __qcom_geni_serial_console_write(&dev->port, s, n);
1148}
1149
1150#ifdef CONFIG_CONSOLE_POLL
1151static int qcom_geni_serial_earlycon_read(struct console *con,
1152                                          char *s, unsigned int n)
1153{
1154        struct earlycon_device *dev = con->data;
1155        struct uart_port *uport = &dev->port;
1156        int num_read = 0;
1157        int ch;
1158
1159        while (num_read < n) {
1160                ch = qcom_geni_serial_get_char(uport);
1161                if (ch == NO_POLL_CHAR)
1162                        break;
1163                s[num_read++] = ch;
1164        }
1165
1166        return num_read;
1167}
1168
1169static void __init qcom_geni_serial_enable_early_read(struct geni_se *se,
1170                                                      struct console *con)
1171{
1172        geni_se_setup_s_cmd(se, UART_START_READ, 0);
1173        con->read = qcom_geni_serial_earlycon_read;
1174}
1175#else
1176static inline void qcom_geni_serial_enable_early_read(struct geni_se *se,
1177                                                      struct console *con) { }
1178#endif
1179
1180static struct qcom_geni_private_data earlycon_private_data;
1181
1182static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
1183                                                                const char *opt)
1184{
1185        struct uart_port *uport = &dev->port;
1186        u32 tx_trans_cfg;
1187        u32 tx_parity_cfg = 0;  /* Disable Tx Parity */
1188        u32 rx_trans_cfg = 0;
1189        u32 rx_parity_cfg = 0;  /* Disable Rx Parity */
1190        u32 stop_bit_len = 0;   /* Default stop bit length - 1 bit */
1191        u32 bits_per_char;
1192        struct geni_se se;
1193
1194        if (!uport->membase)
1195                return -EINVAL;
1196
1197        uport->private_data = &earlycon_private_data;
1198
1199        memset(&se, 0, sizeof(se));
1200        se.base = uport->membase;
1201        if (geni_se_read_proto(&se) != GENI_SE_UART)
1202                return -ENXIO;
1203        /*
1204         * Ignore Flow control.
1205         * n = 8.
1206         */
1207        tx_trans_cfg = UART_CTS_MASK;
1208        bits_per_char = BITS_PER_BYTE;
1209
1210        /*
1211         * Make an unconditional cancel on the main sequencer to reset
1212         * it else we could end up in data loss scenarios.
1213         */
1214        qcom_geni_serial_poll_tx_done(uport);
1215        qcom_geni_serial_abort_rx(uport);
1216        geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
1217                               false, true, true);
1218        geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
1219        geni_se_select_mode(&se, GENI_SE_FIFO);
1220
1221        writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1222        writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1223        writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1224        writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1225        writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1226        writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1227        writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1228
1229        dev->con->write = qcom_geni_serial_earlycon_write;
1230        dev->con->setup = NULL;
1231        qcom_geni_serial_enable_early_read(&se, dev->con);
1232
1233        return 0;
1234}
1235OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1236                                qcom_geni_serial_earlycon_setup);
1237
1238static int __init console_register(struct uart_driver *drv)
1239{
1240        return uart_register_driver(drv);
1241}
1242
1243static void console_unregister(struct uart_driver *drv)
1244{
1245        uart_unregister_driver(drv);
1246}
1247
1248static struct console cons_ops = {
1249        .name = "ttyMSM",
1250        .write = qcom_geni_serial_console_write,
1251        .device = uart_console_device,
1252        .setup = qcom_geni_console_setup,
1253        .flags = CON_PRINTBUFFER,
1254        .index = -1,
1255        .data = &qcom_geni_console_driver,
1256};
1257
1258static struct uart_driver qcom_geni_console_driver = {
1259        .owner = THIS_MODULE,
1260        .driver_name = "qcom_geni_console",
1261        .dev_name = "ttyMSM",
1262        .nr =  GENI_UART_CONS_PORTS,
1263        .cons = &cons_ops,
1264};
1265#else
1266static int console_register(struct uart_driver *drv)
1267{
1268        return 0;
1269}
1270
1271static void console_unregister(struct uart_driver *drv)
1272{
1273}
1274#endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
1275
1276static struct uart_driver qcom_geni_uart_driver = {
1277        .owner = THIS_MODULE,
1278        .driver_name = "qcom_geni_uart",
1279        .dev_name = "ttyHS",
1280        .nr =  GENI_UART_PORTS,
1281};
1282
1283static void qcom_geni_serial_pm(struct uart_port *uport,
1284                unsigned int new_state, unsigned int old_state)
1285{
1286        struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1287
1288        /* If we've never been called, treat it as off */
1289        if (old_state == UART_PM_STATE_UNDEFINED)
1290                old_state = UART_PM_STATE_OFF;
1291
1292        if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) {
1293                geni_icc_enable(&port->se);
1294                geni_se_resources_on(&port->se);
1295        } else if (new_state == UART_PM_STATE_OFF &&
1296                        old_state == UART_PM_STATE_ON) {
1297                geni_se_resources_off(&port->se);
1298                geni_icc_disable(&port->se);
1299        }
1300}
1301
1302static const struct uart_ops qcom_geni_console_pops = {
1303        .tx_empty = qcom_geni_serial_tx_empty,
1304        .stop_tx = qcom_geni_serial_stop_tx,
1305        .start_tx = qcom_geni_serial_start_tx,
1306        .stop_rx = qcom_geni_serial_stop_rx,
1307        .set_termios = qcom_geni_serial_set_termios,
1308        .startup = qcom_geni_serial_startup,
1309        .request_port = qcom_geni_serial_request_port,
1310        .config_port = qcom_geni_serial_config_port,
1311        .shutdown = qcom_geni_serial_shutdown,
1312        .type = qcom_geni_serial_get_type,
1313        .set_mctrl = qcom_geni_serial_set_mctrl,
1314        .get_mctrl = qcom_geni_serial_get_mctrl,
1315#ifdef CONFIG_CONSOLE_POLL
1316        .poll_get_char  = qcom_geni_serial_get_char,
1317        .poll_put_char  = qcom_geni_serial_poll_put_char,
1318#endif
1319        .pm = qcom_geni_serial_pm,
1320};
1321
1322static const struct uart_ops qcom_geni_uart_pops = {
1323        .tx_empty = qcom_geni_serial_tx_empty,
1324        .stop_tx = qcom_geni_serial_stop_tx,
1325        .start_tx = qcom_geni_serial_start_tx,
1326        .stop_rx = qcom_geni_serial_stop_rx,
1327        .set_termios = qcom_geni_serial_set_termios,
1328        .startup = qcom_geni_serial_startup,
1329        .request_port = qcom_geni_serial_request_port,
1330        .config_port = qcom_geni_serial_config_port,
1331        .shutdown = qcom_geni_serial_shutdown,
1332        .type = qcom_geni_serial_get_type,
1333        .set_mctrl = qcom_geni_serial_set_mctrl,
1334        .get_mctrl = qcom_geni_serial_get_mctrl,
1335        .pm = qcom_geni_serial_pm,
1336};
1337
1338static int qcom_geni_serial_probe(struct platform_device *pdev)
1339{
1340        int ret = 0;
1341        int line = -1;
1342        struct qcom_geni_serial_port *port;
1343        struct uart_port *uport;
1344        struct resource *res;
1345        int irq;
1346        bool console = false;
1347        struct uart_driver *drv;
1348
1349        if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart"))
1350                console = true;
1351
1352        if (console) {
1353                drv = &qcom_geni_console_driver;
1354                line = of_alias_get_id(pdev->dev.of_node, "serial");
1355        } else {
1356                drv = &qcom_geni_uart_driver;
1357                line = of_alias_get_id(pdev->dev.of_node, "hsuart");
1358        }
1359
1360        port = get_port_from_line(line, console);
1361        if (IS_ERR(port)) {
1362                dev_err(&pdev->dev, "Invalid line %d\n", line);
1363                return PTR_ERR(port);
1364        }
1365
1366        uport = &port->uport;
1367        /* Don't allow 2 drivers to access the same port */
1368        if (uport->private_data)
1369                return -ENODEV;
1370
1371        uport->dev = &pdev->dev;
1372        port->se.dev = &pdev->dev;
1373        port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1374        port->se.clk = devm_clk_get(&pdev->dev, "se");
1375        if (IS_ERR(port->se.clk)) {
1376                ret = PTR_ERR(port->se.clk);
1377                dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1378                return ret;
1379        }
1380
1381        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1382        if (!res)
1383                return -EINVAL;
1384        uport->mapbase = res->start;
1385
1386        port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1387        port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1388        port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1389
1390        if (!console) {
1391                port->rx_fifo = devm_kcalloc(uport->dev,
1392                        port->rx_fifo_depth, sizeof(u32), GFP_KERNEL);
1393                if (!port->rx_fifo)
1394                        return -ENOMEM;
1395        }
1396
1397        ret = geni_icc_get(&port->se, NULL);
1398        if (ret)
1399                return ret;
1400        port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
1401        port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
1402
1403        /* Set BW for register access */
1404        ret = geni_icc_set_bw(&port->se);
1405        if (ret)
1406                return ret;
1407
1408        port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
1409                        "qcom_geni_serial_%s%d",
1410                        uart_console(uport) ? "console" : "uart", uport->line);
1411        if (!port->name)
1412                return -ENOMEM;
1413
1414        irq = platform_get_irq(pdev, 0);
1415        if (irq < 0)
1416                return irq;
1417        uport->irq = irq;
1418        uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE);
1419
1420        if (!console)
1421                port->wakeup_irq = platform_get_irq_optional(pdev, 1);
1422
1423        if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"))
1424                port->rx_tx_swap = true;
1425
1426        if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap"))
1427                port->cts_rts_swap = true;
1428
1429        ret = devm_pm_opp_set_clkname(&pdev->dev, "se");
1430        if (ret)
1431                return ret;
1432        /* OPP table is optional */
1433        ret = devm_pm_opp_of_add_table(&pdev->dev);
1434        if (ret && ret != -ENODEV) {
1435                dev_err(&pdev->dev, "invalid OPP table in device tree\n");
1436                return ret;
1437        }
1438
1439        port->private_data.drv = drv;
1440        uport->private_data = &port->private_data;
1441        platform_set_drvdata(pdev, port);
1442        port->handle_rx = console ? handle_rx_console : handle_rx_uart;
1443
1444        ret = uart_add_one_port(drv, uport);
1445        if (ret)
1446                return ret;
1447
1448        irq_set_status_flags(uport->irq, IRQ_NOAUTOEN);
1449        ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr,
1450                        IRQF_TRIGGER_HIGH, port->name, uport);
1451        if (ret) {
1452                dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
1453                uart_remove_one_port(drv, uport);
1454                return ret;
1455        }
1456
1457        /*
1458         * Set pm_runtime status as ACTIVE so that wakeup_irq gets
1459         * enabled/disabled from dev_pm_arm_wake_irq during system
1460         * suspend/resume respectively.
1461         */
1462        pm_runtime_set_active(&pdev->dev);
1463
1464        if (port->wakeup_irq > 0) {
1465                device_init_wakeup(&pdev->dev, true);
1466                ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1467                                                port->wakeup_irq);
1468                if (ret) {
1469                        device_init_wakeup(&pdev->dev, false);
1470                        uart_remove_one_port(drv, uport);
1471                        return ret;
1472                }
1473        }
1474
1475        return 0;
1476}
1477
1478static int qcom_geni_serial_remove(struct platform_device *pdev)
1479{
1480        struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1481        struct uart_driver *drv = port->private_data.drv;
1482
1483        dev_pm_clear_wake_irq(&pdev->dev);
1484        device_init_wakeup(&pdev->dev, false);
1485        uart_remove_one_port(drv, &port->uport);
1486
1487        return 0;
1488}
1489
1490static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev)
1491{
1492        struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1493        struct uart_port *uport = &port->uport;
1494        struct qcom_geni_private_data *private_data = uport->private_data;
1495
1496        /*
1497         * This is done so we can hit the lowest possible state in suspend
1498         * even with no_console_suspend
1499         */
1500        if (uart_console(uport)) {
1501                geni_icc_set_tag(&port->se, 0x3);
1502                geni_icc_set_bw(&port->se);
1503        }
1504        return uart_suspend_port(private_data->drv, uport);
1505}
1506
1507static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev)
1508{
1509        int ret;
1510        struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1511        struct uart_port *uport = &port->uport;
1512        struct qcom_geni_private_data *private_data = uport->private_data;
1513
1514        ret = uart_resume_port(private_data->drv, uport);
1515        if (uart_console(uport)) {
1516                geni_icc_set_tag(&port->se, 0x7);
1517                geni_icc_set_bw(&port->se);
1518        }
1519        return ret;
1520}
1521
1522static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1523        SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend,
1524                                        qcom_geni_serial_sys_resume)
1525};
1526
1527static const struct of_device_id qcom_geni_serial_match_table[] = {
1528        { .compatible = "qcom,geni-debug-uart", },
1529        { .compatible = "qcom,geni-uart", },
1530        {}
1531};
1532MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1533
1534static struct platform_driver qcom_geni_serial_platform_driver = {
1535        .remove = qcom_geni_serial_remove,
1536        .probe = qcom_geni_serial_probe,
1537        .driver = {
1538                .name = "qcom_geni_serial",
1539                .of_match_table = qcom_geni_serial_match_table,
1540                .pm = &qcom_geni_serial_pm_ops,
1541        },
1542};
1543
1544static int __init qcom_geni_serial_init(void)
1545{
1546        int ret;
1547
1548        ret = console_register(&qcom_geni_console_driver);
1549        if (ret)
1550                return ret;
1551
1552        ret = uart_register_driver(&qcom_geni_uart_driver);
1553        if (ret) {
1554                console_unregister(&qcom_geni_console_driver);
1555                return ret;
1556        }
1557
1558        ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1559        if (ret) {
1560                console_unregister(&qcom_geni_console_driver);
1561                uart_unregister_driver(&qcom_geni_uart_driver);
1562        }
1563        return ret;
1564}
1565module_init(qcom_geni_serial_init);
1566
1567static void __exit qcom_geni_serial_exit(void)
1568{
1569        platform_driver_unregister(&qcom_geni_serial_platform_driver);
1570        console_unregister(&qcom_geni_console_driver);
1571        uart_unregister_driver(&qcom_geni_uart_driver);
1572}
1573module_exit(qcom_geni_serial_exit);
1574
1575MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1576MODULE_LICENSE("GPL v2");
1577