linux/drivers/net/ethernet/intel/ice/ice_txrx.h
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   1/* SPDX-License-Identifier: GPL-2.0 */
   2/* Copyright (c) 2018, Intel Corporation. */
   3
   4#ifndef _ICE_TXRX_H_
   5#define _ICE_TXRX_H_
   6
   7#include "ice_type.h"
   8
   9#define ICE_DFLT_IRQ_WORK       256
  10#define ICE_RXBUF_3072          3072
  11#define ICE_RXBUF_2048          2048
  12#define ICE_RXBUF_1536          1536
  13#define ICE_MAX_CHAINED_RX_BUFS 5
  14#define ICE_MAX_BUF_TXD         8
  15#define ICE_MIN_TX_LEN          17
  16
  17/* The size limit for a transmit buffer in a descriptor is (16K - 1).
  18 * In order to align with the read requests we will align the value to
  19 * the nearest 4K which represents our maximum read request size.
  20 */
  21#define ICE_MAX_READ_REQ_SIZE   4096
  22#define ICE_MAX_DATA_PER_TXD    (16 * 1024 - 1)
  23#define ICE_MAX_DATA_PER_TXD_ALIGNED \
  24        (~(ICE_MAX_READ_REQ_SIZE - 1) & ICE_MAX_DATA_PER_TXD)
  25
  26#define ICE_RX_BUF_WRITE        16      /* Must be power of 2 */
  27#define ICE_MAX_TXQ_PER_TXQG    128
  28
  29/* Attempt to maximize the headroom available for incoming frames. We use a 2K
  30 * buffer for MTUs <= 1500 and need 1536/1534 to store the data for the frame.
  31 * This leaves us with 512 bytes of room.  From that we need to deduct the
  32 * space needed for the shared info and the padding needed to IP align the
  33 * frame.
  34 *
  35 * Note: For cache line sizes 256 or larger this value is going to end
  36 *       up negative.  In these cases we should fall back to the legacy
  37 *       receive path.
  38 */
  39#if (PAGE_SIZE < 8192)
  40#define ICE_2K_TOO_SMALL_WITH_PADDING \
  41        ((unsigned int)(NET_SKB_PAD + ICE_RXBUF_1536) > \
  42                        SKB_WITH_OVERHEAD(ICE_RXBUF_2048))
  43
  44/**
  45 * ice_compute_pad - compute the padding
  46 * @rx_buf_len: buffer length
  47 *
  48 * Figure out the size of half page based on given buffer length and
  49 * then subtract the skb_shared_info followed by subtraction of the
  50 * actual buffer length; this in turn results in the actual space that
  51 * is left for padding usage
  52 */
  53static inline int ice_compute_pad(int rx_buf_len)
  54{
  55        int half_page_size;
  56
  57        half_page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2);
  58        return SKB_WITH_OVERHEAD(half_page_size) - rx_buf_len;
  59}
  60
  61/**
  62 * ice_skb_pad - determine the padding that we can supply
  63 *
  64 * Figure out the right Rx buffer size and based on that calculate the
  65 * padding
  66 */
  67static inline int ice_skb_pad(void)
  68{
  69        int rx_buf_len;
  70
  71        /* If a 2K buffer cannot handle a standard Ethernet frame then
  72         * optimize padding for a 3K buffer instead of a 1.5K buffer.
  73         *
  74         * For a 3K buffer we need to add enough padding to allow for
  75         * tailroom due to NET_IP_ALIGN possibly shifting us out of
  76         * cache-line alignment.
  77         */
  78        if (ICE_2K_TOO_SMALL_WITH_PADDING)
  79                rx_buf_len = ICE_RXBUF_3072 + SKB_DATA_ALIGN(NET_IP_ALIGN);
  80        else
  81                rx_buf_len = ICE_RXBUF_1536;
  82
  83        /* if needed make room for NET_IP_ALIGN */
  84        rx_buf_len -= NET_IP_ALIGN;
  85
  86        return ice_compute_pad(rx_buf_len);
  87}
  88
  89#define ICE_SKB_PAD ice_skb_pad()
  90#else
  91#define ICE_2K_TOO_SMALL_WITH_PADDING false
  92#define ICE_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
  93#endif
  94
  95/* We are assuming that the cache line is always 64 Bytes here for ice.
  96 * In order to make sure that is a correct assumption there is a check in probe
  97 * to print a warning if the read from GLPCI_CNF2 tells us that the cache line
  98 * size is 128 bytes. We do it this way because we do not want to read the
  99 * GLPCI_CNF2 register or a variable containing the value on every pass through
 100 * the Tx path.
 101 */
 102#define ICE_CACHE_LINE_BYTES            64
 103#define ICE_DESCS_PER_CACHE_LINE        (ICE_CACHE_LINE_BYTES / \
 104                                         sizeof(struct ice_tx_desc))
 105#define ICE_DESCS_FOR_CTX_DESC          1
 106#define ICE_DESCS_FOR_SKB_DATA_PTR      1
 107/* Tx descriptors needed, worst case */
 108#define DESC_NEEDED (MAX_SKB_FRAGS + ICE_DESCS_FOR_CTX_DESC + \
 109                     ICE_DESCS_PER_CACHE_LINE + ICE_DESCS_FOR_SKB_DATA_PTR)
 110#define ICE_DESC_UNUSED(R)      \
 111        (u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 112              (R)->next_to_clean - (R)->next_to_use - 1)
 113
 114#define ICE_TX_FLAGS_TSO        BIT(0)
 115#define ICE_TX_FLAGS_HW_VLAN    BIT(1)
 116#define ICE_TX_FLAGS_SW_VLAN    BIT(2)
 117/* ICE_TX_FLAGS_DUMMY_PKT is used to mark dummy packets that should be
 118 * freed instead of returned like skb packets.
 119 */
 120#define ICE_TX_FLAGS_DUMMY_PKT  BIT(3)
 121#define ICE_TX_FLAGS_IPV4       BIT(5)
 122#define ICE_TX_FLAGS_IPV6       BIT(6)
 123#define ICE_TX_FLAGS_TUNNEL     BIT(7)
 124#define ICE_TX_FLAGS_VLAN_M     0xffff0000
 125#define ICE_TX_FLAGS_VLAN_PR_M  0xe0000000
 126#define ICE_TX_FLAGS_VLAN_PR_S  29
 127#define ICE_TX_FLAGS_VLAN_S     16
 128
 129#define ICE_XDP_PASS            0
 130#define ICE_XDP_CONSUMED        BIT(0)
 131#define ICE_XDP_TX              BIT(1)
 132#define ICE_XDP_REDIR           BIT(2)
 133
 134#define ICE_RX_DMA_ATTR \
 135        (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
 136
 137#define ICE_ETH_PKT_HDR_PAD     (ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2))
 138
 139#define ICE_TXD_LAST_DESC_CMD (ICE_TX_DESC_CMD_EOP | ICE_TX_DESC_CMD_RS)
 140
 141struct ice_tx_buf {
 142        struct ice_tx_desc *next_to_watch;
 143        union {
 144                struct sk_buff *skb;
 145                void *raw_buf; /* used for XDP */
 146        };
 147        unsigned int bytecount;
 148        unsigned short gso_segs;
 149        u32 tx_flags;
 150        DEFINE_DMA_UNMAP_LEN(len);
 151        DEFINE_DMA_UNMAP_ADDR(dma);
 152};
 153
 154struct ice_tx_offload_params {
 155        u64 cd_qw1;
 156        struct ice_ring *tx_ring;
 157        u32 td_cmd;
 158        u32 td_offset;
 159        u32 td_l2tag1;
 160        u32 cd_tunnel_params;
 161        u16 cd_l2tag2;
 162        u8 header_len;
 163};
 164
 165struct ice_rx_buf {
 166        union {
 167                struct {
 168                        dma_addr_t dma;
 169                        struct page *page;
 170                        unsigned int page_offset;
 171                        u16 pagecnt_bias;
 172                };
 173                struct {
 174                        struct xdp_buff *xdp;
 175                };
 176        };
 177};
 178
 179struct ice_q_stats {
 180        u64 pkts;
 181        u64 bytes;
 182};
 183
 184struct ice_txq_stats {
 185        u64 restart_q;
 186        u64 tx_busy;
 187        u64 tx_linearize;
 188        int prev_pkt; /* negative if no pending Tx descriptors */
 189};
 190
 191struct ice_rxq_stats {
 192        u64 non_eop_descs;
 193        u64 alloc_page_failed;
 194        u64 alloc_buf_failed;
 195};
 196
 197enum ice_ring_state_t {
 198        ICE_TX_XPS_INIT_DONE,
 199        ICE_TX_NBITS,
 200};
 201
 202/* this enum matches hardware bits and is meant to be used by DYN_CTLN
 203 * registers and QINT registers or more generally anywhere in the manual
 204 * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any
 205 * register but instead is a special value meaning "don't update" ITR0/1/2.
 206 */
 207enum ice_dyn_idx_t {
 208        ICE_IDX_ITR0 = 0,
 209        ICE_IDX_ITR1 = 1,
 210        ICE_IDX_ITR2 = 2,
 211        ICE_ITR_NONE = 3        /* ITR_NONE must not be used as an index */
 212};
 213
 214/* Header split modes defined by DTYPE field of Rx RLAN context */
 215enum ice_rx_dtype {
 216        ICE_RX_DTYPE_NO_SPLIT           = 0,
 217        ICE_RX_DTYPE_HEADER_SPLIT       = 1,
 218        ICE_RX_DTYPE_SPLIT_ALWAYS       = 2,
 219};
 220
 221/* indices into GLINT_ITR registers */
 222#define ICE_RX_ITR      ICE_IDX_ITR0
 223#define ICE_TX_ITR      ICE_IDX_ITR1
 224#define ICE_ITR_8K      124
 225#define ICE_ITR_20K     50
 226#define ICE_ITR_MAX     8160 /* 0x1FE0 */
 227#define ICE_DFLT_TX_ITR ICE_ITR_20K
 228#define ICE_DFLT_RX_ITR ICE_ITR_20K
 229enum ice_dynamic_itr {
 230        ITR_STATIC = 0,
 231        ITR_DYNAMIC = 1
 232};
 233
 234#define ITR_IS_DYNAMIC(rc) ((rc)->itr_mode == ITR_DYNAMIC)
 235#define ICE_ITR_GRAN_S          1       /* ITR granularity is always 2us */
 236#define ICE_ITR_GRAN_US         BIT(ICE_ITR_GRAN_S)
 237#define ICE_ITR_MASK            0x1FFE  /* ITR register value alignment mask */
 238#define ITR_REG_ALIGN(setting)  ((setting) & ICE_ITR_MASK)
 239
 240#define ICE_DFLT_INTRL  0
 241#define ICE_MAX_INTRL   236
 242
 243#define ICE_IN_WB_ON_ITR_MODE   255
 244/* Sets WB_ON_ITR and assumes INTENA bit is already cleared, which allows
 245 * setting the MSK_M bit to tell hardware to ignore the INTENA_M bit. Also,
 246 * set the write-back latency to the usecs passed in.
 247 */
 248#define ICE_GLINT_DYN_CTL_WB_ON_ITR(usecs, itr_idx)     \
 249        ((((usecs) << (GLINT_DYN_CTL_INTERVAL_S - ICE_ITR_GRAN_S)) & \
 250          GLINT_DYN_CTL_INTERVAL_M) | \
 251         (((itr_idx) << GLINT_DYN_CTL_ITR_INDX_S) & \
 252          GLINT_DYN_CTL_ITR_INDX_M) | GLINT_DYN_CTL_INTENA_MSK_M | \
 253         GLINT_DYN_CTL_WB_ON_ITR_M)
 254
 255/* Legacy or Advanced Mode Queue */
 256#define ICE_TX_ADVANCED 0
 257#define ICE_TX_LEGACY   1
 258
 259/* descriptor ring, associated with a VSI */
 260struct ice_ring {
 261        /* CL1 - 1st cacheline starts here */
 262        struct ice_ring *next;          /* pointer to next ring in q_vector */
 263        void *desc;                     /* Descriptor ring memory */
 264        struct device *dev;             /* Used for DMA mapping */
 265        struct net_device *netdev;      /* netdev ring maps to */
 266        struct ice_vsi *vsi;            /* Backreference to associated VSI */
 267        struct ice_q_vector *q_vector;  /* Backreference to associated vector */
 268        u8 __iomem *tail;
 269        union {
 270                struct ice_tx_buf *tx_buf;
 271                struct ice_rx_buf *rx_buf;
 272        };
 273        /* CL2 - 2nd cacheline starts here */
 274        u16 q_index;                    /* Queue number of ring */
 275        u16 q_handle;                   /* Queue handle per TC */
 276
 277        u8 ring_active:1;               /* is ring online or not */
 278
 279        u16 count;                      /* Number of descriptors */
 280        u16 reg_idx;                    /* HW register index of the ring */
 281
 282        /* used in interrupt processing */
 283        u16 next_to_use;
 284        u16 next_to_clean;
 285        u16 next_to_alloc;
 286
 287        /* stats structs */
 288        struct ice_q_stats      stats;
 289        struct u64_stats_sync syncp;
 290        union {
 291                struct ice_txq_stats tx_stats;
 292                struct ice_rxq_stats rx_stats;
 293        };
 294
 295        struct rcu_head rcu;            /* to avoid race on free */
 296        DECLARE_BITMAP(xps_state, ICE_TX_NBITS);        /* XPS Config State */
 297        struct bpf_prog *xdp_prog;
 298        struct xsk_buff_pool *xsk_pool;
 299        u16 rx_offset;
 300        /* CL3 - 3rd cacheline starts here */
 301        struct xdp_rxq_info xdp_rxq;
 302        struct sk_buff *skb;
 303        /* CLX - the below items are only accessed infrequently and should be
 304         * in their own cache line if possible
 305         */
 306#define ICE_TX_FLAGS_RING_XDP           BIT(0)
 307#define ICE_RX_FLAGS_RING_BUILD_SKB     BIT(1)
 308        u8 flags;
 309        dma_addr_t dma;                 /* physical address of ring */
 310        unsigned int size;              /* length of descriptor ring in bytes */
 311        u32 txq_teid;                   /* Added Tx queue TEID */
 312        u16 rx_buf_len;
 313        u8 dcb_tc;                      /* Traffic class of ring */
 314} ____cacheline_internodealigned_in_smp;
 315
 316static inline bool ice_ring_uses_build_skb(struct ice_ring *ring)
 317{
 318        return !!(ring->flags & ICE_RX_FLAGS_RING_BUILD_SKB);
 319}
 320
 321static inline void ice_set_ring_build_skb_ena(struct ice_ring *ring)
 322{
 323        ring->flags |= ICE_RX_FLAGS_RING_BUILD_SKB;
 324}
 325
 326static inline void ice_clear_ring_build_skb_ena(struct ice_ring *ring)
 327{
 328        ring->flags &= ~ICE_RX_FLAGS_RING_BUILD_SKB;
 329}
 330
 331static inline bool ice_ring_is_xdp(struct ice_ring *ring)
 332{
 333        return !!(ring->flags & ICE_TX_FLAGS_RING_XDP);
 334}
 335
 336struct ice_ring_container {
 337        /* head of linked-list of rings */
 338        struct ice_ring *ring;
 339        struct dim dim;         /* data for net_dim algorithm */
 340        u16 itr_idx;            /* index in the interrupt vector */
 341        /* this matches the maximum number of ITR bits, but in usec
 342         * values, so it is shifted left one bit (bit zero is ignored)
 343         */
 344        u16 itr_setting:13;
 345        u16 itr_reserved:2;
 346        u16 itr_mode:1;
 347};
 348
 349struct ice_coalesce_stored {
 350        u16 itr_tx;
 351        u16 itr_rx;
 352        u8 intrl;
 353        u8 tx_valid;
 354        u8 rx_valid;
 355};
 356
 357/* iterator for handling rings in ring container */
 358#define ice_for_each_ring(pos, head) \
 359        for (pos = (head).ring; pos; pos = pos->next)
 360
 361static inline unsigned int ice_rx_pg_order(struct ice_ring *ring)
 362{
 363#if (PAGE_SIZE < 8192)
 364        if (ring->rx_buf_len > (PAGE_SIZE / 2))
 365                return 1;
 366#endif
 367        return 0;
 368}
 369
 370#define ice_rx_pg_size(_ring) (PAGE_SIZE << ice_rx_pg_order(_ring))
 371
 372union ice_32b_rx_flex_desc;
 373
 374bool ice_alloc_rx_bufs(struct ice_ring *rxr, u16 cleaned_count);
 375netdev_tx_t ice_start_xmit(struct sk_buff *skb, struct net_device *netdev);
 376void ice_clean_tx_ring(struct ice_ring *tx_ring);
 377void ice_clean_rx_ring(struct ice_ring *rx_ring);
 378int ice_setup_tx_ring(struct ice_ring *tx_ring);
 379int ice_setup_rx_ring(struct ice_ring *rx_ring);
 380void ice_free_tx_ring(struct ice_ring *tx_ring);
 381void ice_free_rx_ring(struct ice_ring *rx_ring);
 382int ice_napi_poll(struct napi_struct *napi, int budget);
 383int
 384ice_prgm_fdir_fltr(struct ice_vsi *vsi, struct ice_fltr_desc *fdir_desc,
 385                   u8 *raw_packet);
 386int ice_clean_rx_irq(struct ice_ring *rx_ring, int budget);
 387void ice_clean_ctrl_tx_irq(struct ice_ring *tx_ring);
 388#endif /* _ICE_TXRX_H_ */
 389