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7#ifndef HINIC_PORT_H
8#define HINIC_PORT_H
9
10#include <linux/types.h>
11#include <linux/ethtool.h>
12#include <linux/etherdevice.h>
13#include <linux/bitops.h>
14
15#include "hinic_dev.h"
16
17#define HINIC_RSS_KEY_SIZE 40
18#define HINIC_RSS_INDIR_SIZE 256
19#define HINIC_PORT_STATS_VERSION 0
20#define HINIC_FW_VERSION_NAME 16
21#define HINIC_COMPILE_TIME_LEN 20
22#define HINIC_MGMT_VERSION_MAX_LEN 32
23
24struct hinic_version_info {
25 u8 status;
26 u8 version;
27 u8 rsvd[6];
28
29 u8 ver[HINIC_FW_VERSION_NAME];
30 u8 time[HINIC_COMPILE_TIME_LEN];
31};
32
33enum hinic_rx_mode {
34 HINIC_RX_MODE_UC = BIT(0),
35 HINIC_RX_MODE_MC = BIT(1),
36 HINIC_RX_MODE_BC = BIT(2),
37 HINIC_RX_MODE_MC_ALL = BIT(3),
38 HINIC_RX_MODE_PROMISC = BIT(4),
39};
40
41enum hinic_port_link_state {
42 HINIC_LINK_STATE_DOWN,
43 HINIC_LINK_STATE_UP,
44};
45
46enum hinic_port_state {
47 HINIC_PORT_DISABLE = 0,
48 HINIC_PORT_ENABLE = 3,
49};
50
51enum hinic_func_port_state {
52 HINIC_FUNC_PORT_DISABLE = 0,
53 HINIC_FUNC_PORT_ENABLE = 2,
54};
55
56enum hinic_autoneg_cap {
57 HINIC_AUTONEG_UNSUPPORTED,
58 HINIC_AUTONEG_SUPPORTED,
59};
60
61enum hinic_autoneg_state {
62 HINIC_AUTONEG_DISABLED,
63 HINIC_AUTONEG_ACTIVE,
64};
65
66enum hinic_duplex {
67 HINIC_DUPLEX_HALF,
68 HINIC_DUPLEX_FULL,
69};
70
71enum hinic_speed {
72 HINIC_SPEED_10MB_LINK = 0,
73 HINIC_SPEED_100MB_LINK,
74 HINIC_SPEED_1000MB_LINK,
75 HINIC_SPEED_10GB_LINK,
76 HINIC_SPEED_25GB_LINK,
77 HINIC_SPEED_40GB_LINK,
78 HINIC_SPEED_100GB_LINK,
79
80 HINIC_SPEED_UNKNOWN = 0xFF,
81};
82
83enum hinic_link_mode {
84 HINIC_10GE_BASE_KR = 0,
85 HINIC_40GE_BASE_KR4 = 1,
86 HINIC_40GE_BASE_CR4 = 2,
87 HINIC_100GE_BASE_KR4 = 3,
88 HINIC_100GE_BASE_CR4 = 4,
89 HINIC_25GE_BASE_KR_S = 5,
90 HINIC_25GE_BASE_CR_S = 6,
91 HINIC_25GE_BASE_KR = 7,
92 HINIC_25GE_BASE_CR = 8,
93 HINIC_GE_BASE_KX = 9,
94 HINIC_LINK_MODE_NUMBERS,
95
96 HINIC_SUPPORTED_UNKNOWN = 0xFFFF,
97};
98
99enum hinic_port_type {
100 HINIC_PORT_TP,
101 HINIC_PORT_AUI,
102 HINIC_PORT_MII,
103 HINIC_PORT_FIBRE,
104 HINIC_PORT_BNC,
105 HINIC_PORT_ELEC,
106 HINIC_PORT_COPPER,
107 HINIC_PORT_AOC,
108 HINIC_PORT_BACKPLANE,
109 HINIC_PORT_NONE = 0xEF,
110 HINIC_PORT_OTHER = 0xFF,
111};
112
113enum hinic_valid_link_settings {
114 HILINK_LINK_SET_SPEED = 0x1,
115 HILINK_LINK_SET_AUTONEG = 0x2,
116 HILINK_LINK_SET_FEC = 0x4,
117};
118
119enum hinic_tso_state {
120 HINIC_TSO_DISABLE = 0,
121 HINIC_TSO_ENABLE = 1,
122};
123
124struct hinic_port_mac_cmd {
125 u8 status;
126 u8 version;
127 u8 rsvd0[6];
128
129 u16 func_idx;
130 u16 vlan_id;
131 u16 rsvd1;
132 unsigned char mac[ETH_ALEN];
133};
134
135struct hinic_port_mtu_cmd {
136 u8 status;
137 u8 version;
138 u8 rsvd0[6];
139
140 u16 func_idx;
141 u16 rsvd1;
142 u32 mtu;
143};
144
145struct hinic_port_vlan_cmd {
146 u8 status;
147 u8 version;
148 u8 rsvd0[6];
149
150 u16 func_idx;
151 u16 vlan_id;
152};
153
154struct hinic_port_rx_mode_cmd {
155 u8 status;
156 u8 version;
157 u8 rsvd0[6];
158
159 u16 func_idx;
160 u16 rsvd;
161 u32 rx_mode;
162};
163
164struct hinic_port_link_cmd {
165 u8 status;
166 u8 version;
167 u8 rsvd0[6];
168
169 u16 func_idx;
170 u8 state;
171 u8 rsvd1;
172};
173
174struct hinic_port_state_cmd {
175 u8 status;
176 u8 version;
177 u8 rsvd0[6];
178
179 u8 state;
180 u8 rsvd1[3];
181};
182
183struct hinic_port_link_status {
184 u8 status;
185 u8 version;
186 u8 rsvd0[6];
187
188 u16 func_id;
189 u8 link;
190 u8 port_id;
191};
192
193struct hinic_cable_plug_event {
194 u8 status;
195 u8 version;
196 u8 rsvd0[6];
197
198 u16 func_id;
199 u8 plugged;
200 u8 port_id;
201};
202
203enum link_err_type {
204 LINK_ERR_MODULE_UNRECOGENIZED,
205 LINK_ERR_NUM,
206};
207
208struct hinic_link_err_event {
209 u8 status;
210 u8 version;
211 u8 rsvd0[6];
212
213 u16 func_id;
214 u8 err_type;
215 u8 port_id;
216};
217
218struct hinic_port_func_state_cmd {
219 u8 status;
220 u8 version;
221 u8 rsvd0[6];
222
223 u16 func_idx;
224 u16 rsvd1;
225 u8 state;
226 u8 rsvd2[3];
227};
228
229struct hinic_port_cap {
230 u8 status;
231 u8 version;
232 u8 rsvd0[6];
233
234 u16 func_idx;
235 u16 rsvd1;
236 u8 port_type;
237 u8 autoneg_cap;
238 u8 autoneg_state;
239 u8 duplex;
240 u8 speed;
241 u8 rsvd2[3];
242};
243
244struct hinic_link_mode_cmd {
245 u8 status;
246 u8 version;
247 u8 rsvd0[6];
248
249 u16 func_id;
250 u16 rsvd1;
251 u16 supported;
252 u16 advertised;
253};
254
255struct hinic_speed_cmd {
256 u8 status;
257 u8 version;
258 u8 rsvd0[6];
259
260 u16 func_id;
261 u16 speed;
262};
263
264struct hinic_set_autoneg_cmd {
265 u8 status;
266 u8 version;
267 u8 rsvd0[6];
268
269 u16 func_id;
270 u16 enable;
271};
272
273struct hinic_link_ksettings_info {
274 u8 status;
275 u8 version;
276 u8 rsvd0[6];
277
278 u16 func_id;
279 u16 rsvd1;
280
281 u32 valid_bitmap;
282 u32 speed;
283 u8 autoneg;
284 u8 fec;
285 u8 rsvd2[18];
286};
287
288struct hinic_tso_config {
289 u8 status;
290 u8 version;
291 u8 rsvd0[6];
292
293 u16 func_id;
294 u16 rsvd1;
295 u8 tso_en;
296 u8 resv2[3];
297};
298
299struct hinic_checksum_offload {
300 u8 status;
301 u8 version;
302 u8 rsvd0[6];
303
304 u16 func_id;
305 u16 rsvd1;
306 u32 rx_csum_offload;
307};
308
309struct hinic_rq_num {
310 u8 status;
311 u8 version;
312 u8 rsvd0[6];
313
314 u16 func_id;
315 u16 rsvd1[33];
316 u32 num_rqs;
317 u32 rq_depth;
318};
319
320struct hinic_lro_config {
321 u8 status;
322 u8 version;
323 u8 rsvd0[6];
324
325 u16 func_id;
326 u16 rsvd1;
327 u8 lro_ipv4_en;
328 u8 lro_ipv6_en;
329 u8 lro_max_wqe_num;
330 u8 resv2[13];
331};
332
333struct hinic_lro_timer {
334 u8 status;
335 u8 version;
336 u8 rsvd0[6];
337
338 u8 type;
339 u8 enable;
340 u16 rsvd1;
341 u32 timer;
342};
343
344struct hinic_vlan_cfg {
345 u8 status;
346 u8 version;
347 u8 rsvd0[6];
348
349 u16 func_id;
350 u8 vlan_rx_offload;
351 u8 rsvd1[5];
352};
353
354struct hinic_rss_template_mgmt {
355 u8 status;
356 u8 version;
357 u8 rsvd0[6];
358
359 u16 func_id;
360 u8 cmd;
361 u8 template_id;
362 u8 rsvd1[4];
363};
364
365struct hinic_rss_template_key {
366 u8 status;
367 u8 version;
368 u8 rsvd0[6];
369
370 u16 func_id;
371 u8 template_id;
372 u8 rsvd1;
373 u8 key[HINIC_RSS_KEY_SIZE];
374};
375
376struct hinic_rss_context_tbl {
377 u32 group_index;
378 u32 offset;
379 u32 size;
380 u32 rsvd;
381 u32 ctx;
382};
383
384struct hinic_rss_context_table {
385 u8 status;
386 u8 version;
387 u8 rsvd0[6];
388
389 u16 func_id;
390 u8 template_id;
391 u8 rsvd1;
392 u32 context;
393};
394
395struct hinic_rss_indirect_tbl {
396 u32 group_index;
397 u32 offset;
398 u32 size;
399 u32 rsvd;
400 u8 entry[HINIC_RSS_INDIR_SIZE];
401};
402
403struct hinic_rss_indir_table {
404 u8 status;
405 u8 version;
406 u8 rsvd0[6];
407
408 u16 func_id;
409 u8 template_id;
410 u8 rsvd1;
411 u8 indir[HINIC_RSS_INDIR_SIZE];
412};
413
414struct hinic_rss_key {
415 u8 status;
416 u8 version;
417 u8 rsvd0[6];
418
419 u16 func_id;
420 u8 template_id;
421 u8 rsvd1;
422 u8 key[HINIC_RSS_KEY_SIZE];
423};
424
425struct hinic_rss_engine_type {
426 u8 status;
427 u8 version;
428 u8 rsvd0[6];
429
430 u16 func_id;
431 u8 template_id;
432 u8 hash_engine;
433 u8 rsvd1[4];
434};
435
436struct hinic_rss_config {
437 u8 status;
438 u8 version;
439 u8 rsvd0[6];
440
441 u16 func_id;
442 u8 rss_en;
443 u8 template_id;
444 u8 rq_priority_number;
445 u8 rsvd1[11];
446};
447
448struct hinic_stats {
449 char name[ETH_GSTRING_LEN];
450 u32 size;
451 int offset;
452};
453
454struct hinic_vport_stats {
455 u64 tx_unicast_pkts_vport;
456 u64 tx_unicast_bytes_vport;
457 u64 tx_multicast_pkts_vport;
458 u64 tx_multicast_bytes_vport;
459 u64 tx_broadcast_pkts_vport;
460 u64 tx_broadcast_bytes_vport;
461
462 u64 rx_unicast_pkts_vport;
463 u64 rx_unicast_bytes_vport;
464 u64 rx_multicast_pkts_vport;
465 u64 rx_multicast_bytes_vport;
466 u64 rx_broadcast_pkts_vport;
467 u64 rx_broadcast_bytes_vport;
468
469 u64 tx_discard_vport;
470 u64 rx_discard_vport;
471 u64 tx_err_vport;
472 u64 rx_err_vport;
473};
474
475struct hinic_phy_port_stats {
476 u64 mac_rx_total_pkt_num;
477 u64 mac_rx_total_oct_num;
478 u64 mac_rx_bad_pkt_num;
479 u64 mac_rx_bad_oct_num;
480 u64 mac_rx_good_pkt_num;
481 u64 mac_rx_good_oct_num;
482 u64 mac_rx_uni_pkt_num;
483 u64 mac_rx_multi_pkt_num;
484 u64 mac_rx_broad_pkt_num;
485
486 u64 mac_tx_total_pkt_num;
487 u64 mac_tx_total_oct_num;
488 u64 mac_tx_bad_pkt_num;
489 u64 mac_tx_bad_oct_num;
490 u64 mac_tx_good_pkt_num;
491 u64 mac_tx_good_oct_num;
492 u64 mac_tx_uni_pkt_num;
493 u64 mac_tx_multi_pkt_num;
494 u64 mac_tx_broad_pkt_num;
495
496 u64 mac_rx_fragment_pkt_num;
497 u64 mac_rx_undersize_pkt_num;
498 u64 mac_rx_undermin_pkt_num;
499 u64 mac_rx_64_oct_pkt_num;
500 u64 mac_rx_65_127_oct_pkt_num;
501 u64 mac_rx_128_255_oct_pkt_num;
502 u64 mac_rx_256_511_oct_pkt_num;
503 u64 mac_rx_512_1023_oct_pkt_num;
504 u64 mac_rx_1024_1518_oct_pkt_num;
505 u64 mac_rx_1519_2047_oct_pkt_num;
506 u64 mac_rx_2048_4095_oct_pkt_num;
507 u64 mac_rx_4096_8191_oct_pkt_num;
508 u64 mac_rx_8192_9216_oct_pkt_num;
509 u64 mac_rx_9217_12287_oct_pkt_num;
510 u64 mac_rx_12288_16383_oct_pkt_num;
511 u64 mac_rx_1519_max_bad_pkt_num;
512 u64 mac_rx_1519_max_good_pkt_num;
513 u64 mac_rx_oversize_pkt_num;
514 u64 mac_rx_jabber_pkt_num;
515
516 u64 mac_rx_pause_num;
517 u64 mac_rx_pfc_pkt_num;
518 u64 mac_rx_pfc_pri0_pkt_num;
519 u64 mac_rx_pfc_pri1_pkt_num;
520 u64 mac_rx_pfc_pri2_pkt_num;
521 u64 mac_rx_pfc_pri3_pkt_num;
522 u64 mac_rx_pfc_pri4_pkt_num;
523 u64 mac_rx_pfc_pri5_pkt_num;
524 u64 mac_rx_pfc_pri6_pkt_num;
525 u64 mac_rx_pfc_pri7_pkt_num;
526 u64 mac_rx_control_pkt_num;
527 u64 mac_rx_y1731_pkt_num;
528 u64 mac_rx_sym_err_pkt_num;
529 u64 mac_rx_fcs_err_pkt_num;
530 u64 mac_rx_send_app_good_pkt_num;
531 u64 mac_rx_send_app_bad_pkt_num;
532
533 u64 mac_tx_fragment_pkt_num;
534 u64 mac_tx_undersize_pkt_num;
535 u64 mac_tx_undermin_pkt_num;
536 u64 mac_tx_64_oct_pkt_num;
537 u64 mac_tx_65_127_oct_pkt_num;
538 u64 mac_tx_128_255_oct_pkt_num;
539 u64 mac_tx_256_511_oct_pkt_num;
540 u64 mac_tx_512_1023_oct_pkt_num;
541 u64 mac_tx_1024_1518_oct_pkt_num;
542 u64 mac_tx_1519_2047_oct_pkt_num;
543 u64 mac_tx_2048_4095_oct_pkt_num;
544 u64 mac_tx_4096_8191_oct_pkt_num;
545 u64 mac_tx_8192_9216_oct_pkt_num;
546 u64 mac_tx_9217_12287_oct_pkt_num;
547 u64 mac_tx_12288_16383_oct_pkt_num;
548 u64 mac_tx_1519_max_bad_pkt_num;
549 u64 mac_tx_1519_max_good_pkt_num;
550 u64 mac_tx_oversize_pkt_num;
551 u64 mac_tx_jabber_pkt_num;
552
553 u64 mac_tx_pause_num;
554 u64 mac_tx_pfc_pkt_num;
555 u64 mac_tx_pfc_pri0_pkt_num;
556 u64 mac_tx_pfc_pri1_pkt_num;
557 u64 mac_tx_pfc_pri2_pkt_num;
558 u64 mac_tx_pfc_pri3_pkt_num;
559 u64 mac_tx_pfc_pri4_pkt_num;
560 u64 mac_tx_pfc_pri5_pkt_num;
561 u64 mac_tx_pfc_pri6_pkt_num;
562 u64 mac_tx_pfc_pri7_pkt_num;
563 u64 mac_tx_control_pkt_num;
564 u64 mac_tx_y1731_pkt_num;
565 u64 mac_tx_1588_pkt_num;
566 u64 mac_tx_err_all_pkt_num;
567 u64 mac_tx_from_app_good_pkt_num;
568 u64 mac_tx_from_app_bad_pkt_num;
569
570 u64 mac_rx_higig2_ext_pkt_num;
571 u64 mac_rx_higig2_message_pkt_num;
572 u64 mac_rx_higig2_error_pkt_num;
573 u64 mac_rx_higig2_cpu_ctrl_pkt_num;
574 u64 mac_rx_higig2_unicast_pkt_num;
575 u64 mac_rx_higig2_broadcast_pkt_num;
576 u64 mac_rx_higig2_l2_multicast_pkt_num;
577 u64 mac_rx_higig2_l3_multicast_pkt_num;
578
579 u64 mac_tx_higig2_message_pkt_num;
580 u64 mac_tx_higig2_ext_pkt_num;
581 u64 mac_tx_higig2_cpu_ctrl_pkt_num;
582 u64 mac_tx_higig2_unicast_pkt_num;
583 u64 mac_tx_higig2_broadcast_pkt_num;
584 u64 mac_tx_higig2_l2_multicast_pkt_num;
585 u64 mac_tx_higig2_l3_multicast_pkt_num;
586};
587
588struct hinic_port_stats_info {
589 u8 status;
590 u8 version;
591 u8 rsvd0[6];
592
593 u16 func_id;
594 u16 rsvd1;
595 u32 stats_version;
596 u32 stats_size;
597};
598
599struct hinic_port_stats {
600 u8 status;
601 u8 version;
602 u8 rsvd[6];
603
604 struct hinic_phy_port_stats stats;
605};
606
607struct hinic_cmd_vport_stats {
608 u8 status;
609 u8 version;
610 u8 rsvd0[6];
611
612 struct hinic_vport_stats stats;
613};
614
615struct hinic_tx_rate_cfg_max_min {
616 u8 status;
617 u8 version;
618 u8 rsvd0[6];
619
620 u16 func_id;
621 u16 rsvd1;
622 u32 min_rate;
623 u32 max_rate;
624 u8 rsvd2[8];
625};
626
627struct hinic_tx_rate_cfg {
628 u8 status;
629 u8 version;
630 u8 rsvd0[6];
631
632 u16 func_id;
633 u16 rsvd1;
634 u32 tx_rate;
635};
636
637enum nic_speed_level {
638 LINK_SPEED_10MB = 0,
639 LINK_SPEED_100MB,
640 LINK_SPEED_1GB,
641 LINK_SPEED_10GB,
642 LINK_SPEED_25GB,
643 LINK_SPEED_40GB,
644 LINK_SPEED_100GB,
645 LINK_SPEED_LEVELS,
646};
647
648struct hinic_spoofchk_set {
649 u8 status;
650 u8 version;
651 u8 rsvd0[6];
652
653 u8 state;
654 u8 rsvd1;
655 u16 func_id;
656};
657
658struct hinic_pause_config {
659 u8 status;
660 u8 version;
661 u8 rsvd0[6];
662
663 u16 func_id;
664 u16 rsvd1;
665 u32 auto_neg;
666 u32 rx_pause;
667 u32 tx_pause;
668};
669
670struct hinic_set_pfc {
671 u8 status;
672 u8 version;
673 u8 rsvd0[6];
674
675 u16 func_id;
676 u8 pfc_en;
677 u8 pfc_bitmap;
678 u8 rsvd1[4];
679};
680
681
682#define HINIC_INTERNAL_LP_MODE 5
683#define LOOP_MODE_MIN 1
684#define LOOP_MODE_MAX 6
685
686struct hinic_port_loopback {
687 u8 status;
688 u8 version;
689 u8 rsvd[6];
690
691 u32 mode;
692 u32 en;
693};
694
695struct hinic_led_info {
696 u8 status;
697 u8 version;
698 u8 rsvd0[6];
699
700 u8 port;
701 u8 type;
702 u8 mode;
703 u8 reset;
704};
705
706#define STD_SFP_INFO_MAX_SIZE 640
707
708struct hinic_cmd_get_light_module_abs {
709 u8 status;
710 u8 version;
711 u8 rsvd0[6];
712
713 u8 port_id;
714 u8 abs_status;
715 u8 rsv[2];
716};
717
718#define STD_SFP_INFO_MAX_SIZE 640
719
720struct hinic_cmd_get_std_sfp_info {
721 u8 status;
722 u8 version;
723 u8 rsvd0[6];
724
725 u8 port_id;
726 u8 wire_type;
727 u16 eeprom_len;
728 u32 rsvd;
729 u8 sfp_info[STD_SFP_INFO_MAX_SIZE];
730};
731
732struct hinic_cmd_update_fw {
733 u8 status;
734 u8 version;
735 u8 rsvd0[6];
736
737 struct {
738 u32 SL:1;
739 u32 SF:1;
740 u32 flag:1;
741 u32 reserved:13;
742 u32 fragment_len:16;
743 } ctl_info;
744
745 struct {
746 u32 FW_section_CRC;
747 u32 FW_section_type;
748 } section_info;
749
750 u32 total_len;
751 u32 setion_total_len;
752 u32 fw_section_version;
753 u32 section_offset;
754 u32 data[384];
755};
756
757int hinic_port_add_mac(struct hinic_dev *nic_dev, const u8 *addr,
758 u16 vlan_id);
759
760int hinic_port_del_mac(struct hinic_dev *nic_dev, const u8 *addr,
761 u16 vlan_id);
762
763int hinic_port_get_mac(struct hinic_dev *nic_dev, u8 *addr);
764
765int hinic_port_set_mtu(struct hinic_dev *nic_dev, int new_mtu);
766
767int hinic_port_add_vlan(struct hinic_dev *nic_dev, u16 vlan_id);
768
769int hinic_port_del_vlan(struct hinic_dev *nic_dev, u16 vlan_id);
770
771int hinic_port_set_rx_mode(struct hinic_dev *nic_dev, u32 rx_mode);
772
773int hinic_port_link_state(struct hinic_dev *nic_dev,
774 enum hinic_port_link_state *link_state);
775
776int hinic_port_set_state(struct hinic_dev *nic_dev,
777 enum hinic_port_state state);
778
779int hinic_port_set_func_state(struct hinic_dev *nic_dev,
780 enum hinic_func_port_state state);
781
782int hinic_port_get_cap(struct hinic_dev *nic_dev,
783 struct hinic_port_cap *port_cap);
784
785int hinic_set_max_qnum(struct hinic_dev *nic_dev, u8 num_rqs);
786
787int hinic_port_set_tso(struct hinic_dev *nic_dev, enum hinic_tso_state state);
788
789int hinic_set_rx_csum_offload(struct hinic_dev *nic_dev, u32 en);
790
791int hinic_set_rx_lro_state(struct hinic_dev *nic_dev, u8 lro_en,
792 u32 lro_timer, u32 wqe_num);
793
794int hinic_set_rss_type(struct hinic_dev *nic_dev, u32 tmpl_idx,
795 struct hinic_rss_type rss_type);
796
797int hinic_rss_set_indir_tbl(struct hinic_dev *nic_dev, u32 tmpl_idx,
798 const u32 *indir_table);
799
800int hinic_rss_set_template_tbl(struct hinic_dev *nic_dev, u32 template_id,
801 const u8 *temp);
802
803int hinic_rss_set_hash_engine(struct hinic_dev *nic_dev, u8 template_id,
804 u8 type);
805
806int hinic_rss_cfg(struct hinic_dev *nic_dev, u8 rss_en, u8 template_id);
807
808int hinic_rss_template_alloc(struct hinic_dev *nic_dev, u8 *tmpl_idx);
809
810int hinic_rss_template_free(struct hinic_dev *nic_dev, u8 tmpl_idx);
811
812void hinic_set_ethtool_ops(struct net_device *netdev);
813
814int hinic_get_rss_type(struct hinic_dev *nic_dev, u32 tmpl_idx,
815 struct hinic_rss_type *rss_type);
816
817int hinic_rss_get_indir_tbl(struct hinic_dev *nic_dev, u32 tmpl_idx,
818 u32 *indir_table);
819
820int hinic_rss_get_template_tbl(struct hinic_dev *nic_dev, u32 tmpl_idx,
821 u8 *temp);
822
823int hinic_rss_get_hash_engine(struct hinic_dev *nic_dev, u8 tmpl_idx,
824 u8 *type);
825
826int hinic_get_phy_port_stats(struct hinic_dev *nic_dev,
827 struct hinic_phy_port_stats *stats);
828
829int hinic_get_vport_stats(struct hinic_dev *nic_dev,
830 struct hinic_vport_stats *stats);
831
832int hinic_set_rx_vlan_offload(struct hinic_dev *nic_dev, u8 en);
833
834int hinic_get_mgmt_version(struct hinic_dev *nic_dev, u8 *mgmt_ver);
835
836int hinic_set_link_settings(struct hinic_hwdev *hwdev,
837 struct hinic_link_ksettings_info *info);
838
839int hinic_get_link_mode(struct hinic_hwdev *hwdev,
840 struct hinic_link_mode_cmd *link_mode);
841
842int hinic_set_autoneg(struct hinic_hwdev *hwdev, bool enable);
843
844int hinic_set_speed(struct hinic_hwdev *hwdev, enum nic_speed_level speed);
845
846int hinic_get_hw_pause_info(struct hinic_hwdev *hwdev,
847 struct hinic_pause_config *pause_info);
848
849int hinic_set_hw_pause_info(struct hinic_hwdev *hwdev,
850 struct hinic_pause_config *pause_info);
851
852int hinic_dcb_set_pfc(struct hinic_hwdev *hwdev, u8 pfc_en, u8 pfc_bitmap);
853
854int hinic_set_loopback_mode(struct hinic_hwdev *hwdev, u32 mode, u32 enable);
855
856enum hinic_led_mode {
857 HINIC_LED_MODE_ON,
858 HINIC_LED_MODE_OFF,
859 HINIC_LED_MODE_FORCE_1HZ,
860 HINIC_LED_MODE_FORCE_2HZ,
861 HINIC_LED_MODE_FORCE_4HZ,
862 HINIC_LED_MODE_1HZ,
863 HINIC_LED_MODE_2HZ,
864 HINIC_LED_MODE_4HZ,
865 HINIC_LED_MODE_INVALID,
866};
867
868enum hinic_led_type {
869 HINIC_LED_TYPE_LINK,
870 HINIC_LED_TYPE_LOW_SPEED,
871 HINIC_LED_TYPE_HIGH_SPEED,
872 HINIC_LED_TYPE_INVALID,
873};
874
875int hinic_reset_led_status(struct hinic_hwdev *hwdev, u8 port);
876
877int hinic_set_led_status(struct hinic_hwdev *hwdev, u8 port,
878 enum hinic_led_type type, enum hinic_led_mode mode);
879
880int hinic_get_sfp_type(struct hinic_hwdev *hwdev, u8 *data0, u8 *data1);
881
882int hinic_get_sfp_eeprom(struct hinic_hwdev *hwdev, u8 *data, u16 *len);
883
884int hinic_open(struct net_device *netdev);
885
886int hinic_close(struct net_device *netdev);
887
888#endif
889
