LXR linux/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
   4 */
   5
   6#include <linux/adreno-smmu-priv.h>
   7#include <linux/of_device.h>
   8#include <linux/qcom_scm.h>
   9
  10#include "arm-smmu.h"
  11
  12struct qcom_smmu {
  13        struct arm_smmu_device smmu;
  14        bool bypass_quirk;
  15        u8 bypass_cbndx;
  16};
  17
  18static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
  19{
  20        return container_of(smmu, struct qcom_smmu, smmu);
  21}
  22
  23static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx,
  24                u32 reg)
  25{
  26        /*
  27         * On the GPU device we want to process subsequent transactions after a
  28         * fault to keep the GPU from hanging
  29         */
  30        reg |= ARM_SMMU_SCTLR_HUPCF;
  31
  32        arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg);
  33}
  34
  35#define QCOM_ADRENO_SMMU_GPU_SID 0
  36
  37static bool qcom_adreno_smmu_is_gpu_device(struct device *dev)
  38{
  39        struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
  40        int i;
  41
  42        /*
  43         * The GPU will always use SID 0 so that is a handy way to uniquely
  44         * identify it and configure it for per-instance pagetables
  45         */
  46        for (i = 0; i < fwspec->num_ids; i++) {
  47                u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]);
  48
  49                if (sid == QCOM_ADRENO_SMMU_GPU_SID)
  50                        return true;
  51        }
  52
  53        return false;
  54}
  55
  56static const struct io_pgtable_cfg *qcom_adreno_smmu_get_ttbr1_cfg(
  57                const void *cookie)
  58{
  59        struct arm_smmu_domain *smmu_domain = (void *)cookie;
  60        struct io_pgtable *pgtable =
  61                io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);
  62        return &pgtable->cfg;
  63}
  64
  65/*
  66 * Local implementation to configure TTBR0 with the specified pagetable config.
  67 * The GPU driver will call this to enable TTBR0 when per-instance pagetables
  68 * are active
  69 */
  70
  71static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie,
  72                const struct io_pgtable_cfg *pgtbl_cfg)
  73{
  74        struct arm_smmu_domain *smmu_domain = (void *)cookie;
  75        struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);
  76        struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
  77        struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx];
  78
  79        /* The domain must have split pagetables already enabled */
  80        if (cb->tcr[0] & ARM_SMMU_TCR_EPD1)
  81                return -EINVAL;
  82
  83        /* If the pagetable config is NULL, disable TTBR0 */
  84        if (!pgtbl_cfg) {
  85                /* Do nothing if it is already disabled */
  86                if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0))
  87                        return -EINVAL;
  88
  89                /* Set TCR to the original configuration */
  90                cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg);
  91                cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
  92        } else {
  93                u32 tcr = cb->tcr[0];
  94
  95                /* Don't call this again if TTBR0 is already enabled */
  96                if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0))
  97                        return -EINVAL;
  98
  99                tcr |= arm_smmu_lpae_tcr(pgtbl_cfg);
 100                tcr &= ~(ARM_SMMU_TCR_EPD0 | ARM_SMMU_TCR_EPD1);
 101
 102                cb->tcr[0] = tcr;
 103                cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
 104                cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
 105        }
 106
 107        arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx);
 108
 109        return 0;
 110}
 111
 112static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain,
 113                                               struct arm_smmu_device *smmu,
 114                                               struct device *dev, int start)
 115{
 116        int count;
 117
 118        /*
 119         * Assign context bank 0 to the GPU device so the GPU hardware can
 120         * switch pagetables
 121         */
 122        if (qcom_adreno_smmu_is_gpu_device(dev)) {
 123                start = 0;
 124                count = 1;
 125        } else {
 126                start = 1;
 127                count = smmu->num_context_banks;
 128        }
 129
 130        return __arm_smmu_alloc_bitmap(smmu->context_map, start, count);
 131}
 132
 133static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu)
 134{
 135        const struct device_node *np = smmu->dev->of_node;
 136
 137        if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2"))
 138                return false;
 139
 140        return true;
 141}
 142
 143static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
 144                struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
 145{
 146        struct adreno_smmu_priv *priv;
 147
 148        /* Only enable split pagetables for the GPU device (SID 0) */
 149        if (!qcom_adreno_smmu_is_gpu_device(dev))
 150                return 0;
 151
 152        /*
 153         * All targets that use the qcom,adreno-smmu compatible string *should*
 154         * be AARCH64 stage 1 but double check because the arm-smmu code assumes
 155         * that is the case when the TTBR1 quirk is enabled
 156         */
 157        if (qcom_adreno_can_do_ttbr1(smmu_domain->smmu) &&
 158            (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) &&
 159            (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64))
 160                pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1;
 161
 162        /*
 163         * Initialize private interface with GPU:
 164         */
 165
 166        priv = dev_get_drvdata(dev);
 167        priv->cookie = smmu_domain;
 168        priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg;
 169        priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg;
 170
 171        return 0;
 172}
 173
 174static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
 175        { .compatible = "qcom,adreno" },
 176        { .compatible = "qcom,mdp4" },
 177        { .compatible = "qcom,mdss" },
 178        { .compatible = "qcom,sc7180-mdss" },
 179        { .compatible = "qcom,sc7180-mss-pil" },
 180        { .compatible = "qcom,sc8180x-mdss" },
 181        { .compatible = "qcom,sdm845-mdss" },
 182        { .compatible = "qcom,sdm845-mss-pil" },
 183        { }
 184};
 185
 186static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu)
 187{
 188        unsigned int last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1);
 189        struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
 190        u32 reg;
 191        u32 smr;
 192        int i;
 193
 194        /*
 195         * With some firmware versions writes to S2CR of type FAULT are
 196         * ignored, and writing BYPASS will end up written as FAULT in the
 197         * register. Perform a write to S2CR to detect if this is the case and
 198         * if so reserve a context bank to emulate bypass streams.
 199         */
 200        reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, S2CR_TYPE_BYPASS) |
 201              FIELD_PREP(ARM_SMMU_S2CR_CBNDX, 0xff) |
 202              FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, S2CR_PRIVCFG_DEFAULT);
 203        arm_smmu_gr0_write(smmu, last_s2cr, reg);
 204        reg = arm_smmu_gr0_read(smmu, last_s2cr);
 205        if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) {
 206                qsmmu->bypass_quirk = true;
 207                qsmmu->bypass_cbndx = smmu->num_context_banks - 1;
 208
 209                set_bit(qsmmu->bypass_cbndx, smmu->context_map);
 210
 211                arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0);
 212
 213                reg = FIELD_PREP(ARM_SMMU_CBAR_TYPE, CBAR_TYPE_S1_TRANS_S2_BYPASS);
 214                arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg);
 215        }
 216
 217        for (i = 0; i < smmu->num_mapping_groups; i++) {
 218                smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i));
 219
 220                if (FIELD_GET(ARM_SMMU_SMR_VALID, smr)) {
 221                        /* Ignore valid bit for SMR mask extraction. */
 222                        smr &= ~ARM_SMMU_SMR_VALID;
 223                        smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr);
 224                        smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr);
 225                        smmu->smrs[i].valid = true;
 226
 227                        smmu->s2crs[i].type = S2CR_TYPE_BYPASS;
 228                        smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT;
 229                        smmu->s2crs[i].cbndx = 0xff;
 230                }
 231        }
 232
 233        return 0;
 234}
 235
 236static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx)
 237{
 238        struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx;
 239        struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
 240        u32 cbndx = s2cr->cbndx;
 241        u32 type = s2cr->type;
 242        u32 reg;
 243
 244        if (qsmmu->bypass_quirk) {
 245                if (type == S2CR_TYPE_BYPASS) {
 246                        /*
 247                         * Firmware with quirky S2CR handling will substitute
 248                         * BYPASS writes with FAULT, so point the stream to the
 249                         * reserved context bank and ask for translation on the
 250                         * stream
 251                         */
 252                        type = S2CR_TYPE_TRANS;
 253                        cbndx = qsmmu->bypass_cbndx;
 254                } else if (type == S2CR_TYPE_FAULT) {
 255                        /*
 256                         * Firmware with quirky S2CR handling will ignore FAULT
 257                         * writes, so trick it to write FAULT by asking for a
 258                         * BYPASS.
 259                         */
 260                        type = S2CR_TYPE_BYPASS;
 261                        cbndx = 0xff;
 262                }
 263        }
 264
 265        reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, type) |
 266              FIELD_PREP(ARM_SMMU_S2CR_CBNDX, cbndx) |
 267              FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg);
 268        arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg);
 269}
 270
 271static int qcom_smmu_def_domain_type(struct device *dev)
 272{
 273        const struct of_device_id *match =
 274                of_match_device(qcom_smmu_client_of_match, dev);
 275
 276        return match ? IOMMU_DOMAIN_IDENTITY : 0;
 277}
 278
 279static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
 280{
 281        int ret;
 282
 283        /*
 284         * To address performance degradation in non-real time clients,
 285         * such as USB and UFS, turn off wait-for-safe on sdm845 based boards,
 286         * such as MTP and db845, whose firmwares implement secure monitor
 287         * call handlers to turn on/off the wait-for-safe logic.
 288         */
 289        ret = qcom_scm_qsmmu500_wait_safe_toggle(0);
 290        if (ret)
 291                dev_warn(smmu->dev, "Failed to turn off SAFE logic\n");
 292
 293        return ret;
 294}
 295
 296static int qcom_smmu500_reset(struct arm_smmu_device *smmu)
 297{
 298        const struct device_node *np = smmu->dev->of_node;
 299
 300        arm_mmu500_reset(smmu);
 301
 302        if (of_device_is_compatible(np, "qcom,sdm845-smmu-500"))
 303                return qcom_sdm845_smmu500_reset(smmu);
 304
 305        return 0;
 306}
 307
 308static const struct arm_smmu_impl qcom_smmu_impl = {
 309        .cfg_probe = qcom_smmu_cfg_probe,
 310        .def_domain_type = qcom_smmu_def_domain_type,
 311        .reset = qcom_smmu500_reset,
 312        .write_s2cr = qcom_smmu_write_s2cr,
 313};
 314
 315static const struct arm_smmu_impl qcom_adreno_smmu_impl = {
 316        .init_context = qcom_adreno_smmu_init_context,
 317        .def_domain_type = qcom_smmu_def_domain_type,
 318        .reset = qcom_smmu500_reset,
 319        .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
 320        .write_sctlr = qcom_adreno_smmu_write_sctlr,
 321};
 322
 323static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,
 324                const struct arm_smmu_impl *impl)
 325{
 326        struct qcom_smmu *qsmmu;
 327
 328        /* Check to make sure qcom_scm has finished probing */
 329        if (!qcom_scm_is_available())
 330                return ERR_PTR(-EPROBE_DEFER);
 331
 332        qsmmu = devm_krealloc(smmu->dev, smmu, sizeof(*qsmmu), GFP_KERNEL);
 333        if (!qsmmu)
 334                return ERR_PTR(-ENOMEM);
 335
 336        qsmmu->smmu.impl = impl;
 337
 338        return &qsmmu->smmu;
 339}
 340
 341static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
 342        { .compatible = "qcom,msm8998-smmu-v2" },
 343        { .compatible = "qcom,sc7180-smmu-500" },
 344        { .compatible = "qcom,sc8180x-smmu-500" },
 345        { .compatible = "qcom,sdm630-smmu-v2" },
 346        { .compatible = "qcom,sdm845-smmu-500" },
 347        { .compatible = "qcom,sm8150-smmu-500" },
 348        { .compatible = "qcom,sm8250-smmu-500" },
 349        { .compatible = "qcom,sm8350-smmu-500" },
 350        { }
 351};
 352
 353struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
 354{
 355        const struct device_node *np = smmu->dev->of_node;
 356
 357        if (of_match_node(qcom_smmu_impl_of_match, np))
 358                return qcom_smmu_create(smmu, &qcom_smmu_impl);
 359
 360        if (of_device_is_compatible(np, "qcom,adreno-smmu"))
 361                return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl);
 362
 363        return smmu;
 364}
 365