linux/arch/arm/plat-omap/dma.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * linux/arch/arm/plat-omap/dma.c
   4 *
   5 * Copyright (C) 2003 - 2008 Nokia Corporation
   6 * Author: Juha Yrj\xC3\xB6l\xC3\xA4 <juha.yrjola@nokia.com>
   7 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
   8 * Graphics DMA and LCD DMA graphics tranformations
   9 * by Imre Deak <imre.deak@nokia.com>
  10 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
  11 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
  12 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  13 *
  14 * Copyright (C) 2009 Texas Instruments
  15 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  16 *
  17 * Support functions for the OMAP internal DMA channels.
  18 *
  19 * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
  20 * Converted DMA library into DMA platform driver.
  21 *      - G, Manjunath Kondaiah <manjugk@ti.com>
  22 */
  23
  24#include <linux/module.h>
  25#include <linux/init.h>
  26#include <linux/sched.h>
  27#include <linux/spinlock.h>
  28#include <linux/errno.h>
  29#include <linux/interrupt.h>
  30#include <linux/irq.h>
  31#include <linux/io.h>
  32#include <linux/slab.h>
  33#include <linux/delay.h>
  34
  35#include <linux/omap-dma.h>
  36
  37#ifdef CONFIG_ARCH_OMAP1
  38#include <mach/soc.h>
  39#endif
  40
  41/*
  42 * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA
  43 * channels that an instance of the SDMA IP block can support.  Used
  44 * to size arrays.  (The actual maximum on a particular SoC may be less
  45 * than this -- for example, OMAP1 SDMA instances only support 17 logical
  46 * DMA channels.)
  47 */
  48#define MAX_LOGICAL_DMA_CH_COUNT                32
  49
  50#undef DEBUG
  51
  52#ifndef CONFIG_ARCH_OMAP1
  53enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
  54        DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
  55};
  56
  57enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
  58#endif
  59
  60#define OMAP_DMA_ACTIVE                 0x01
  61#define OMAP2_DMA_CSR_CLEAR_MASK        0xffffffff
  62
  63#define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
  64
  65static struct omap_system_dma_plat_info *p;
  66static struct omap_dma_dev_attr *d;
  67static void omap_clear_dma(int lch);
  68static int enable_1510_mode;
  69static u32 errata;
  70
  71struct dma_link_info {
  72        int *linked_dmach_q;
  73        int no_of_lchs_linked;
  74
  75        int q_count;
  76        int q_tail;
  77        int q_head;
  78
  79        int chain_state;
  80        int chain_mode;
  81
  82};
  83
  84static int dma_lch_count;
  85static int dma_chan_count;
  86static int omap_dma_reserve_channels;
  87
  88static DEFINE_SPINLOCK(dma_chan_lock);
  89static struct omap_dma_lch *dma_chan;
  90
  91static inline void disable_lnk(int lch);
  92static void omap_disable_channel_irq(int lch);
  93static inline void omap_enable_channel_irq(int lch);
  94
  95#ifdef CONFIG_ARCH_OMAP15XX
  96/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
  97static int omap_dma_in_1510_mode(void)
  98{
  99        return enable_1510_mode;
 100}
 101#else
 102#define omap_dma_in_1510_mode()         0
 103#endif
 104
 105#ifdef CONFIG_ARCH_OMAP1
 106static inline void set_gdma_dev(int req, int dev)
 107{
 108        u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 109        int shift = ((req - 1) % 5) * 6;
 110        u32 l;
 111
 112        l = omap_readl(reg);
 113        l &= ~(0x3f << shift);
 114        l |= (dev - 1) << shift;
 115        omap_writel(l, reg);
 116}
 117#else
 118#define set_gdma_dev(req, dev)  do {} while (0)
 119#define omap_readl(reg)         0
 120#define omap_writel(val, reg)   do {} while (0)
 121#endif
 122
 123#ifdef CONFIG_ARCH_OMAP1
 124void omap_set_dma_priority(int lch, int dst_port, int priority)
 125{
 126        unsigned long reg;
 127        u32 l;
 128
 129        if (dma_omap1()) {
 130                switch (dst_port) {
 131                case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
 132                        reg = OMAP_TC_OCPT1_PRIOR;
 133                        break;
 134                case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
 135                        reg = OMAP_TC_OCPT2_PRIOR;
 136                        break;
 137                case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
 138                        reg = OMAP_TC_EMIFF_PRIOR;
 139                        break;
 140                case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
 141                        reg = OMAP_TC_EMIFS_PRIOR;
 142                        break;
 143                default:
 144                        BUG();
 145                        return;
 146                }
 147                l = omap_readl(reg);
 148                l &= ~(0xf << 8);
 149                l |= (priority & 0xf) << 8;
 150                omap_writel(l, reg);
 151        }
 152}
 153#endif
 154
 155#ifdef CONFIG_ARCH_OMAP2PLUS
 156void omap_set_dma_priority(int lch, int dst_port, int priority)
 157{
 158        u32 ccr;
 159
 160        ccr = p->dma_read(CCR, lch);
 161        if (priority)
 162                ccr |= (1 << 6);
 163        else
 164                ccr &= ~(1 << 6);
 165        p->dma_write(ccr, CCR, lch);
 166}
 167#endif
 168EXPORT_SYMBOL(omap_set_dma_priority);
 169
 170void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
 171                                  int frame_count, int sync_mode,
 172                                  int dma_trigger, int src_or_dst_synch)
 173{
 174        u32 l;
 175
 176        l = p->dma_read(CSDP, lch);
 177        l &= ~0x03;
 178        l |= data_type;
 179        p->dma_write(l, CSDP, lch);
 180
 181        if (dma_omap1()) {
 182                u16 ccr;
 183
 184                ccr = p->dma_read(CCR, lch);
 185                ccr &= ~(1 << 5);
 186                if (sync_mode == OMAP_DMA_SYNC_FRAME)
 187                        ccr |= 1 << 5;
 188                p->dma_write(ccr, CCR, lch);
 189
 190                ccr = p->dma_read(CCR2, lch);
 191                ccr &= ~(1 << 2);
 192                if (sync_mode == OMAP_DMA_SYNC_BLOCK)
 193                        ccr |= 1 << 2;
 194                p->dma_write(ccr, CCR2, lch);
 195        }
 196
 197        if (dma_omap2plus() && dma_trigger) {
 198                u32 val;
 199
 200                val = p->dma_read(CCR, lch);
 201
 202                /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
 203                val &= ~((1 << 23) | (3 << 19) | 0x1f);
 204                val |= (dma_trigger & ~0x1f) << 14;
 205                val |= dma_trigger & 0x1f;
 206
 207                if (sync_mode & OMAP_DMA_SYNC_FRAME)
 208                        val |= 1 << 5;
 209                else
 210                        val &= ~(1 << 5);
 211
 212                if (sync_mode & OMAP_DMA_SYNC_BLOCK)
 213                        val |= 1 << 18;
 214                else
 215                        val &= ~(1 << 18);
 216
 217                if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
 218                        val &= ~(1 << 24);      /* dest synch */
 219                        val |= (1 << 23);       /* Prefetch */
 220                } else if (src_or_dst_synch) {
 221                        val |= 1 << 24;         /* source synch */
 222                } else {
 223                        val &= ~(1 << 24);      /* dest synch */
 224                }
 225                p->dma_write(val, CCR, lch);
 226        }
 227
 228        p->dma_write(elem_count, CEN, lch);
 229        p->dma_write(frame_count, CFN, lch);
 230}
 231EXPORT_SYMBOL(omap_set_dma_transfer_params);
 232
 233void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
 234{
 235        if (dma_omap1() && !dma_omap15xx()) {
 236                u32 l;
 237
 238                l = p->dma_read(LCH_CTRL, lch);
 239                l &= ~0x7;
 240                l |= mode;
 241                p->dma_write(l, LCH_CTRL, lch);
 242        }
 243}
 244EXPORT_SYMBOL(omap_set_dma_channel_mode);
 245
 246/* Note that src_port is only for omap1 */
 247void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 248                             unsigned long src_start,
 249                             int src_ei, int src_fi)
 250{
 251        u32 l;
 252
 253        if (dma_omap1()) {
 254                u16 w;
 255
 256                w = p->dma_read(CSDP, lch);
 257                w &= ~(0x1f << 2);
 258                w |= src_port << 2;
 259                p->dma_write(w, CSDP, lch);
 260        }
 261
 262        l = p->dma_read(CCR, lch);
 263        l &= ~(0x03 << 12);
 264        l |= src_amode << 12;
 265        p->dma_write(l, CCR, lch);
 266
 267        p->dma_write(src_start, CSSA, lch);
 268
 269        p->dma_write(src_ei, CSEI, lch);
 270        p->dma_write(src_fi, CSFI, lch);
 271}
 272EXPORT_SYMBOL(omap_set_dma_src_params);
 273
 274void omap_set_dma_src_data_pack(int lch, int enable)
 275{
 276        u32 l;
 277
 278        l = p->dma_read(CSDP, lch);
 279        l &= ~(1 << 6);
 280        if (enable)
 281                l |= (1 << 6);
 282        p->dma_write(l, CSDP, lch);
 283}
 284EXPORT_SYMBOL(omap_set_dma_src_data_pack);
 285
 286void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 287{
 288        unsigned int burst = 0;
 289        u32 l;
 290
 291        l = p->dma_read(CSDP, lch);
 292        l &= ~(0x03 << 7);
 293
 294        switch (burst_mode) {
 295        case OMAP_DMA_DATA_BURST_DIS:
 296                break;
 297        case OMAP_DMA_DATA_BURST_4:
 298                if (dma_omap2plus())
 299                        burst = 0x1;
 300                else
 301                        burst = 0x2;
 302                break;
 303        case OMAP_DMA_DATA_BURST_8:
 304                if (dma_omap2plus()) {
 305                        burst = 0x2;
 306                        break;
 307                }
 308                /*
 309                 * not supported by current hardware on OMAP1
 310                 * w |= (0x03 << 7);
 311                 */
 312                fallthrough;
 313        case OMAP_DMA_DATA_BURST_16:
 314                if (dma_omap2plus()) {
 315                        burst = 0x3;
 316                        break;
 317                }
 318                /* OMAP1 don't support burst 16 */
 319                fallthrough;
 320        default:
 321                BUG();
 322        }
 323
 324        l |= (burst << 7);
 325        p->dma_write(l, CSDP, lch);
 326}
 327EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
 328
 329/* Note that dest_port is only for OMAP1 */
 330void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 331                              unsigned long dest_start,
 332                              int dst_ei, int dst_fi)
 333{
 334        u32 l;
 335
 336        if (dma_omap1()) {
 337                l = p->dma_read(CSDP, lch);
 338                l &= ~(0x1f << 9);
 339                l |= dest_port << 9;
 340                p->dma_write(l, CSDP, lch);
 341        }
 342
 343        l = p->dma_read(CCR, lch);
 344        l &= ~(0x03 << 14);
 345        l |= dest_amode << 14;
 346        p->dma_write(l, CCR, lch);
 347
 348        p->dma_write(dest_start, CDSA, lch);
 349
 350        p->dma_write(dst_ei, CDEI, lch);
 351        p->dma_write(dst_fi, CDFI, lch);
 352}
 353EXPORT_SYMBOL(omap_set_dma_dest_params);
 354
 355void omap_set_dma_dest_data_pack(int lch, int enable)
 356{
 357        u32 l;
 358
 359        l = p->dma_read(CSDP, lch);
 360        l &= ~(1 << 13);
 361        if (enable)
 362                l |= 1 << 13;
 363        p->dma_write(l, CSDP, lch);
 364}
 365EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
 366
 367void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 368{
 369        unsigned int burst = 0;
 370        u32 l;
 371
 372        l = p->dma_read(CSDP, lch);
 373        l &= ~(0x03 << 14);
 374
 375        switch (burst_mode) {
 376        case OMAP_DMA_DATA_BURST_DIS:
 377                break;
 378        case OMAP_DMA_DATA_BURST_4:
 379                if (dma_omap2plus())
 380                        burst = 0x1;
 381                else
 382                        burst = 0x2;
 383                break;
 384        case OMAP_DMA_DATA_BURST_8:
 385                if (dma_omap2plus())
 386                        burst = 0x2;
 387                else
 388                        burst = 0x3;
 389                break;
 390        case OMAP_DMA_DATA_BURST_16:
 391                if (dma_omap2plus()) {
 392                        burst = 0x3;
 393                        break;
 394                }
 395                /* OMAP1 don't support burst 16 */
 396                fallthrough;
 397        default:
 398                printk(KERN_ERR "Invalid DMA burst mode\n");
 399                BUG();
 400                return;
 401        }
 402        l |= (burst << 14);
 403        p->dma_write(l, CSDP, lch);
 404}
 405EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 406
 407static inline void omap_enable_channel_irq(int lch)
 408{
 409        /* Clear CSR */
 410        if (dma_omap1())
 411                p->dma_read(CSR, lch);
 412        else
 413                p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
 414
 415        /* Enable some nice interrupts. */
 416        p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
 417}
 418
 419static inline void omap_disable_channel_irq(int lch)
 420{
 421        /* disable channel interrupts */
 422        p->dma_write(0, CICR, lch);
 423        /* Clear CSR */
 424        if (dma_omap1())
 425                p->dma_read(CSR, lch);
 426        else
 427                p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
 428}
 429
 430void omap_disable_dma_irq(int lch, u16 bits)
 431{
 432        dma_chan[lch].enabled_irqs &= ~bits;
 433}
 434EXPORT_SYMBOL(omap_disable_dma_irq);
 435
 436static inline void enable_lnk(int lch)
 437{
 438        u32 l;
 439
 440        l = p->dma_read(CLNK_CTRL, lch);
 441
 442        if (dma_omap1())
 443                l &= ~(1 << 14);
 444
 445        /* Set the ENABLE_LNK bits */
 446        if (dma_chan[lch].next_lch != -1)
 447                l = dma_chan[lch].next_lch | (1 << 15);
 448
 449        p->dma_write(l, CLNK_CTRL, lch);
 450}
 451
 452static inline void disable_lnk(int lch)
 453{
 454        u32 l;
 455
 456        l = p->dma_read(CLNK_CTRL, lch);
 457
 458        /* Disable interrupts */
 459        omap_disable_channel_irq(lch);
 460
 461        if (dma_omap1()) {
 462                /* Set the STOP_LNK bit */
 463                l |= 1 << 14;
 464        }
 465
 466        if (dma_omap2plus()) {
 467                /* Clear the ENABLE_LNK bit */
 468                l &= ~(1 << 15);
 469        }
 470
 471        p->dma_write(l, CLNK_CTRL, lch);
 472        dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 473}
 474
 475int omap_request_dma(int dev_id, const char *dev_name,
 476                     void (*callback)(int lch, u16 ch_status, void *data),
 477                     void *data, int *dma_ch_out)
 478{
 479        int ch, free_ch = -1;
 480        unsigned long flags;
 481        struct omap_dma_lch *chan;
 482
 483        WARN(strcmp(dev_name, "DMA engine"), "Using deprecated platform DMA API - please update to DMA engine");
 484
 485        spin_lock_irqsave(&dma_chan_lock, flags);
 486        for (ch = 0; ch < dma_chan_count; ch++) {
 487                if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
 488                        free_ch = ch;
 489                        /* Exit after first free channel found */
 490                        break;
 491                }
 492        }
 493        if (free_ch == -1) {
 494                spin_unlock_irqrestore(&dma_chan_lock, flags);
 495                return -EBUSY;
 496        }
 497        chan = dma_chan + free_ch;
 498        chan->dev_id = dev_id;
 499
 500        if (p->clear_lch_regs)
 501                p->clear_lch_regs(free_ch);
 502
 503        spin_unlock_irqrestore(&dma_chan_lock, flags);
 504
 505        chan->dev_name = dev_name;
 506        chan->callback = callback;
 507        chan->data = data;
 508        chan->flags = 0;
 509
 510        chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 511
 512        if (dma_omap1())
 513                chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
 514
 515        if (dma_omap16xx()) {
 516                /* If the sync device is set, configure it dynamically. */
 517                if (dev_id != 0) {
 518                        set_gdma_dev(free_ch + 1, dev_id);
 519                        dev_id = free_ch + 1;
 520                }
 521                /*
 522                 * Disable the 1510 compatibility mode and set the sync device
 523                 * id.
 524                 */
 525                p->dma_write(dev_id | (1 << 10), CCR, free_ch);
 526        } else if (dma_omap1()) {
 527                p->dma_write(dev_id, CCR, free_ch);
 528        }
 529
 530        *dma_ch_out = free_ch;
 531
 532        return 0;
 533}
 534EXPORT_SYMBOL(omap_request_dma);
 535
 536void omap_free_dma(int lch)
 537{
 538        unsigned long flags;
 539
 540        if (dma_chan[lch].dev_id == -1) {
 541                pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
 542                       lch);
 543                return;
 544        }
 545
 546        /* Disable all DMA interrupts for the channel. */
 547        omap_disable_channel_irq(lch);
 548
 549        /* Make sure the DMA transfer is stopped. */
 550        p->dma_write(0, CCR, lch);
 551
 552        spin_lock_irqsave(&dma_chan_lock, flags);
 553        dma_chan[lch].dev_id = -1;
 554        dma_chan[lch].next_lch = -1;
 555        dma_chan[lch].callback = NULL;
 556        spin_unlock_irqrestore(&dma_chan_lock, flags);
 557}
 558EXPORT_SYMBOL(omap_free_dma);
 559
 560/*
 561 * Clears any DMA state so the DMA engine is ready to restart with new buffers
 562 * through omap_start_dma(). Any buffers in flight are discarded.
 563 */
 564static void omap_clear_dma(int lch)
 565{
 566        unsigned long flags;
 567
 568        local_irq_save(flags);
 569        p->clear_dma(lch);
 570        local_irq_restore(flags);
 571}
 572
 573void omap_start_dma(int lch)
 574{
 575        u32 l;
 576
 577        /*
 578         * The CPC/CDAC register needs to be initialized to zero
 579         * before starting dma transfer.
 580         */
 581        if (dma_omap15xx())
 582                p->dma_write(0, CPC, lch);
 583        else
 584                p->dma_write(0, CDAC, lch);
 585
 586        if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 587                int next_lch, cur_lch;
 588                char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
 589
 590                /* Set the link register of the first channel */
 591                enable_lnk(lch);
 592
 593                memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 594                dma_chan_link_map[lch] = 1;
 595
 596                cur_lch = dma_chan[lch].next_lch;
 597                do {
 598                        next_lch = dma_chan[cur_lch].next_lch;
 599
 600                        /* The loop case: we've been here already */
 601                        if (dma_chan_link_map[cur_lch])
 602                                break;
 603                        /* Mark the current channel */
 604                        dma_chan_link_map[cur_lch] = 1;
 605
 606                        enable_lnk(cur_lch);
 607                        omap_enable_channel_irq(cur_lch);
 608
 609                        cur_lch = next_lch;
 610                } while (next_lch != -1);
 611        } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
 612                p->dma_write(lch, CLNK_CTRL, lch);
 613
 614        omap_enable_channel_irq(lch);
 615
 616        l = p->dma_read(CCR, lch);
 617
 618        if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
 619                        l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
 620        l |= OMAP_DMA_CCR_EN;
 621
 622        /*
 623         * As dma_write() uses IO accessors which are weakly ordered, there
 624         * is no guarantee that data in coherent DMA memory will be visible
 625         * to the DMA device.  Add a memory barrier here to ensure that any
 626         * such data is visible prior to enabling DMA.
 627         */
 628        mb();
 629        p->dma_write(l, CCR, lch);
 630
 631        dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 632}
 633EXPORT_SYMBOL(omap_start_dma);
 634
 635void omap_stop_dma(int lch)
 636{
 637        u32 l;
 638
 639        /* Disable all interrupts on the channel */
 640        omap_disable_channel_irq(lch);
 641
 642        l = p->dma_read(CCR, lch);
 643        if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
 644                        (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
 645                int i = 0;
 646                u32 sys_cf;
 647
 648                /* Configure No-Standby */
 649                l = p->dma_read(OCP_SYSCONFIG, lch);
 650                sys_cf = l;
 651                l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
 652                l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
 653                p->dma_write(l , OCP_SYSCONFIG, 0);
 654
 655                l = p->dma_read(CCR, lch);
 656                l &= ~OMAP_DMA_CCR_EN;
 657                p->dma_write(l, CCR, lch);
 658
 659                /* Wait for sDMA FIFO drain */
 660                l = p->dma_read(CCR, lch);
 661                while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
 662                                        OMAP_DMA_CCR_WR_ACTIVE))) {
 663                        udelay(5);
 664                        i++;
 665                        l = p->dma_read(CCR, lch);
 666                }
 667                if (i >= 100)
 668                        pr_err("DMA drain did not complete on lch %d\n", lch);
 669                /* Restore OCP_SYSCONFIG */
 670                p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
 671        } else {
 672                l &= ~OMAP_DMA_CCR_EN;
 673                p->dma_write(l, CCR, lch);
 674        }
 675
 676        /*
 677         * Ensure that data transferred by DMA is visible to any access
 678         * after DMA has been disabled.  This is important for coherent
 679         * DMA regions.
 680         */
 681        mb();
 682
 683        if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 684                int next_lch, cur_lch = lch;
 685                char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
 686
 687                memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 688                do {
 689                        /* The loop case: we've been here already */
 690                        if (dma_chan_link_map[cur_lch])
 691                                break;
 692                        /* Mark the current channel */
 693                        dma_chan_link_map[cur_lch] = 1;
 694
 695                        disable_lnk(cur_lch);
 696
 697                        next_lch = dma_chan[cur_lch].next_lch;
 698                        cur_lch = next_lch;
 699                } while (next_lch != -1);
 700        }
 701
 702        dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 703}
 704EXPORT_SYMBOL(omap_stop_dma);
 705
 706/*
 707 * Allows changing the DMA callback function or data. This may be needed if
 708 * the driver shares a single DMA channel for multiple dma triggers.
 709 */
 710/*
 711 * Returns current physical source address for the given DMA channel.
 712 * If the channel is running the caller must disable interrupts prior calling
 713 * this function and process the returned value before re-enabling interrupt to
 714 * prevent races with the interrupt handler. Note that in continuous mode there
 715 * is a chance for CSSA_L register overflow between the two reads resulting
 716 * in incorrect return value.
 717 */
 718dma_addr_t omap_get_dma_src_pos(int lch)
 719{
 720        dma_addr_t offset = 0;
 721
 722        if (dma_omap15xx())
 723                offset = p->dma_read(CPC, lch);
 724        else
 725                offset = p->dma_read(CSAC, lch);
 726
 727        if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
 728                offset = p->dma_read(CSAC, lch);
 729
 730        if (!dma_omap15xx()) {
 731                /*
 732                 * CDAC == 0 indicates that the DMA transfer on the channel has
 733                 * not been started (no data has been transferred so far).
 734                 * Return the programmed source start address in this case.
 735                 */
 736                if (likely(p->dma_read(CDAC, lch)))
 737                        offset = p->dma_read(CSAC, lch);
 738                else
 739                        offset = p->dma_read(CSSA, lch);
 740        }
 741
 742        if (dma_omap1())
 743                offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
 744
 745        return offset;
 746}
 747EXPORT_SYMBOL(omap_get_dma_src_pos);
 748
 749/*
 750 * Returns current physical destination address for the given DMA channel.
 751 * If the channel is running the caller must disable interrupts prior calling
 752 * this function and process the returned value before re-enabling interrupt to
 753 * prevent races with the interrupt handler. Note that in continuous mode there
 754 * is a chance for CDSA_L register overflow between the two reads resulting
 755 * in incorrect return value.
 756 */
 757dma_addr_t omap_get_dma_dst_pos(int lch)
 758{
 759        dma_addr_t offset = 0;
 760
 761        if (dma_omap15xx())
 762                offset = p->dma_read(CPC, lch);
 763        else
 764                offset = p->dma_read(CDAC, lch);
 765
 766        /*
 767         * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
 768         * read before the DMA controller finished disabling the channel.
 769         */
 770        if (!dma_omap15xx() && offset == 0) {
 771                offset = p->dma_read(CDAC, lch);
 772                /*
 773                 * CDAC == 0 indicates that the DMA transfer on the channel has
 774                 * not been started (no data has been transferred so far).
 775                 * Return the programmed destination start address in this case.
 776                 */
 777                if (unlikely(!offset))
 778                        offset = p->dma_read(CDSA, lch);
 779        }
 780
 781        if (dma_omap1())
 782                offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
 783
 784        return offset;
 785}
 786EXPORT_SYMBOL(omap_get_dma_dst_pos);
 787
 788int omap_get_dma_active_status(int lch)
 789{
 790        return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
 791}
 792EXPORT_SYMBOL(omap_get_dma_active_status);
 793
 794int omap_dma_running(void)
 795{
 796        int lch;
 797
 798        if (dma_omap1())
 799                if (omap_lcd_dma_running())
 800                        return 1;
 801
 802        for (lch = 0; lch < dma_chan_count; lch++)
 803                if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
 804                        return 1;
 805
 806        return 0;
 807}
 808
 809/*----------------------------------------------------------------------------*/
 810
 811#ifdef CONFIG_ARCH_OMAP1
 812
 813static int omap1_dma_handle_ch(int ch)
 814{
 815        u32 csr;
 816
 817        if (enable_1510_mode && ch >= 6) {
 818                csr = dma_chan[ch].saved_csr;
 819                dma_chan[ch].saved_csr = 0;
 820        } else
 821                csr = p->dma_read(CSR, ch);
 822        if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
 823                dma_chan[ch + 6].saved_csr = csr >> 7;
 824                csr &= 0x7f;
 825        }
 826        if ((csr & 0x3f) == 0)
 827                return 0;
 828        if (unlikely(dma_chan[ch].dev_id == -1)) {
 829                pr_warn("Spurious interrupt from DMA channel %d (CSR %04x)\n",
 830                        ch, csr);
 831                return 0;
 832        }
 833        if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
 834                pr_warn("DMA timeout with device %d\n", dma_chan[ch].dev_id);
 835        if (unlikely(csr & OMAP_DMA_DROP_IRQ))
 836                pr_warn("DMA synchronization event drop occurred with device %d\n",
 837                        dma_chan[ch].dev_id);
 838        if (likely(csr & OMAP_DMA_BLOCK_IRQ))
 839                dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
 840        if (likely(dma_chan[ch].callback != NULL))
 841                dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
 842
 843        return 1;
 844}
 845
 846static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
 847{
 848        int ch = ((int) dev_id) - 1;
 849        int handled = 0;
 850
 851        for (;;) {
 852                int handled_now = 0;
 853
 854                handled_now += omap1_dma_handle_ch(ch);
 855                if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
 856                        handled_now += omap1_dma_handle_ch(ch + 6);
 857                if (!handled_now)
 858                        break;
 859                handled += handled_now;
 860        }
 861
 862        return handled ? IRQ_HANDLED : IRQ_NONE;
 863}
 864
 865#else
 866#define omap1_dma_irq_handler   NULL
 867#endif
 868
 869struct omap_system_dma_plat_info *omap_get_plat_info(void)
 870{
 871        return p;
 872}
 873EXPORT_SYMBOL_GPL(omap_get_plat_info);
 874
 875static int omap_system_dma_probe(struct platform_device *pdev)
 876{
 877        int ch, ret = 0;
 878        int dma_irq;
 879        char irq_name[4];
 880
 881        p = pdev->dev.platform_data;
 882        if (!p) {
 883                dev_err(&pdev->dev,
 884                        "%s: System DMA initialized without platform data\n",
 885                        __func__);
 886                return -EINVAL;
 887        }
 888
 889        d                       = p->dma_attr;
 890        errata                  = p->errata;
 891
 892        if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
 893                        && (omap_dma_reserve_channels < d->lch_count))
 894                d->lch_count    = omap_dma_reserve_channels;
 895
 896        dma_lch_count           = d->lch_count;
 897        dma_chan_count          = dma_lch_count;
 898        enable_1510_mode        = d->dev_caps & ENABLE_1510_MODE;
 899
 900        dma_chan = devm_kcalloc(&pdev->dev, dma_lch_count,
 901                                sizeof(*dma_chan), GFP_KERNEL);
 902        if (!dma_chan)
 903                return -ENOMEM;
 904
 905        for (ch = 0; ch < dma_chan_count; ch++) {
 906                omap_clear_dma(ch);
 907
 908                dma_chan[ch].dev_id = -1;
 909                dma_chan[ch].next_lch = -1;
 910
 911                if (ch >= 6 && enable_1510_mode)
 912                        continue;
 913
 914                if (dma_omap1()) {
 915                        /*
 916                         * request_irq() doesn't like dev_id (ie. ch) being
 917                         * zero, so we have to kludge around this.
 918                         */
 919                        sprintf(&irq_name[0], "%d", ch);
 920                        dma_irq = platform_get_irq_byname(pdev, irq_name);
 921
 922                        if (dma_irq < 0) {
 923                                ret = dma_irq;
 924                                goto exit_dma_irq_fail;
 925                        }
 926
 927                        /* INT_DMA_LCD is handled in lcd_dma.c */
 928                        if (dma_irq == INT_DMA_LCD)
 929                                continue;
 930
 931                        ret = request_irq(dma_irq,
 932                                        omap1_dma_irq_handler, 0, "DMA",
 933                                        (void *) (ch + 1));
 934                        if (ret != 0)
 935                                goto exit_dma_irq_fail;
 936                }
 937        }
 938
 939        /* reserve dma channels 0 and 1 in high security devices on 34xx */
 940        if (d->dev_caps & HS_CHANNELS_RESERVED) {
 941                pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n");
 942                dma_chan[0].dev_id = 0;
 943                dma_chan[1].dev_id = 1;
 944        }
 945        p->show_dma_caps();
 946        return 0;
 947
 948exit_dma_irq_fail:
 949        return ret;
 950}
 951
 952static int omap_system_dma_remove(struct platform_device *pdev)
 953{
 954        int dma_irq, irq_rel = 0;
 955
 956        if (dma_omap2plus())
 957                return 0;
 958
 959        for ( ; irq_rel < dma_chan_count; irq_rel++) {
 960                dma_irq = platform_get_irq(pdev, irq_rel);
 961                free_irq(dma_irq, (void *)(irq_rel + 1));
 962        }
 963
 964        return 0;
 965}
 966
 967static struct platform_driver omap_system_dma_driver = {
 968        .probe          = omap_system_dma_probe,
 969        .remove         = omap_system_dma_remove,
 970        .driver         = {
 971                .name   = "omap_dma_system"
 972        },
 973};
 974
 975static int __init omap_system_dma_init(void)
 976{
 977        return platform_driver_register(&omap_system_dma_driver);
 978}
 979arch_initcall(omap_system_dma_init);
 980
 981static void __exit omap_system_dma_exit(void)
 982{
 983        platform_driver_unregister(&omap_system_dma_driver);
 984}
 985
 986MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
 987MODULE_LICENSE("GPL");
 988MODULE_AUTHOR("Texas Instruments Inc");
 989
 990/*
 991 * Reserve the omap SDMA channels using cmdline bootarg
 992 * "omap_dma_reserve_ch=". The valid range is 1 to 32
 993 */
 994static int __init omap_dma_cmdline_reserve_ch(char *str)
 995{
 996        if (get_option(&str, &omap_dma_reserve_channels) != 1)
 997                omap_dma_reserve_channels = 0;
 998        return 1;
 999}
1000
1001__setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
1002
1003
1004