linux/arch/arm/mm/cache-tauros3.h
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   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Marvell Tauros3 cache controller includes
   4 *
   5 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
   6 *
   7 * based on GPL'ed 2.6 kernel sources
   8 *  (c) Marvell International Ltd.
   9 */
  10
  11#ifndef __ASM_ARM_HARDWARE_TAUROS3_H
  12#define __ASM_ARM_HARDWARE_TAUROS3_H
  13
  14/*
  15 * Marvell Tauros3 L2CC is compatible with PL310 r0p0
  16 * but with PREFETCH_CTRL (r2p0) and an additional event counter.
  17 * Also, there is AUX2_CTRL for some Marvell specific control.
  18 */
  19
  20#define TAUROS3_EVENT_CNT2_CFG          0x224
  21#define TAUROS3_EVENT_CNT2_VAL          0x228
  22#define TAUROS3_INV_ALL                 0x780
  23#define TAUROS3_CLEAN_ALL               0x784
  24#define TAUROS3_AUX2_CTRL               0x820
  25
  26/* Registers shifts and masks */
  27#define TAUROS3_AUX2_CTRL_LINEFILL_BURST8_EN    (1 << 2)
  28
  29#endif
  30