1/* 2 * IO mappings for OMAP2+ 3 * 4 * IO definitions for TI OMAP processors and boards 5 * 6 * Copied from arch/arm/mach-sa1100/include/mach/io.h 7 * Copyright (C) 1997-1999 Russell King 8 * 9 * Copyright (C) 2009-2012 Texas Instruments 10 * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 11 * 12 * This program is free software; you can redistribute it and/or modify it 13 * under the terms of the GNU General Public License as published by the 14 * Free Software Foundation; either version 2 of the License, or (at your 15 * option) any later version. 16 * 17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * You should have received a copy of the GNU General Public License along 29 * with this program; if not, write to the Free Software Foundation, Inc., 30 * 675 Mass Ave, Cambridge, MA 02139, USA. 31 */ 32 33#define OMAP2_L3_IO_OFFSET 0x90000000 34#define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */ 35 36#define OMAP2_L4_IO_OFFSET 0xb2000000 37#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */ 38 39#define OMAP4_L3_IO_OFFSET 0xb4000000 40#define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */ 41 42#define AM33XX_L4_WK_IO_OFFSET 0xb5000000 43#define AM33XX_L4_WK_IO_ADDRESS(pa) IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET) 44 45#define OMAP4_L3_PER_IO_OFFSET 0xb1100000 46#define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET) 47 48#define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */ 49#define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET) 50 51/* 52 * ---------------------------------------------------------------------------- 53 * Omap2 specific IO mapping 54 * ---------------------------------------------------------------------------- 55 */ 56 57/* We map both L3 and L4 on OMAP2 */ 58#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/ 59#define L3_24XX_VIRT (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET) 60#define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ 61#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */ 62#define L4_24XX_VIRT (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET) 63#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */ 64 65#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */ 66#define L4_WK_243X_VIRT (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET) 67#define L4_WK_243X_SIZE SZ_1M 68#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE 69#define OMAP243X_GPMC_VIRT (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET) 70 /* 0x6e000000 --> 0xfe000000 */ 71#define OMAP243X_GPMC_SIZE SZ_1M 72#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE 73 /* 0x6D000000 --> 0xfd000000 */ 74#define OMAP243X_SDRC_VIRT (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET) 75#define OMAP243X_SDRC_SIZE SZ_1M 76#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE 77 /* 0x6c000000 --> 0xfc000000 */ 78#define OMAP243X_SMS_VIRT (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET) 79#define OMAP243X_SMS_SIZE SZ_1M 80 81/* 2420 IVA */ 82#define DSP_MEM_2420_PHYS OMAP2420_DSP_MEM_BASE 83 /* 0x58000000 --> 0xfc100000 */ 84#define DSP_MEM_2420_VIRT 0xfc100000 85#define DSP_MEM_2420_SIZE 0x28000 86#define DSP_IPI_2420_PHYS OMAP2420_DSP_IPI_BASE 87 /* 0x59000000 --> 0xfc128000 */ 88#define DSP_IPI_2420_VIRT 0xfc128000 89#define DSP_IPI_2420_SIZE SZ_4K 90#define DSP_MMU_2420_PHYS OMAP2420_DSP_MMU_BASE 91 /* 0x5a000000 --> 0xfc129000 */ 92#define DSP_MMU_2420_VIRT 0xfc129000 93#define DSP_MMU_2420_SIZE SZ_4K 94 95/* 2430 IVA2.1 - currently unmapped */ 96 97/* 98 * ---------------------------------------------------------------------------- 99 * Omap3 specific IO mapping 100 * ---------------------------------------------------------------------------- 101 */ 102 103/* We map both L3 and L4 on OMAP3 */ 104#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 --> 0xf8000000 */ 105#define L3_34XX_VIRT (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET) 106#define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ 107 108#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 --> 0xfa000000 */ 109#define L4_34XX_VIRT (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET) 110#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */ 111 112/* 113 * ---------------------------------------------------------------------------- 114 * AM33XX specific IO mapping 115 * ---------------------------------------------------------------------------- 116 */ 117#define L4_WK_AM33XX_PHYS L4_WK_AM33XX_BASE 118#define L4_WK_AM33XX_VIRT (L4_WK_AM33XX_PHYS + AM33XX_L4_WK_IO_OFFSET) 119#define L4_WK_AM33XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */ 120 121/* 122 * Need to look at the Size 4M for L4. 123 * VPOM3430 was not working for Int controller 124 */ 125 126#define L4_PER_34XX_PHYS L4_PER_34XX_BASE 127 /* 0x49000000 --> 0xfb000000 */ 128#define L4_PER_34XX_VIRT (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET) 129#define L4_PER_34XX_SIZE SZ_1M 130 131#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE 132 /* 0x54000000 --> 0xfe800000 */ 133#define L4_EMU_34XX_VIRT (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET) 134#define L4_EMU_34XX_SIZE SZ_8M 135 136#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE 137 /* 0x6e000000 --> 0xfe000000 */ 138#define OMAP34XX_GPMC_VIRT (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET) 139#define OMAP34XX_GPMC_SIZE SZ_1M 140 141#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE 142 /* 0x6c000000 --> 0xfc000000 */ 143#define OMAP343X_SMS_VIRT (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET) 144#define OMAP343X_SMS_SIZE SZ_1M 145 146#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE 147 /* 0x6D000000 --> 0xfd000000 */ 148#define OMAP343X_SDRC_VIRT (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET) 149#define OMAP343X_SDRC_SIZE SZ_1M 150 151/* 3430 IVA - currently unmapped */ 152 153/* 154 * ---------------------------------------------------------------------------- 155 * Omap4 specific IO mapping 156 * ---------------------------------------------------------------------------- 157 */ 158 159/* We map both L3 and L4 on OMAP4 */ 160#define L3_44XX_PHYS L3_44XX_BASE /* 0x44000000 --> 0xf8000000 */ 161#define L3_44XX_VIRT (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET) 162#define L3_44XX_SIZE SZ_1M 163 164#define L4_44XX_PHYS L4_44XX_BASE /* 0x4a000000 --> 0xfc000000 */ 165#define L4_44XX_VIRT (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET) 166#define L4_44XX_SIZE SZ_4M 167 168#define L4_PER_44XX_PHYS L4_PER_44XX_BASE 169 /* 0x48000000 --> 0xfa000000 */ 170#define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET) 171#define L4_PER_44XX_SIZE SZ_4M 172 173#define L4_ABE_44XX_PHYS L4_ABE_44XX_BASE 174 /* 0x49000000 --> 0xfb000000 */ 175#define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET) 176#define L4_ABE_44XX_SIZE SZ_1M 177/* 178 * ---------------------------------------------------------------------------- 179 * Omap5 specific IO mapping 180 * ---------------------------------------------------------------------------- 181 */ 182#define L3_54XX_PHYS L3_54XX_BASE /* 0x44000000 --> 0xf8000000 */ 183#define L3_54XX_VIRT (L3_54XX_PHYS + OMAP4_L3_IO_OFFSET) 184#define L3_54XX_SIZE SZ_1M 185 186#define L4_54XX_PHYS L4_54XX_BASE /* 0x4a000000 --> 0xfc000000 */ 187#define L4_54XX_VIRT (L4_54XX_PHYS + OMAP2_L4_IO_OFFSET) 188#define L4_54XX_SIZE SZ_4M 189 190#define L4_WK_54XX_PHYS L4_WK_54XX_BASE /* 0x4ae00000 --> 0xfce00000 */ 191#define L4_WK_54XX_VIRT (L4_WK_54XX_PHYS + OMAP2_L4_IO_OFFSET) 192#define L4_WK_54XX_SIZE SZ_2M 193 194#define L4_PER_54XX_PHYS L4_PER_54XX_BASE /* 0x48000000 --> 0xfa000000 */ 195#define L4_PER_54XX_VIRT (L4_PER_54XX_PHYS + OMAP2_L4_IO_OFFSET) 196#define L4_PER_54XX_SIZE SZ_4M 197 198/* 199 * ---------------------------------------------------------------------------- 200 * DRA7xx specific IO mapping 201 * ---------------------------------------------------------------------------- 202 */ 203/* 204 * L3_MAIN_SN_DRA7XX_PHYS 0x44000000 --> 0xf8000000 205 * The overall space is 24MiB (0x4400_0000<->0x457F_FFFF), but mapping 206 * everything is just inefficient, since, there are too many address holes. 207 */ 208#define L3_MAIN_SN_DRA7XX_PHYS L3_MAIN_SN_DRA7XX_BASE 209#define L3_MAIN_SN_DRA7XX_VIRT (L3_MAIN_SN_DRA7XX_PHYS + OMAP4_L3_IO_OFFSET) 210#define L3_MAIN_SN_DRA7XX_SIZE SZ_1M 211 212/* 213 * L4_PER1_DRA7XX_PHYS (0x4800_000<>0x480D_2FFF) -> 0.82MiB (alloc 1MiB) 214 * (0x48000000<->0x48100000) <=> (0xFA000000<->0xFA100000) 215 */ 216#define L4_PER1_DRA7XX_PHYS L4_PER1_DRA7XX_BASE 217#define L4_PER1_DRA7XX_VIRT (L4_PER1_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET) 218#define L4_PER1_DRA7XX_SIZE SZ_1M 219 220/* 221 * L4_CFG_MPU_DRA7XX_PHYS (0x48210000<>0x482A_F2FF) -> 0.62MiB (alloc 1MiB) 222 * (0x48210000<->0x48310000) <=> (0xFA210000<->0xFA310000) 223 * NOTE: This is a bit of an orphan memory map sitting isolated in TRM 224 */ 225#define L4_CFG_MPU_DRA7XX_PHYS L4_CFG_MPU_DRA7XX_BASE 226#define L4_CFG_MPU_DRA7XX_VIRT (L4_CFG_MPU_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET) 227#define L4_CFG_MPU_DRA7XX_SIZE SZ_1M 228 229/* 230 * L4_PER2_DRA7XX_PHYS (0x4840_0000<>0x4848_8FFF) -> .53MiB (alloc 1MiB) 231 * (0x48400000<->0x48500000) <=> (0xFA400000<->0xFA500000) 232 */ 233#define L4_PER2_DRA7XX_PHYS L4_PER2_DRA7XX_BASE 234#define L4_PER2_DRA7XX_VIRT (L4_PER2_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET) 235#define L4_PER2_DRA7XX_SIZE SZ_1M 236 237/* 238 * L4_PER3_DRA7XX_PHYS (0x4880_0000<>0x489E_0FFF) -> 1.87MiB (alloc 2MiB) 239 * (0x48800000<->0x48A00000) <=> (0xFA800000<->0xFAA00000) 240 */ 241#define L4_PER3_DRA7XX_PHYS L4_PER3_DRA7XX_BASE 242#define L4_PER3_DRA7XX_VIRT (L4_PER3_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET) 243#define L4_PER3_DRA7XX_SIZE SZ_2M 244 245/* 246 * L4_CFG_DRA7XX_PHYS (0x4A00_0000<>0x4A22_BFFF) ->2.17MiB (alloc 3MiB)? 247 * (0x4A000000<->0x4A300000) <=> (0xFC000000<->0xFC300000) 248 */ 249#define L4_CFG_DRA7XX_PHYS L4_CFG_DRA7XX_BASE 250#define L4_CFG_DRA7XX_VIRT (L4_CFG_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET) 251#define L4_CFG_DRA7XX_SIZE (SZ_1M + SZ_2M) 252 253/* 254 * L4_WKUP_DRA7XX_PHYS (0x4AE0_0000<>0x4AE3_EFFF) -> .24 mb (alloc 1MiB)? 255 * (0x4AE00000<->4AF00000) <=> (0xFCE00000<->0xFCF00000) 256 */ 257#define L4_WKUP_DRA7XX_PHYS L4_WKUP_DRA7XX_BASE 258#define L4_WKUP_DRA7XX_VIRT (L4_WKUP_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET) 259#define L4_WKUP_DRA7XX_SIZE SZ_1M 260