linux/arch/arm/mach-imx/pm-imx6.c
<<
>>
Prefs
   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Copyright 2011-2014 Freescale Semiconductor, Inc.
   4 * Copyright 2011 Linaro Ltd.
   5 */
   6
   7#include <linux/clk/imx.h>
   8#include <linux/delay.h>
   9#include <linux/init.h>
  10#include <linux/io.h>
  11#include <linux/irq.h>
  12#include <linux/genalloc.h>
  13#include <linux/mfd/syscon.h>
  14#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  15#include <linux/of.h>
  16#include <linux/of_address.h>
  17#include <linux/of_platform.h>
  18#include <linux/regmap.h>
  19#include <linux/suspend.h>
  20#include <asm/cacheflush.h>
  21#include <asm/fncpy.h>
  22#include <asm/proc-fns.h>
  23#include <asm/suspend.h>
  24#include <asm/tlb.h>
  25
  26#include "common.h"
  27#include "hardware.h"
  28
  29#define CCR                             0x0
  30#define BM_CCR_WB_COUNT                 (0x7 << 16)
  31#define BM_CCR_RBC_BYPASS_COUNT         (0x3f << 21)
  32#define BM_CCR_RBC_EN                   (0x1 << 27)
  33
  34#define CLPCR                           0x54
  35#define BP_CLPCR_LPM                    0
  36#define BM_CLPCR_LPM                    (0x3 << 0)
  37#define BM_CLPCR_BYPASS_PMIC_READY      (0x1 << 2)
  38#define BM_CLPCR_ARM_CLK_DIS_ON_LPM     (0x1 << 5)
  39#define BM_CLPCR_SBYOS                  (0x1 << 6)
  40#define BM_CLPCR_DIS_REF_OSC            (0x1 << 7)
  41#define BM_CLPCR_VSTBY                  (0x1 << 8)
  42#define BP_CLPCR_STBY_COUNT             9
  43#define BM_CLPCR_STBY_COUNT             (0x3 << 9)
  44#define BM_CLPCR_COSC_PWRDOWN           (0x1 << 11)
  45#define BM_CLPCR_WB_PER_AT_LPM          (0x1 << 16)
  46#define BM_CLPCR_WB_CORE_AT_LPM         (0x1 << 17)
  47#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS    (0x1 << 19)
  48#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS    (0x1 << 21)
  49#define BM_CLPCR_MASK_CORE0_WFI         (0x1 << 22)
  50#define BM_CLPCR_MASK_CORE1_WFI         (0x1 << 23)
  51#define BM_CLPCR_MASK_CORE2_WFI         (0x1 << 24)
  52#define BM_CLPCR_MASK_CORE3_WFI         (0x1 << 25)
  53#define BM_CLPCR_MASK_SCU_IDLE          (0x1 << 26)
  54#define BM_CLPCR_MASK_L2CC_IDLE         (0x1 << 27)
  55
  56#define CGPR                            0x64
  57#define BM_CGPR_INT_MEM_CLK_LPM         (0x1 << 17)
  58
  59#define MX6Q_SUSPEND_OCRAM_SIZE         0x1000
  60#define MX6_MAX_MMDC_IO_NUM             33
  61
  62static void __iomem *ccm_base;
  63static void __iomem *suspend_ocram_base;
  64static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase);
  65
  66/*
  67 * suspend ocram space layout:
  68 * ======================== high address ======================
  69 *                              .
  70 *                              .
  71 *                              .
  72 *                              ^
  73 *                              ^
  74 *                              ^
  75 *                      imx6_suspend code
  76 *              PM_INFO structure(imx6_cpu_pm_info)
  77 * ======================== low address =======================
  78 */
  79
  80struct imx6_pm_base {
  81        phys_addr_t pbase;
  82        void __iomem *vbase;
  83};
  84
  85struct imx6_pm_socdata {
  86        u32 ddr_type;
  87        const char *mmdc_compat;
  88        const char *src_compat;
  89        const char *iomuxc_compat;
  90        const char *gpc_compat;
  91        const char *pl310_compat;
  92        const u32 mmdc_io_num;
  93        const u32 *mmdc_io_offset;
  94};
  95
  96static const u32 imx6q_mmdc_io_offset[] __initconst = {
  97        0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */
  98        0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */
  99        0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */
 100        0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */
 101        0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */
 102        0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */
 103        0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */
 104        0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */
 105        0x74c,                      /* GPR_ADDS */
 106};
 107
 108static const u32 imx6dl_mmdc_io_offset[] __initconst = {
 109        0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */
 110        0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */
 111        0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */
 112        0x4bc, 0x4c0, 0x4c4, 0x4c8, /* DRAM_SDQS0 ~ DRAM_SDQS3 */
 113        0x4cc, 0x4d0, 0x4d4, 0x4d8, /* DRAM_SDQS4 ~ DRAM_SDQS7 */
 114        0x764, 0x770, 0x778, 0x77c, /* GPR_B0DS ~ GPR_B3DS */
 115        0x780, 0x784, 0x78c, 0x748, /* GPR_B4DS ~ GPR_B7DS */
 116        0x4b4, 0x4b8, 0x750, 0x760, /* SODT0, SODT1, MODE_CTL, MODE */
 117        0x74c,                      /* GPR_ADDS */
 118};
 119
 120static const u32 imx6sl_mmdc_io_offset[] __initconst = {
 121        0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */
 122        0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */
 123        0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */
 124        0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */
 125        0x330, 0x334, 0x320,        /* SDCKE0, SDCKE1, RESET */
 126};
 127
 128static const u32 imx6sll_mmdc_io_offset[] __initconst = {
 129        0x294, 0x298, 0x29c, 0x2a0, /* DQM0 ~ DQM3 */
 130        0x544, 0x54c, 0x554, 0x558, /* GPR_B0DS ~ GPR_B3DS */
 131        0x530, 0x540, 0x2ac, 0x52c, /* MODE_CTL, MODE, SDCLK_0, GPR_ADDDS */
 132        0x2a4, 0x2a8,               /* SDCKE0, SDCKE1*/
 133};
 134
 135static const u32 imx6sx_mmdc_io_offset[] __initconst = {
 136        0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */
 137        0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */
 138        0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */
 139        0x310, 0x314, 0x5f8, 0x608, /* SODT0, SODT1, MODE_CTL, MODE */
 140        0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */
 141};
 142
 143static const u32 imx6ul_mmdc_io_offset[] __initconst = {
 144        0x244, 0x248, 0x24c, 0x250, /* DQM0, DQM1, RAS, CAS */
 145        0x27c, 0x498, 0x4a4, 0x490, /* SDCLK0, GPR_B0DS-B1DS, GPR_ADDS */
 146        0x280, 0x284, 0x260, 0x264, /* SDQS0~1, SODT0, SODT1 */
 147        0x494, 0x4b0,               /* MODE_CTL, MODE, */
 148};
 149
 150static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
 151        .mmdc_compat = "fsl,imx6q-mmdc",
 152        .src_compat = "fsl,imx6q-src",
 153        .iomuxc_compat = "fsl,imx6q-iomuxc",
 154        .gpc_compat = "fsl,imx6q-gpc",
 155        .pl310_compat = "arm,pl310-cache",
 156        .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset),
 157        .mmdc_io_offset = imx6q_mmdc_io_offset,
 158};
 159
 160static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
 161        .mmdc_compat = "fsl,imx6q-mmdc",
 162        .src_compat = "fsl,imx6q-src",
 163        .iomuxc_compat = "fsl,imx6dl-iomuxc",
 164        .gpc_compat = "fsl,imx6q-gpc",
 165        .pl310_compat = "arm,pl310-cache",
 166        .mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset),
 167        .mmdc_io_offset = imx6dl_mmdc_io_offset,
 168};
 169
 170static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
 171        .mmdc_compat = "fsl,imx6sl-mmdc",
 172        .src_compat = "fsl,imx6sl-src",
 173        .iomuxc_compat = "fsl,imx6sl-iomuxc",
 174        .gpc_compat = "fsl,imx6sl-gpc",
 175        .pl310_compat = "arm,pl310-cache",
 176        .mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset),
 177        .mmdc_io_offset = imx6sl_mmdc_io_offset,
 178};
 179
 180static const struct imx6_pm_socdata imx6sll_pm_data __initconst = {
 181        .mmdc_compat = "fsl,imx6sll-mmdc",
 182        .src_compat = "fsl,imx6sll-src",
 183        .iomuxc_compat = "fsl,imx6sll-iomuxc",
 184        .gpc_compat = "fsl,imx6sll-gpc",
 185        .pl310_compat = "arm,pl310-cache",
 186        .mmdc_io_num = ARRAY_SIZE(imx6sll_mmdc_io_offset),
 187        .mmdc_io_offset = imx6sll_mmdc_io_offset,
 188};
 189
 190static const struct imx6_pm_socdata imx6sx_pm_data __initconst = {
 191        .mmdc_compat = "fsl,imx6sx-mmdc",
 192        .src_compat = "fsl,imx6sx-src",
 193        .iomuxc_compat = "fsl,imx6sx-iomuxc",
 194        .gpc_compat = "fsl,imx6sx-gpc",
 195        .pl310_compat = "arm,pl310-cache",
 196        .mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset),
 197        .mmdc_io_offset = imx6sx_mmdc_io_offset,
 198};
 199
 200static const struct imx6_pm_socdata imx6ul_pm_data __initconst = {
 201        .mmdc_compat = "fsl,imx6ul-mmdc",
 202        .src_compat = "fsl,imx6ul-src",
 203        .iomuxc_compat = "fsl,imx6ul-iomuxc",
 204        .gpc_compat = "fsl,imx6ul-gpc",
 205        .pl310_compat = NULL,
 206        .mmdc_io_num = ARRAY_SIZE(imx6ul_mmdc_io_offset),
 207        .mmdc_io_offset = imx6ul_mmdc_io_offset,
 208};
 209
 210/*
 211 * This structure is for passing necessary data for low level ocram
 212 * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct
 213 * definition is changed, the offset definition in
 214 * arch/arm/mach-imx/suspend-imx6.S must be also changed accordingly,
 215 * otherwise, the suspend to ocram function will be broken!
 216 */
 217struct imx6_cpu_pm_info {
 218        phys_addr_t pbase; /* The physical address of pm_info. */
 219        phys_addr_t resume_addr; /* The physical resume address for asm code */
 220        u32 ddr_type;
 221        u32 pm_info_size; /* Size of pm_info. */
 222        struct imx6_pm_base mmdc_base;
 223        struct imx6_pm_base src_base;
 224        struct imx6_pm_base iomuxc_base;
 225        struct imx6_pm_base ccm_base;
 226        struct imx6_pm_base gpc_base;
 227        struct imx6_pm_base l2_base;
 228        u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */
 229        u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */
 230} __aligned(8);
 231
 232void imx6_set_int_mem_clk_lpm(bool enable)
 233{
 234        u32 val = readl_relaxed(ccm_base + CGPR);
 235
 236        val &= ~BM_CGPR_INT_MEM_CLK_LPM;
 237        if (enable)
 238                val |= BM_CGPR_INT_MEM_CLK_LPM;
 239        writel_relaxed(val, ccm_base + CGPR);
 240}
 241
 242void imx6_enable_rbc(bool enable)
 243{
 244        u32 val;
 245
 246        /*
 247         * need to mask all interrupts in GPC before
 248         * operating RBC configurations
 249         */
 250        imx_gpc_mask_all();
 251
 252        /* configure RBC enable bit */
 253        val = readl_relaxed(ccm_base + CCR);
 254        val &= ~BM_CCR_RBC_EN;
 255        val |= enable ? BM_CCR_RBC_EN : 0;
 256        writel_relaxed(val, ccm_base + CCR);
 257
 258        /* configure RBC count */
 259        val = readl_relaxed(ccm_base + CCR);
 260        val &= ~BM_CCR_RBC_BYPASS_COUNT;
 261        val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
 262        writel(val, ccm_base + CCR);
 263
 264        /*
 265         * need to delay at least 2 cycles of CKIL(32K)
 266         * due to hardware design requirement, which is
 267         * ~61us, here we use 65us for safe
 268         */
 269        udelay(65);
 270
 271        /* restore GPC interrupt mask settings */
 272        imx_gpc_restore_all();
 273}
 274
 275static void imx6q_enable_wb(bool enable)
 276{
 277        u32 val;
 278
 279        /* configure well bias enable bit */
 280        val = readl_relaxed(ccm_base + CLPCR);
 281        val &= ~BM_CLPCR_WB_PER_AT_LPM;
 282        val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
 283        writel_relaxed(val, ccm_base + CLPCR);
 284
 285        /* configure well bias count */
 286        val = readl_relaxed(ccm_base + CCR);
 287        val &= ~BM_CCR_WB_COUNT;
 288        val |= enable ? BM_CCR_WB_COUNT : 0;
 289        writel_relaxed(val, ccm_base + CCR);
 290}
 291
 292int imx6_set_lpm(enum mxc_cpu_pwr_mode mode)
 293{
 294        u32 val = readl_relaxed(ccm_base + CLPCR);
 295
 296        val &= ~BM_CLPCR_LPM;
 297        switch (mode) {
 298        case WAIT_CLOCKED:
 299                break;
 300        case WAIT_UNCLOCKED:
 301                val |= 0x1 << BP_CLPCR_LPM;
 302                val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
 303                break;
 304        case STOP_POWER_ON:
 305                val |= 0x2 << BP_CLPCR_LPM;
 306                val &= ~BM_CLPCR_VSTBY;
 307                val &= ~BM_CLPCR_SBYOS;
 308                if (cpu_is_imx6sl())
 309                        val |= BM_CLPCR_BYPASS_PMIC_READY;
 310                if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() ||
 311                    cpu_is_imx6ull() || cpu_is_imx6sll() || cpu_is_imx6ulz())
 312                        val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
 313                else
 314                        val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
 315                break;
 316        case WAIT_UNCLOCKED_POWER_OFF:
 317                val |= 0x1 << BP_CLPCR_LPM;
 318                val &= ~BM_CLPCR_VSTBY;
 319                val &= ~BM_CLPCR_SBYOS;
 320                break;
 321        case STOP_POWER_OFF:
 322                val |= 0x2 << BP_CLPCR_LPM;
 323                val |= 0x3 << BP_CLPCR_STBY_COUNT;
 324                val |= BM_CLPCR_VSTBY;
 325                val |= BM_CLPCR_SBYOS;
 326                if (cpu_is_imx6sl() || cpu_is_imx6sx())
 327                        val |= BM_CLPCR_BYPASS_PMIC_READY;
 328                if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() ||
 329                    cpu_is_imx6ull() || cpu_is_imx6sll() || cpu_is_imx6ulz())
 330                        val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
 331                else
 332                        val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
 333                break;
 334        default:
 335                return -EINVAL;
 336        }
 337
 338        /*
 339         * ERR007265: CCM: When improper low-power sequence is used,
 340         * the SoC enters low power mode before the ARM core executes WFI.
 341         *
 342         * Software workaround:
 343         * 1) Software should trigger IRQ #32 (IOMUX) to be always pending
 344         *    by setting IOMUX_GPR1_GINT.
 345         * 2) Software should then unmask IRQ #32 in GPC before setting CCM
 346         *    Low-Power mode.
 347         * 3) Software should mask IRQ #32 right after CCM Low-Power mode
 348         *    is set (set bits 0-1 of CCM_CLPCR).
 349         *
 350         * Note that IRQ #32 is GIC SPI #0.
 351         */
 352        if (mode != WAIT_CLOCKED)
 353                imx_gpc_hwirq_unmask(0);
 354        writel_relaxed(val, ccm_base + CLPCR);
 355        if (mode != WAIT_CLOCKED)
 356                imx_gpc_hwirq_mask(0);
 357
 358        return 0;
 359}
 360
 361static int imx6q_suspend_finish(unsigned long val)
 362{
 363        if (!imx6_suspend_in_ocram_fn) {
 364                cpu_do_idle();
 365        } else {
 366                /*
 367                 * call low level suspend function in ocram,
 368                 * as we need to float DDR IO.
 369                 */
 370                local_flush_tlb_all();
 371                /* check if need to flush internal L2 cache */
 372                if (!((struct imx6_cpu_pm_info *)
 373                        suspend_ocram_base)->l2_base.vbase)
 374                        flush_cache_all();
 375                imx6_suspend_in_ocram_fn(suspend_ocram_base);
 376        }
 377
 378        return 0;
 379}
 380
 381static int imx6q_pm_enter(suspend_state_t state)
 382{
 383        switch (state) {
 384        case PM_SUSPEND_STANDBY:
 385                imx6_set_lpm(STOP_POWER_ON);
 386                imx6_set_int_mem_clk_lpm(true);
 387                imx_gpc_pre_suspend(false);
 388                if (cpu_is_imx6sl())
 389                        imx6sl_set_wait_clk(true);
 390                /* Zzz ... */
 391                cpu_do_idle();
 392                if (cpu_is_imx6sl())
 393                        imx6sl_set_wait_clk(false);
 394                imx_gpc_post_resume();
 395                imx6_set_lpm(WAIT_CLOCKED);
 396                break;
 397        case PM_SUSPEND_MEM:
 398                imx6_set_lpm(STOP_POWER_OFF);
 399                imx6_set_int_mem_clk_lpm(false);
 400                imx6q_enable_wb(true);
 401                /*
 402                 * For suspend into ocram, asm code already take care of
 403                 * RBC setting, so we do NOT need to do that here.
 404                 */
 405                if (!imx6_suspend_in_ocram_fn)
 406                        imx6_enable_rbc(true);
 407                imx_gpc_pre_suspend(true);
 408                imx_anatop_pre_suspend();
 409                /* Zzz ... */
 410                cpu_suspend(0, imx6q_suspend_finish);
 411                if (cpu_is_imx6q() || cpu_is_imx6dl())
 412                        imx_smp_prepare();
 413                imx_anatop_post_resume();
 414                imx_gpc_post_resume();
 415                imx6_enable_rbc(false);
 416                imx6q_enable_wb(false);
 417                imx6_set_int_mem_clk_lpm(true);
 418                imx6_set_lpm(WAIT_CLOCKED);
 419                break;
 420        default:
 421                return -EINVAL;
 422        }
 423
 424        return 0;
 425}
 426
 427static int imx6q_pm_valid(suspend_state_t state)
 428{
 429        return (state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM);
 430}
 431
 432static const struct platform_suspend_ops imx6q_pm_ops = {
 433        .enter = imx6q_pm_enter,
 434        .valid = imx6q_pm_valid,
 435};
 436
 437static int __init imx6_pm_get_base(struct imx6_pm_base *base,
 438                                const char *compat)
 439{
 440        struct device_node *node;
 441        struct resource res;
 442        int ret = 0;
 443
 444        node = of_find_compatible_node(NULL, NULL, compat);
 445        if (!node)
 446                return -ENODEV;
 447
 448        ret = of_address_to_resource(node, 0, &res);
 449        if (ret)
 450                goto put_node;
 451
 452        base->pbase = res.start;
 453        base->vbase = ioremap(res.start, resource_size(&res));
 454        if (!base->vbase)
 455                ret = -ENOMEM;
 456
 457put_node:
 458        of_node_put(node);
 459        return ret;
 460}
 461
 462static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
 463{
 464        phys_addr_t ocram_pbase;
 465        struct device_node *node;
 466        struct platform_device *pdev;
 467        struct imx6_cpu_pm_info *pm_info;
 468        struct gen_pool *ocram_pool;
 469        unsigned long ocram_base;
 470        int i, ret = 0;
 471        const u32 *mmdc_offset_array;
 472
 473        suspend_set_ops(&imx6q_pm_ops);
 474
 475        if (!socdata) {
 476                pr_warn("%s: invalid argument!\n", __func__);
 477                return -EINVAL;
 478        }
 479
 480        node = of_find_compatible_node(NULL, NULL, "mmio-sram");
 481        if (!node) {
 482                pr_warn("%s: failed to find ocram node!\n", __func__);
 483                return -ENODEV;
 484        }
 485
 486        pdev = of_find_device_by_node(node);
 487        if (!pdev) {
 488                pr_warn("%s: failed to find ocram device!\n", __func__);
 489                ret = -ENODEV;
 490                goto put_node;
 491        }
 492
 493        ocram_pool = gen_pool_get(&pdev->dev, NULL);
 494        if (!ocram_pool) {
 495                pr_warn("%s: ocram pool unavailable!\n", __func__);
 496                ret = -ENODEV;
 497                goto put_device;
 498        }
 499
 500        ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE);
 501        if (!ocram_base) {
 502                pr_warn("%s: unable to alloc ocram!\n", __func__);
 503                ret = -ENOMEM;
 504                goto put_device;
 505        }
 506
 507        ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base);
 508
 509        suspend_ocram_base = __arm_ioremap_exec(ocram_pbase,
 510                MX6Q_SUSPEND_OCRAM_SIZE, false);
 511
 512        memset(suspend_ocram_base, 0, sizeof(*pm_info));
 513        pm_info = suspend_ocram_base;
 514        pm_info->pbase = ocram_pbase;
 515        pm_info->resume_addr = __pa_symbol(v7_cpu_resume);
 516        pm_info->pm_info_size = sizeof(*pm_info);
 517
 518        /*
 519         * ccm physical address is not used by asm code currently,
 520         * so get ccm virtual address directly.
 521         */
 522        pm_info->ccm_base.vbase = ccm_base;
 523
 524        ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat);
 525        if (ret) {
 526                pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret);
 527                goto put_device;
 528        }
 529
 530        ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat);
 531        if (ret) {
 532                pr_warn("%s: failed to get src base %d!\n", __func__, ret);
 533                goto src_map_failed;
 534        }
 535
 536        ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat);
 537        if (ret) {
 538                pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret);
 539                goto iomuxc_map_failed;
 540        }
 541
 542        ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat);
 543        if (ret) {
 544                pr_warn("%s: failed to get gpc base %d!\n", __func__, ret);
 545                goto gpc_map_failed;
 546        }
 547
 548        if (socdata->pl310_compat) {
 549                ret = imx6_pm_get_base(&pm_info->l2_base, socdata->pl310_compat);
 550                if (ret) {
 551                        pr_warn("%s: failed to get pl310-cache base %d!\n",
 552                                __func__, ret);
 553                        goto pl310_cache_map_failed;
 554                }
 555        }
 556
 557        pm_info->ddr_type = imx_mmdc_get_ddr_type();
 558        pm_info->mmdc_io_num = socdata->mmdc_io_num;
 559        mmdc_offset_array = socdata->mmdc_io_offset;
 560
 561        for (i = 0; i < pm_info->mmdc_io_num; i++) {
 562                pm_info->mmdc_io_val[i][0] =
 563                        mmdc_offset_array[i];
 564                pm_info->mmdc_io_val[i][1] =
 565                        readl_relaxed(pm_info->iomuxc_base.vbase +
 566                        mmdc_offset_array[i]);
 567        }
 568
 569        imx6_suspend_in_ocram_fn = fncpy(
 570                suspend_ocram_base + sizeof(*pm_info),
 571                &imx6_suspend,
 572                MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info));
 573
 574        goto put_device;
 575
 576pl310_cache_map_failed:
 577        iounmap(pm_info->gpc_base.vbase);
 578gpc_map_failed:
 579        iounmap(pm_info->iomuxc_base.vbase);
 580iomuxc_map_failed:
 581        iounmap(pm_info->src_base.vbase);
 582src_map_failed:
 583        iounmap(pm_info->mmdc_base.vbase);
 584put_device:
 585        put_device(&pdev->dev);
 586put_node:
 587        of_node_put(node);
 588
 589        return ret;
 590}
 591
 592static void __init imx6_pm_common_init(const struct imx6_pm_socdata
 593                                        *socdata)
 594{
 595        struct regmap *gpr;
 596        int ret;
 597
 598        WARN_ON(!ccm_base);
 599
 600        if (IS_ENABLED(CONFIG_SUSPEND)) {
 601                ret = imx6q_suspend_init(socdata);
 602                if (ret)
 603                        pr_warn("%s: No DDR LPM support with suspend %d!\n",
 604                                __func__, ret);
 605        }
 606
 607        /*
 608         * This is for SW workaround step #1 of ERR007265, see comments
 609         * in imx6_set_lpm for details of this errata.
 610         * Force IOMUXC irq pending, so that the interrupt to GPC can be
 611         * used to deassert dsm_request signal when the signal gets
 612         * asserted unexpectedly.
 613         */
 614        gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
 615        if (!IS_ERR(gpr))
 616                regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT,
 617                                   IMX6Q_GPR1_GINT);
 618}
 619
 620static void imx6_pm_stby_poweroff(void)
 621{
 622        imx6_set_lpm(STOP_POWER_OFF);
 623        imx6q_suspend_finish(0);
 624
 625        mdelay(1000);
 626
 627        pr_emerg("Unable to poweroff system\n");
 628}
 629
 630static int imx6_pm_stby_poweroff_probe(void)
 631{
 632        if (pm_power_off) {
 633                pr_warn("%s: pm_power_off already claimed  %p %ps!\n",
 634                        __func__, pm_power_off, pm_power_off);
 635                return -EBUSY;
 636        }
 637
 638        pm_power_off = imx6_pm_stby_poweroff;
 639        return 0;
 640}
 641
 642void __init imx6_pm_ccm_init(const char *ccm_compat)
 643{
 644        struct device_node *np;
 645        u32 val;
 646
 647        np = of_find_compatible_node(NULL, NULL, ccm_compat);
 648        ccm_base = of_iomap(np, 0);
 649        BUG_ON(!ccm_base);
 650
 651        /*
 652         * Initialize CCM_CLPCR_LPM into RUN mode to avoid ARM core
 653         * clock being shut down unexpectedly by WAIT mode.
 654         */
 655        val = readl_relaxed(ccm_base + CLPCR);
 656        val &= ~BM_CLPCR_LPM;
 657        writel_relaxed(val, ccm_base + CLPCR);
 658
 659        if (of_property_read_bool(np, "fsl,pmic-stby-poweroff"))
 660                imx6_pm_stby_poweroff_probe();
 661
 662        of_node_put(np);
 663}
 664
 665void __init imx6q_pm_init(void)
 666{
 667        imx6_pm_common_init(&imx6q_pm_data);
 668}
 669
 670void __init imx6dl_pm_init(void)
 671{
 672        imx6_pm_common_init(&imx6dl_pm_data);
 673}
 674
 675void __init imx6sl_pm_init(void)
 676{
 677        struct regmap *gpr;
 678
 679        if (cpu_is_imx6sl()) {
 680                imx6_pm_common_init(&imx6sl_pm_data);
 681        } else {
 682                imx6_pm_common_init(&imx6sll_pm_data);
 683                gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
 684                if (!IS_ERR(gpr))
 685                        regmap_update_bits(gpr, IOMUXC_GPR5,
 686                                IMX6SLL_GPR5_AFCG_X_BYPASS_MASK, 0);
 687        }
 688}
 689
 690void __init imx6sx_pm_init(void)
 691{
 692        imx6_pm_common_init(&imx6sx_pm_data);
 693}
 694
 695void __init imx6ul_pm_init(void)
 696{
 697        imx6_pm_common_init(&imx6ul_pm_data);
 698}
 699