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7#ifndef __ASM_ARCH_MXC_COMMON_H__
8#define __ASM_ARCH_MXC_COMMON_H__
9
10#include <linux/reboot.h>
11
12struct irq_data;
13struct platform_device;
14struct pt_regs;
15struct clk;
16struct device_node;
17enum mxc_cpu_pwr_mode;
18struct of_device_id;
19
20void mx31_map_io(void);
21void mx35_map_io(void);
22void imx21_init_early(void);
23void imx31_init_early(void);
24void imx35_init_early(void);
25void mx31_init_irq(void);
26void mx35_init_irq(void);
27void mxc_set_cpu_type(unsigned int type);
28void mxc_restart(enum reboot_mode, const char *);
29void mxc_arch_reset_init(void __iomem *);
30void imx1_reset_init(void __iomem *);
31void imx_set_aips(void __iomem *);
32void imx_aips_allow_unprivileged_access(const char *compat);
33int mxc_device_init(void);
34void imx_set_soc_revision(unsigned int rev);
35void imx_init_revision_from_anatop(void);
36void imx6_enable_rbc(bool enable);
37void imx_gpc_check_dt(void);
38void imx_gpc_set_arm_power_in_lpm(bool power_off);
39void imx_gpc_set_l2_mem_power_in_lpm(bool power_off);
40void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
41void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
42void imx25_pm_init(void);
43void imx27_pm_init(void);
44void imx5_pmu_init(void);
45
46enum mxc_cpu_pwr_mode {
47 WAIT_CLOCKED,
48 WAIT_UNCLOCKED,
49 WAIT_UNCLOCKED_POWER_OFF,
50 STOP_POWER_ON,
51 STOP_POWER_OFF,
52};
53
54enum ulp_cpu_pwr_mode {
55 ULP_PM_HSRUN,
56 ULP_PM_RUN,
57 ULP_PM_WAIT,
58 ULP_PM_STOP,
59 ULP_PM_VLPS,
60 ULP_PM_VLLS,
61};
62
63void imx_enable_cpu(int cpu, bool enable);
64void imx_set_cpu_jump(int cpu, void *jump_addr);
65u32 imx_get_cpu_arg(int cpu);
66void imx_set_cpu_arg(int cpu, u32 arg);
67#ifdef CONFIG_SMP
68void v7_secondary_startup(void);
69void imx_scu_map_io(void);
70void imx_smp_prepare(void);
71#else
72static inline void imx_scu_map_io(void) {}
73static inline void imx_smp_prepare(void) {}
74#endif
75void imx_src_init(void);
76void imx_gpc_pre_suspend(bool arm_power_off);
77void imx_gpc_post_resume(void);
78void imx_gpc_mask_all(void);
79void imx_gpc_restore_all(void);
80void imx_gpc_hwirq_mask(unsigned int hwirq);
81void imx_gpc_hwirq_unmask(unsigned int hwirq);
82void imx_anatop_init(void);
83void imx_anatop_pre_suspend(void);
84void imx_anatop_post_resume(void);
85int imx6_set_lpm(enum mxc_cpu_pwr_mode mode);
86void imx6_set_int_mem_clk_lpm(bool enable);
87int imx_mmdc_get_ddr_type(void);
88int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode);
89
90void imx_cpu_die(unsigned int cpu);
91int imx_cpu_kill(unsigned int cpu);
92
93#ifdef CONFIG_SUSPEND
94void imx53_suspend(void __iomem *ocram_vbase);
95extern const u32 imx53_suspend_sz;
96void imx6_suspend(void __iomem *ocram_vbase);
97#else
98static inline void imx53_suspend(void __iomem *ocram_vbase) {}
99static const u32 imx53_suspend_sz;
100static inline void imx6_suspend(void __iomem *ocram_vbase) {}
101#endif
102
103void v7_cpu_resume(void);
104
105void imx6_pm_ccm_init(const char *ccm_compat);
106void imx6q_pm_init(void);
107void imx6dl_pm_init(void);
108void imx6sl_pm_init(void);
109void imx6sx_pm_init(void);
110void imx6ul_pm_init(void);
111void imx7ulp_pm_init(void);
112
113#ifdef CONFIG_PM
114void imx51_pm_init(void);
115void imx53_pm_init(void);
116#else
117static inline void imx51_pm_init(void) {}
118static inline void imx53_pm_init(void) {}
119#endif
120
121#ifdef CONFIG_NEON
122int mx51_neon_fixup(void);
123#else
124static inline int mx51_neon_fixup(void) { return 0; }
125#endif
126
127#ifdef CONFIG_CACHE_L2X0
128void imx_init_l2cache(void);
129#else
130static inline void imx_init_l2cache(void) {}
131#endif
132
133extern const struct smp_operations imx_smp_ops;
134extern const struct smp_operations ls1021a_smp_ops;
135
136#endif
137