linux/arch/arm/mach-davinci/board-neuros-osd2.c
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   1/*
   2 * Neuros Technologies OSD2 board support
   3 *
   4 * Modified from original 644X-EVM board support.
   5 * 2008 (c) Neuros Technology, LLC.
   6 * 2009 (c) Jorge Luis Zapata Muga <jorgeluis.zapata@gmail.com>
   7 * 2009 (c) Andrey A. Porodko <Andrey.Porodko@gmail.com>
   8 *
   9 * The Neuros OSD 2.0 is the hardware component of the Neuros Open
  10 * Internet Television Platform. Hardware is very close to TI
  11 * DM644X-EVM board. It has:
  12 *      DM6446M02 module with 256MB NAND, 256MB RAM, TLV320AIC32 AIC,
  13 *      USB, Ethernet, SD/MMC, UART, THS8200, TVP7000 for video.
  14 *      Additionally realtime clock, IR remote control receiver,
  15 *      IR Blaster based on MSP430 (firmware although is different
  16 *      from used in DM644X-EVM), internal ATA-6 3.5\xE2\x80\x9D HDD drive
  17 *      with PATA interface, two muxed red-green leds.
  18 *
  19 * For more information please refer to
  20 *              http://wiki.neurostechnology.com/index.php/OSD_2.0_HD
  21 *
  22 * This file is licensed under the terms of the GNU General Public
  23 * License version 2. This program is licensed "as is" without any
  24 * warranty of any kind, whether express or implied.
  25 */
  26#include <linux/platform_device.h>
  27#include <linux/gpio.h>
  28#include <linux/leds.h>
  29#include <linux/mtd/partitions.h>
  30#include <linux/platform_data/gpio-davinci.h>
  31#include <linux/platform_data/i2c-davinci.h>
  32#include <linux/platform_data/mmc-davinci.h>
  33#include <linux/platform_data/mtd-davinci.h>
  34#include <linux/platform_data/usb-davinci.h>
  35
  36#include <asm/mach-types.h>
  37#include <asm/mach/arch.h>
  38
  39#include <mach/common.h>
  40#include <mach/serial.h>
  41#include <mach/mux.h>
  42
  43#include "davinci.h"
  44
  45#define NEUROS_OSD2_PHY_ID              "davinci_mdio-0:01"
  46#define LXT971_PHY_ID                   0x001378e2
  47#define LXT971_PHY_MASK                 0xfffffff0
  48
  49#define NTOSD2_AUDIOSOC_I2C_ADDR        0x18
  50#define NTOSD2_MSP430_I2C_ADDR          0x59
  51#define NTOSD2_MSP430_IRQ               2
  52
  53/* Neuros OSD2 has a Samsung 256 MByte NAND flash (Dev ID of 0xAA,
  54 * 2048 blocks in the device, 64 pages per block, 2048 bytes per
  55 * page.
  56 */
  57
  58#define NAND_BLOCK_SIZE         SZ_128K
  59
  60static struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
  61        {
  62                /* UBL (a few copies) plus U-Boot */
  63                .name           = "bootloader",
  64                .offset         = 0,
  65                .size           = 15 * NAND_BLOCK_SIZE,
  66                .mask_flags     = MTD_WRITEABLE, /* force read-only */
  67        }, {
  68                /* U-Boot environment */
  69                .name           = "params",
  70                .offset         = MTDPART_OFS_APPEND,
  71                .size           = 1 * NAND_BLOCK_SIZE,
  72                .mask_flags     = 0,
  73        }, {
  74                /* Kernel */
  75                .name           = "kernel",
  76                .offset         = MTDPART_OFS_APPEND,
  77                .size           = SZ_4M,
  78                .mask_flags     = 0,
  79        }, {
  80                /* File System */
  81                .name           = "filesystem",
  82                .offset         = MTDPART_OFS_APPEND,
  83                .size           = MTDPART_SIZ_FULL,
  84                .mask_flags     = 0,
  85        }
  86        /* A few blocks at end hold a flash Bad Block Table. */
  87};
  88
  89static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = {
  90        .core_chipsel   = 0,
  91        .parts          = davinci_ntosd2_nandflash_partition,
  92        .nr_parts       = ARRAY_SIZE(davinci_ntosd2_nandflash_partition),
  93        .engine_type    = NAND_ECC_ENGINE_TYPE_ON_HOST,
  94        .ecc_bits       = 1,
  95        .bbt_options    = NAND_BBT_USE_FLASH,
  96};
  97
  98static struct resource davinci_ntosd2_nandflash_resource[] = {
  99        {
 100                .start          = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
 101                .end            = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
 102                .flags          = IORESOURCE_MEM,
 103        }, {
 104                .start          = DM644X_ASYNC_EMIF_CONTROL_BASE,
 105                .end            = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
 106                .flags          = IORESOURCE_MEM,
 107        },
 108};
 109
 110static struct platform_device davinci_ntosd2_nandflash_device = {
 111        .name           = "davinci_nand",
 112        .id             = 0,
 113        .dev            = {
 114                .platform_data  = &davinci_ntosd2_nandflash_data,
 115        },
 116        .num_resources  = ARRAY_SIZE(davinci_ntosd2_nandflash_resource),
 117        .resource       = davinci_ntosd2_nandflash_resource,
 118};
 119
 120static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
 121
 122static struct platform_device davinci_fb_device = {
 123        .name           = "davincifb",
 124        .id             = -1,
 125        .dev = {
 126                .dma_mask               = &davinci_fb_dma_mask,
 127                .coherent_dma_mask      = DMA_BIT_MASK(32),
 128        },
 129        .num_resources = 0,
 130};
 131
 132static const struct gpio_led ntosd2_leds[] = {
 133        { .name = "led1_green", .gpio = 10, },
 134        { .name = "led1_red",   .gpio = 11, },
 135        { .name = "led2_green", .gpio = 12, },
 136        { .name = "led2_red",   .gpio = 13, },
 137};
 138
 139static struct gpio_led_platform_data ntosd2_leds_data = {
 140        .num_leds       = ARRAY_SIZE(ntosd2_leds),
 141        .leds           = ntosd2_leds,
 142};
 143
 144static struct platform_device ntosd2_leds_dev = {
 145        .name = "leds-gpio",
 146        .id   = -1,
 147        .dev = {
 148                .platform_data          = &ntosd2_leds_data,
 149        },
 150};
 151
 152
 153static struct platform_device *davinci_ntosd2_devices[] __initdata = {
 154        &davinci_fb_device,
 155        &ntosd2_leds_dev,
 156};
 157
 158static void __init davinci_ntosd2_map_io(void)
 159{
 160        dm644x_init();
 161}
 162
 163static struct davinci_mmc_config davinci_ntosd2_mmc_config = {
 164        .wires          = 4,
 165};
 166
 167#define HAS_ATA         (IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
 168                         IS_ENABLED(CONFIG_PATA_BK3710))
 169
 170#define HAS_NAND        IS_ENABLED(CONFIG_MTD_NAND_DAVINCI)
 171
 172static __init void davinci_ntosd2_init(void)
 173{
 174        int ret;
 175        struct clk *aemif_clk;
 176        struct davinci_soc_info *soc_info = &davinci_soc_info;
 177
 178        dm644x_register_clocks();
 179
 180        dm644x_init_devices();
 181
 182        ret = dm644x_gpio_register();
 183        if (ret)
 184                pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
 185
 186        aemif_clk = clk_get(NULL, "aemif");
 187        clk_prepare_enable(aemif_clk);
 188
 189        if (HAS_ATA) {
 190                if (HAS_NAND)
 191                        pr_warn("WARNING: both IDE and Flash are enabled, but they share AEMIF pins\n"
 192                                "\tDisable IDE for NAND/NOR support\n");
 193                davinci_init_ide();
 194        } else if (HAS_NAND) {
 195                davinci_cfg_reg(DM644X_HPIEN_DISABLE);
 196                davinci_cfg_reg(DM644X_ATAEN_DISABLE);
 197
 198                /* only one device will be jumpered and detected */
 199                if (HAS_NAND)
 200                        platform_device_register(
 201                                        &davinci_ntosd2_nandflash_device);
 202        }
 203
 204        platform_add_devices(davinci_ntosd2_devices,
 205                                ARRAY_SIZE(davinci_ntosd2_devices));
 206
 207        davinci_serial_init(dm644x_serial_device);
 208        dm644x_init_asp();
 209
 210        soc_info->emac_pdata->phy_id = NEUROS_OSD2_PHY_ID;
 211
 212        davinci_setup_usb(1000, 8);
 213        /*
 214         * Mux the pins to be GPIOs, VLYNQEN is already done at startup.
 215         * The AEAWx are five new AEAW pins that can be muxed by separately.
 216         * They are a bitmask for GPIO management. According TI
 217         * documentation (https://www.ti.com/lit/gpn/tms320dm6446) to employ
 218         * gpio(10,11,12,13) for leds any combination of bits works except
 219         * four last. So we are to reset all five.
 220         */
 221        davinci_cfg_reg(DM644X_AEAW0);
 222        davinci_cfg_reg(DM644X_AEAW1);
 223        davinci_cfg_reg(DM644X_AEAW2);
 224        davinci_cfg_reg(DM644X_AEAW3);
 225        davinci_cfg_reg(DM644X_AEAW4);
 226
 227        davinci_setup_mmc(0, &davinci_ntosd2_mmc_config);
 228}
 229
 230MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
 231        /* Maintainer: Neuros Technologies <neuros@groups.google.com> */
 232        .atag_offset    = 0x100,
 233        .map_io          = davinci_ntosd2_map_io,
 234        .init_irq       = dm644x_init_irq,
 235        .init_time      = dm644x_init_time,
 236        .init_machine = davinci_ntosd2_init,
 237        .init_late      = davinci_init_late,
 238        .dma_zone_size  = SZ_128M,
 239MACHINE_END
 240