linux/sound/soc/sh/rcar/adg.c
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   1// SPDX-License-Identifier: GPL-2.0
   2//
   3// Helper routines for R-Car sound ADG.
   4//
   5//  Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6
   7#include <linux/clk-provider.h>
   8#include "rsnd.h"
   9
  10#define CLKA    0
  11#define CLKB    1
  12#define CLKC    2
  13#define CLKI    3
  14#define CLKMAX  4
  15
  16#define CLKOUT  0
  17#define CLKOUT1 1
  18#define CLKOUT2 2
  19#define CLKOUT3 3
  20#define CLKOUTMAX 4
  21
  22#define BRRx_MASK(x) (0x3FF & x)
  23
  24static struct rsnd_mod_ops adg_ops = {
  25        .name = "adg",
  26};
  27
  28struct rsnd_adg {
  29        struct clk *clk[CLKMAX];
  30        struct clk *clkout[CLKOUTMAX];
  31        struct clk_onecell_data onecell;
  32        struct rsnd_mod mod;
  33        int clk_rate[CLKMAX];
  34        u32 flags;
  35        u32 ckr;
  36        u32 rbga;
  37        u32 rbgb;
  38
  39        int rbga_rate_for_441khz; /* RBGA */
  40        int rbgb_rate_for_48khz;  /* RBGB */
  41};
  42
  43#define LRCLK_ASYNC     (1 << 0)
  44#define AUDIO_OUT_48    (1 << 1)
  45
  46#define for_each_rsnd_clk(pos, adg, i)          \
  47        for (i = 0;                             \
  48             (i < CLKMAX) &&                    \
  49             ((pos) = adg->clk[i]);             \
  50             i++)
  51#define for_each_rsnd_clkout(pos, adg, i)       \
  52        for (i = 0;                             \
  53             (i < CLKOUTMAX) &&                 \
  54             ((pos) = adg->clkout[i]);  \
  55             i++)
  56#define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
  57
  58static const char * const clk_name[] = {
  59        [CLKA]  = "clk_a",
  60        [CLKB]  = "clk_b",
  61        [CLKC]  = "clk_c",
  62        [CLKI]  = "clk_i",
  63};
  64
  65static u32 rsnd_adg_calculate_rbgx(unsigned long div)
  66{
  67        int i;
  68
  69        if (!div)
  70                return 0;
  71
  72        for (i = 3; i >= 0; i--) {
  73                int ratio = 2 << (i * 2);
  74                if (0 == (div % ratio))
  75                        return (u32)((i << 8) | ((div / ratio) - 1));
  76        }
  77
  78        return ~0;
  79}
  80
  81static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
  82{
  83        struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io);
  84        int id = rsnd_mod_id(ssi_mod);
  85        int ws = id;
  86
  87        if (rsnd_ssi_is_pin_sharing(io)) {
  88                switch (id) {
  89                case 1:
  90                case 2:
  91                case 9:
  92                        ws = 0;
  93                        break;
  94                case 4:
  95                        ws = 3;
  96                        break;
  97                case 8:
  98                        ws = 7;
  99                        break;
 100                }
 101        }
 102
 103        return (0x6 + ws) << 8;
 104}
 105
 106static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
 107                                       struct rsnd_dai_stream *io,
 108                                       unsigned int target_rate,
 109                                       unsigned int *target_val,
 110                                       unsigned int *target_en)
 111{
 112        struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 113        struct device *dev = rsnd_priv_to_dev(priv);
 114        int sel;
 115        unsigned int val, en;
 116        unsigned int min, diff;
 117        unsigned int sel_rate[] = {
 118                adg->clk_rate[CLKA],    /* 0000: CLKA */
 119                adg->clk_rate[CLKB],    /* 0001: CLKB */
 120                adg->clk_rate[CLKC],    /* 0010: CLKC */
 121                adg->rbga_rate_for_441khz,      /* 0011: RBGA */
 122                adg->rbgb_rate_for_48khz,       /* 0100: RBGB */
 123        };
 124
 125        min = ~0;
 126        val = 0;
 127        en = 0;
 128        for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
 129                int idx = 0;
 130                int step = 2;
 131                int div;
 132
 133                if (!sel_rate[sel])
 134                        continue;
 135
 136                for (div = 2; div <= 98304; div += step) {
 137                        diff = abs(target_rate - sel_rate[sel] / div);
 138                        if (min > diff) {
 139                                val = (sel << 8) | idx;
 140                                min = diff;
 141                                en = 1 << (sel + 1); /* fixme */
 142                        }
 143
 144                        /*
 145                         * step of 0_0000 / 0_0001 / 0_1101
 146                         * are out of order
 147                         */
 148                        if ((idx > 2) && (idx % 2))
 149                                step *= 2;
 150                        if (idx == 0x1c) {
 151                                div += step;
 152                                step *= 2;
 153                        }
 154                        idx++;
 155                }
 156        }
 157
 158        if (min == ~0) {
 159                dev_err(dev, "no Input clock\n");
 160                return;
 161        }
 162
 163        *target_val = val;
 164        if (target_en)
 165                *target_en = en;
 166}
 167
 168static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
 169                                       struct rsnd_dai_stream *io,
 170                                       unsigned int in_rate,
 171                                       unsigned int out_rate,
 172                                       u32 *in, u32 *out, u32 *en)
 173{
 174        struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
 175        unsigned int target_rate;
 176        u32 *target_val;
 177        u32 _in;
 178        u32 _out;
 179        u32 _en;
 180
 181        /* default = SSI WS */
 182        _in =
 183        _out = rsnd_adg_ssi_ws_timing_gen2(io);
 184
 185        target_rate = 0;
 186        target_val = NULL;
 187        _en = 0;
 188        if (runtime->rate != in_rate) {
 189                target_rate = out_rate;
 190                target_val  = &_out;
 191        } else if (runtime->rate != out_rate) {
 192                target_rate = in_rate;
 193                target_val  = &_in;
 194        }
 195
 196        if (target_rate)
 197                __rsnd_adg_get_timesel_ratio(priv, io,
 198                                             target_rate,
 199                                             target_val, &_en);
 200
 201        if (in)
 202                *in = _in;
 203        if (out)
 204                *out = _out;
 205        if (en)
 206                *en = _en;
 207}
 208
 209int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod,
 210                                 struct rsnd_dai_stream *io)
 211{
 212        struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod);
 213        struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 214        struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 215        int id = rsnd_mod_id(cmd_mod);
 216        int shift = (id % 2) ? 16 : 0;
 217        u32 mask, val;
 218
 219        rsnd_adg_get_timesel_ratio(priv, io,
 220                                   rsnd_src_get_in_rate(priv, io),
 221                                   rsnd_src_get_out_rate(priv, io),
 222                                   NULL, &val, NULL);
 223
 224        val  = val      << shift;
 225        mask = 0x0f1f   << shift;
 226
 227        rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val);
 228
 229        return 0;
 230}
 231
 232int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod,
 233                                  struct rsnd_dai_stream *io,
 234                                  unsigned int in_rate,
 235                                  unsigned int out_rate)
 236{
 237        struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
 238        struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 239        struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 240        u32 in, out;
 241        u32 mask, en;
 242        int id = rsnd_mod_id(src_mod);
 243        int shift = (id % 2) ? 16 : 0;
 244
 245        rsnd_mod_confirm_src(src_mod);
 246
 247        rsnd_adg_get_timesel_ratio(priv, io,
 248                                   in_rate, out_rate,
 249                                   &in, &out, &en);
 250
 251        in   = in       << shift;
 252        out  = out      << shift;
 253        mask = 0x0f1f   << shift;
 254
 255        rsnd_mod_bset(adg_mod, SRCIN_TIMSEL(id / 2),  mask, in);
 256        rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL(id / 2), mask, out);
 257
 258        if (en)
 259                rsnd_mod_bset(adg_mod, DIV_EN, en, en);
 260
 261        return 0;
 262}
 263
 264static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
 265{
 266        struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
 267        struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 268        struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 269        struct device *dev = rsnd_priv_to_dev(priv);
 270        int id = rsnd_mod_id(ssi_mod);
 271        int shift = (id % 4) * 8;
 272        u32 mask = 0xFF << shift;
 273
 274        rsnd_mod_confirm_ssi(ssi_mod);
 275
 276        val = val << shift;
 277
 278        /*
 279         * SSI 8 is not connected to ADG.
 280         * it works with SSI 7
 281         */
 282        if (id == 8)
 283                return;
 284
 285        rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL(id / 4), mask, val);
 286
 287        dev_dbg(dev, "AUDIO_CLK_SEL is 0x%x\n", val);
 288}
 289
 290int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate)
 291{
 292        struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 293        int i;
 294        int sel_table[] = {
 295                [CLKA] = 0x1,
 296                [CLKB] = 0x2,
 297                [CLKC] = 0x3,
 298                [CLKI] = 0x0,
 299        };
 300
 301        /*
 302         * find suitable clock from
 303         * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
 304         */
 305        for (i = 0; i < CLKMAX; i++)
 306                if (rate == adg->clk_rate[i])
 307                        return sel_table[i];
 308
 309        /*
 310         * find divided clock from BRGA/BRGB
 311         */
 312        if (rate == adg->rbga_rate_for_441khz)
 313                return 0x10;
 314
 315        if (rate == adg->rbgb_rate_for_48khz)
 316                return 0x20;
 317
 318        return -EIO;
 319}
 320
 321int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod)
 322{
 323        rsnd_adg_set_ssi_clk(ssi_mod, 0);
 324
 325        return 0;
 326}
 327
 328int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)
 329{
 330        struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
 331        struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 332        struct device *dev = rsnd_priv_to_dev(priv);
 333        struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 334        int data;
 335        u32 ckr = 0;
 336
 337        data = rsnd_adg_clk_query(priv, rate);
 338        if (data < 0)
 339                return data;
 340
 341        rsnd_adg_set_ssi_clk(ssi_mod, data);
 342
 343        if (rsnd_flags_has(adg, LRCLK_ASYNC)) {
 344                if (rsnd_flags_has(adg, AUDIO_OUT_48))
 345                        ckr = 0x80000000;
 346        } else {
 347                if (0 == (rate % 8000))
 348                        ckr = 0x80000000;
 349        }
 350
 351        rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr | ckr);
 352        rsnd_mod_write(adg_mod, BRRA,  adg->rbga);
 353        rsnd_mod_write(adg_mod, BRRB,  adg->rbgb);
 354
 355        dev_dbg(dev, "CLKOUT is based on BRG%c (= %dHz)\n",
 356                (ckr) ? 'B' : 'A',
 357                (ckr) ? adg->rbgb_rate_for_48khz :
 358                        adg->rbga_rate_for_441khz);
 359
 360        return 0;
 361}
 362
 363void rsnd_adg_clk_control(struct rsnd_priv *priv, int enable)
 364{
 365        struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 366        struct device *dev = rsnd_priv_to_dev(priv);
 367        struct clk *clk;
 368        int i;
 369
 370        for_each_rsnd_clk(clk, adg, i) {
 371                if (enable) {
 372                        int ret = clk_prepare_enable(clk);
 373
 374                        /*
 375                         * We shouldn't use clk_get_rate() under
 376                         * atomic context. Let's keep it when
 377                         * rsnd_adg_clk_enable() was called
 378                         */
 379                        adg->clk_rate[i] = 0;
 380                        if (ret < 0)
 381                                dev_warn(dev, "can't use clk %d\n", i);
 382                        else
 383                                adg->clk_rate[i] = clk_get_rate(clk);
 384                } else {
 385                        if (adg->clk_rate[i])
 386                                clk_disable_unprepare(clk);
 387                        adg->clk_rate[i] = 0;
 388                }
 389        }
 390}
 391
 392static void rsnd_adg_get_clkin(struct rsnd_priv *priv,
 393                               struct rsnd_adg *adg)
 394{
 395        struct device *dev = rsnd_priv_to_dev(priv);
 396        int i;
 397
 398        for (i = 0; i < CLKMAX; i++) {
 399                struct clk *clk = devm_clk_get(dev, clk_name[i]);
 400
 401                adg->clk[i] = IS_ERR(clk) ? NULL : clk;
 402        }
 403}
 404
 405static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
 406                                struct rsnd_adg *adg)
 407{
 408        struct clk *clk;
 409        struct device *dev = rsnd_priv_to_dev(priv);
 410        struct device_node *np = dev->of_node;
 411        struct property *prop;
 412        u32 ckr, rbgx, rbga, rbgb;
 413        u32 rate, div;
 414#define REQ_SIZE 2
 415        u32 req_rate[REQ_SIZE] = {};
 416        uint32_t count = 0;
 417        unsigned long req_48kHz_rate, req_441kHz_rate;
 418        int i, req_size;
 419        const char *parent_clk_name = NULL;
 420        static const char * const clkout_name[] = {
 421                [CLKOUT]  = "audio_clkout",
 422                [CLKOUT1] = "audio_clkout1",
 423                [CLKOUT2] = "audio_clkout2",
 424                [CLKOUT3] = "audio_clkout3",
 425        };
 426        int brg_table[] = {
 427                [CLKA] = 0x0,
 428                [CLKB] = 0x1,
 429                [CLKC] = 0x4,
 430                [CLKI] = 0x2,
 431        };
 432
 433        ckr = 0;
 434        rbga = 2; /* default 1/6 */
 435        rbgb = 2; /* default 1/6 */
 436
 437        /*
 438         * ADG supports BRRA/BRRB output only
 439         * this means all clkout0/1/2/3 will be same rate
 440         */
 441        prop = of_find_property(np, "clock-frequency", NULL);
 442        if (!prop)
 443                goto rsnd_adg_get_clkout_end;
 444
 445        req_size = prop->length / sizeof(u32);
 446        if (req_size > REQ_SIZE) {
 447                dev_err(dev,
 448                        "too many clock-frequency, use top %d\n", REQ_SIZE);
 449                req_size = REQ_SIZE;
 450        }
 451
 452        of_property_read_u32_array(np, "clock-frequency", req_rate, req_size);
 453        req_48kHz_rate = 0;
 454        req_441kHz_rate = 0;
 455        for (i = 0; i < req_size; i++) {
 456                if (0 == (req_rate[i] % 44100))
 457                        req_441kHz_rate = req_rate[i];
 458                if (0 == (req_rate[i] % 48000))
 459                        req_48kHz_rate = req_rate[i];
 460        }
 461
 462        if (req_rate[0] % 48000 == 0)
 463                rsnd_flags_set(adg, AUDIO_OUT_48);
 464
 465        if (of_get_property(np, "clkout-lr-asynchronous", NULL))
 466                rsnd_flags_set(adg, LRCLK_ASYNC);
 467
 468        /*
 469         * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
 470         * have 44.1kHz or 48kHz base clocks for now.
 471         *
 472         * SSI itself can divide parent clock by 1/1 - 1/16
 473         * see
 474         *      rsnd_adg_ssi_clk_try_start()
 475         *      rsnd_ssi_master_clk_start()
 476         */
 477        adg->rbga_rate_for_441khz       = 0;
 478        adg->rbgb_rate_for_48khz        = 0;
 479        for_each_rsnd_clk(clk, adg, i) {
 480                rate = clk_get_rate(clk);
 481
 482                if (0 == rate) /* not used */
 483                        continue;
 484
 485                /* RBGA */
 486                if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) {
 487                        div = 6;
 488                        if (req_441kHz_rate)
 489                                div = rate / req_441kHz_rate;
 490                        rbgx = rsnd_adg_calculate_rbgx(div);
 491                        if (BRRx_MASK(rbgx) == rbgx) {
 492                                rbga = rbgx;
 493                                adg->rbga_rate_for_441khz = rate / div;
 494                                ckr |= brg_table[i] << 20;
 495                                if (req_441kHz_rate &&
 496                                    !rsnd_flags_has(adg, AUDIO_OUT_48))
 497                                        parent_clk_name = __clk_get_name(clk);
 498                        }
 499                }
 500
 501                /* RBGB */
 502                if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) {
 503                        div = 6;
 504                        if (req_48kHz_rate)
 505                                div = rate / req_48kHz_rate;
 506                        rbgx = rsnd_adg_calculate_rbgx(div);
 507                        if (BRRx_MASK(rbgx) == rbgx) {
 508                                rbgb = rbgx;
 509                                adg->rbgb_rate_for_48khz = rate / div;
 510                                ckr |= brg_table[i] << 16;
 511                                if (req_48kHz_rate &&
 512                                    rsnd_flags_has(adg, AUDIO_OUT_48))
 513                                        parent_clk_name = __clk_get_name(clk);
 514                        }
 515                }
 516        }
 517
 518        /*
 519         * ADG supports BRRA/BRRB output only.
 520         * this means all clkout0/1/2/3 will be * same rate
 521         */
 522
 523        of_property_read_u32(np, "#clock-cells", &count);
 524        /*
 525         * for clkout
 526         */
 527        if (!count) {
 528                clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT],
 529                                              parent_clk_name, 0, req_rate[0]);
 530                if (!IS_ERR(clk)) {
 531                        adg->clkout[CLKOUT] = clk;
 532                        of_clk_add_provider(np, of_clk_src_simple_get, clk);
 533                }
 534        }
 535        /*
 536         * for clkout0/1/2/3
 537         */
 538        else {
 539                for (i = 0; i < CLKOUTMAX; i++) {
 540                        clk = clk_register_fixed_rate(dev, clkout_name[i],
 541                                                      parent_clk_name, 0,
 542                                                      req_rate[0]);
 543                        if (!IS_ERR(clk))
 544                                adg->clkout[i] = clk;
 545                }
 546                adg->onecell.clks       = adg->clkout;
 547                adg->onecell.clk_num    = CLKOUTMAX;
 548                of_clk_add_provider(np, of_clk_src_onecell_get,
 549                                    &adg->onecell);
 550        }
 551
 552rsnd_adg_get_clkout_end:
 553        adg->ckr = ckr;
 554        adg->rbga = rbga;
 555        adg->rbgb = rbgb;
 556}
 557
 558#ifdef DEBUG
 559static void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv, struct rsnd_adg *adg)
 560{
 561        struct device *dev = rsnd_priv_to_dev(priv);
 562        struct clk *clk;
 563        int i;
 564
 565        for_each_rsnd_clk(clk, adg, i)
 566                dev_dbg(dev, "%s    : %pa : %ld\n",
 567                        clk_name[i], clk, clk_get_rate(clk));
 568
 569        dev_dbg(dev, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
 570                adg->ckr, adg->rbga, adg->rbgb);
 571        dev_dbg(dev, "BRGA (for 44100 base) = %d\n", adg->rbga_rate_for_441khz);
 572        dev_dbg(dev, "BRGB (for 48000 base) = %d\n", adg->rbgb_rate_for_48khz);
 573
 574        /*
 575         * Actual CLKOUT will be exchanged in rsnd_adg_ssi_clk_try_start()
 576         * by BRGCKR::BRGCKR_31
 577         */
 578        for_each_rsnd_clkout(clk, adg, i)
 579                dev_dbg(dev, "clkout %d : %pa : %ld\n", i,
 580                        clk, clk_get_rate(clk));
 581}
 582#else
 583#define rsnd_adg_clk_dbg_info(priv, adg)
 584#endif
 585
 586int rsnd_adg_probe(struct rsnd_priv *priv)
 587{
 588        struct rsnd_adg *adg;
 589        struct device *dev = rsnd_priv_to_dev(priv);
 590        int ret;
 591
 592        adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
 593        if (!adg)
 594                return -ENOMEM;
 595
 596        ret = rsnd_mod_init(priv, &adg->mod, &adg_ops,
 597                      NULL, 0, 0);
 598        if (ret)
 599                return ret;
 600
 601        rsnd_adg_get_clkin(priv, adg);
 602        rsnd_adg_get_clkout(priv, adg);
 603        rsnd_adg_clk_dbg_info(priv, adg);
 604
 605        priv->adg = adg;
 606
 607        rsnd_adg_clk_enable(priv);
 608
 609        return 0;
 610}
 611
 612void rsnd_adg_remove(struct rsnd_priv *priv)
 613{
 614        struct device *dev = rsnd_priv_to_dev(priv);
 615        struct device_node *np = dev->of_node;
 616        struct rsnd_adg *adg = priv->adg;
 617        struct clk *clk;
 618        int i;
 619
 620        for_each_rsnd_clkout(clk, adg, i)
 621                if (adg->clkout[i])
 622                        clk_unregister_fixed_rate(adg->clkout[i]);
 623
 624        of_clk_del_provider(np);
 625
 626        rsnd_adg_clk_disable(priv);
 627}
 628