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12#include <linux/bitrev.h>
13#include <linux/clk.h>
14#include <linux/module.h>
15#include <linux/of_address.h>
16#include <linux/of_device.h>
17#include <linux/of_irq.h>
18#include <linux/regmap.h>
19#include <linux/pm_runtime.h>
20
21#include <sound/asoundef.h>
22#include <sound/dmaengine_pcm.h>
23#include <sound/soc.h>
24
25#include "fsl_spdif.h"
26#include "imx-pcm.h"
27
28#define FSL_SPDIF_TXFIFO_WML 0x8
29#define FSL_SPDIF_RXFIFO_WML 0x8
30
31#define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC)
32#define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |\
33 INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |\
34 INT_UQ_SYNC | INT_UQ_ERR | INT_RXFIFO_RESYNC |\
35 INT_LOSS_LOCK | INT_DPLL_LOCKED)
36
37#define SIE_INTR_FOR(tx) (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE)
38
39
40static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb };
41#define SRPC_NODPLL_START1 0x5
42#define SRPC_NODPLL_START2 0xc
43
44#define DEFAULT_RXCLK_SRC 1
45
46
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56
57struct fsl_spdif_soc_data {
58 bool imx;
59 bool shared_root_clock;
60 u32 interrupts;
61 u32 tx_burst;
62 u32 rx_burst;
63 u64 tx_formats;
64};
65
66
67
68
69
70struct spdif_mixer_control {
71
72 spinlock_t ctl_lock;
73
74
75 unsigned char ch_status[4];
76
77
78 unsigned char subcode[2 * SPDIF_UBITS_SIZE];
79
80
81 unsigned char qsub[2 * SPDIF_QSUB_SIZE];
82
83
84 u32 upos;
85 u32 qpos;
86
87
88 u32 ready_buf;
89};
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113struct fsl_spdif_priv {
114 const struct fsl_spdif_soc_data *soc;
115 struct spdif_mixer_control fsl_spdif_control;
116 struct snd_soc_dai_driver cpu_dai_drv;
117 struct platform_device *pdev;
118 struct regmap *regmap;
119 bool dpll_locked;
120 u32 txrate[SPDIF_TXRATE_MAX];
121 u8 txclk_df[SPDIF_TXRATE_MAX];
122 u16 sysclk_df[SPDIF_TXRATE_MAX];
123 u8 txclk_src[SPDIF_TXRATE_MAX];
124 u8 rxclk_src;
125 struct clk *txclk[SPDIF_TXRATE_MAX];
126 struct clk *rxclk;
127 struct clk *coreclk;
128 struct clk *sysclk;
129 struct clk *spbaclk;
130 struct snd_dmaengine_dai_dma_data dma_params_tx;
131 struct snd_dmaengine_dai_dma_data dma_params_rx;
132
133 u32 regcache_srpc;
134};
135
136static struct fsl_spdif_soc_data fsl_spdif_vf610 = {
137 .imx = false,
138 .shared_root_clock = false,
139 .interrupts = 1,
140 .tx_burst = FSL_SPDIF_TXFIFO_WML,
141 .rx_burst = FSL_SPDIF_RXFIFO_WML,
142 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK,
143};
144
145static struct fsl_spdif_soc_data fsl_spdif_imx35 = {
146 .imx = true,
147 .shared_root_clock = false,
148 .interrupts = 1,
149 .tx_burst = FSL_SPDIF_TXFIFO_WML,
150 .rx_burst = FSL_SPDIF_RXFIFO_WML,
151 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK,
152};
153
154static struct fsl_spdif_soc_data fsl_spdif_imx6sx = {
155 .imx = true,
156 .shared_root_clock = true,
157 .interrupts = 1,
158 .tx_burst = FSL_SPDIF_TXFIFO_WML,
159 .rx_burst = FSL_SPDIF_RXFIFO_WML,
160 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK,
161
162};
163
164static struct fsl_spdif_soc_data fsl_spdif_imx8qm = {
165 .imx = true,
166 .shared_root_clock = true,
167 .interrupts = 2,
168 .tx_burst = 2,
169 .rx_burst = 2,
170 .tx_formats = SNDRV_PCM_FMTBIT_S24_LE,
171};
172
173
174static inline bool fsl_spdif_can_set_clk_rate(struct fsl_spdif_priv *spdif, int clk)
175{
176 return (clk == STC_TXCLK_SPDIF_ROOT) && !spdif->soc->shared_root_clock;
177}
178
179
180static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv)
181{
182 struct regmap *regmap = spdif_priv->regmap;
183 struct platform_device *pdev = spdif_priv->pdev;
184 u32 locked;
185
186 regmap_read(regmap, REG_SPDIF_SRPC, &locked);
187 locked &= SRPC_DPLL_LOCKED;
188
189 dev_dbg(&pdev->dev, "isr: Rx dpll %s \n",
190 locked ? "locked" : "loss lock");
191
192 spdif_priv->dpll_locked = locked ? true : false;
193}
194
195
196static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv)
197{
198 struct regmap *regmap = spdif_priv->regmap;
199 struct platform_device *pdev = spdif_priv->pdev;
200
201 dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n");
202
203
204 if (!spdif_priv->dpll_locked)
205 regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0);
206}
207
208
209static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name)
210{
211 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
212 struct regmap *regmap = spdif_priv->regmap;
213 struct platform_device *pdev = spdif_priv->pdev;
214 u32 *pos, size, val, reg;
215
216 switch (name) {
217 case 'U':
218 pos = &ctrl->upos;
219 size = SPDIF_UBITS_SIZE;
220 reg = REG_SPDIF_SRU;
221 break;
222 case 'Q':
223 pos = &ctrl->qpos;
224 size = SPDIF_QSUB_SIZE;
225 reg = REG_SPDIF_SRQ;
226 break;
227 default:
228 dev_err(&pdev->dev, "unsupported channel name\n");
229 return;
230 }
231
232 dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name);
233
234 if (*pos >= size * 2) {
235 *pos = 0;
236 } else if (unlikely((*pos % size) + 3 > size)) {
237 dev_err(&pdev->dev, "User bit receive buffer overflow\n");
238 return;
239 }
240
241 regmap_read(regmap, reg, &val);
242 ctrl->subcode[*pos++] = val >> 16;
243 ctrl->subcode[*pos++] = val >> 8;
244 ctrl->subcode[*pos++] = val;
245}
246
247
248static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv)
249{
250 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
251 struct platform_device *pdev = spdif_priv->pdev;
252
253 dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n");
254
255
256 if (ctrl->qpos == 0)
257 return;
258
259
260 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1;
261}
262
263
264static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv)
265{
266 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
267 struct regmap *regmap = spdif_priv->regmap;
268 struct platform_device *pdev = spdif_priv->pdev;
269 u32 val;
270
271 dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n");
272
273
274 regmap_read(regmap, REG_SPDIF_SRU, &val);
275 regmap_read(regmap, REG_SPDIF_SRQ, &val);
276
277
278 ctrl->ready_buf = 0;
279 ctrl->upos = 0;
280 ctrl->qpos = 0;
281}
282
283
284static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv)
285{
286 struct regmap *regmap = spdif_priv->regmap;
287 u32 val, val2;
288
289 regmap_read(regmap, REG_SPDIF_SIS, &val);
290 regmap_read(regmap, REG_SPDIF_SIE, &val2);
291
292 regmap_write(regmap, REG_SPDIF_SIC, val & val2);
293
294 return val;
295}
296
297static irqreturn_t spdif_isr(int irq, void *devid)
298{
299 struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid;
300 struct platform_device *pdev = spdif_priv->pdev;
301 u32 sis;
302
303 sis = spdif_intr_status_clear(spdif_priv);
304
305 if (sis & INT_DPLL_LOCKED)
306 spdif_irq_dpll_lock(spdif_priv);
307
308 if (sis & INT_TXFIFO_UNOV)
309 dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n");
310
311 if (sis & INT_TXFIFO_RESYNC)
312 dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n");
313
314 if (sis & INT_CNEW)
315 dev_dbg(&pdev->dev, "isr: cstatus new\n");
316
317 if (sis & INT_VAL_NOGOOD)
318 dev_dbg(&pdev->dev, "isr: validity flag no good\n");
319
320 if (sis & INT_SYM_ERR)
321 spdif_irq_sym_error(spdif_priv);
322
323 if (sis & INT_BIT_ERR)
324 dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n");
325
326 if (sis & INT_URX_FUL)
327 spdif_irq_uqrx_full(spdif_priv, 'U');
328
329 if (sis & INT_URX_OV)
330 dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n");
331
332 if (sis & INT_QRX_FUL)
333 spdif_irq_uqrx_full(spdif_priv, 'Q');
334
335 if (sis & INT_QRX_OV)
336 dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n");
337
338 if (sis & INT_UQ_SYNC)
339 spdif_irq_uq_sync(spdif_priv);
340
341 if (sis & INT_UQ_ERR)
342 spdif_irq_uq_err(spdif_priv);
343
344 if (sis & INT_RXFIFO_UNOV)
345 dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n");
346
347 if (sis & INT_RXFIFO_RESYNC)
348 dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n");
349
350 if (sis & INT_LOSS_LOCK)
351 spdif_irq_dpll_lock(spdif_priv);
352
353
354 if (sis & INT_TX_EM)
355 dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n");
356
357
358 if (sis & INT_RXFIFO_FUL)
359 dev_dbg(&pdev->dev, "isr: Rx FIFO full\n");
360
361 return IRQ_HANDLED;
362}
363
364static int spdif_softreset(struct fsl_spdif_priv *spdif_priv)
365{
366 struct regmap *regmap = spdif_priv->regmap;
367 u32 val, cycle = 1000;
368
369 regcache_cache_bypass(regmap, true);
370
371 regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET);
372
373
374
375
376
377 do {
378 regmap_read(regmap, REG_SPDIF_SCR, &val);
379 } while ((val & SCR_SOFT_RESET) && cycle--);
380
381 regcache_cache_bypass(regmap, false);
382 regcache_mark_dirty(regmap);
383 regcache_sync(regmap);
384
385 if (cycle)
386 return 0;
387 else
388 return -EBUSY;
389}
390
391static void spdif_set_cstatus(struct spdif_mixer_control *ctrl,
392 u8 mask, u8 cstatus)
393{
394 ctrl->ch_status[3] &= ~mask;
395 ctrl->ch_status[3] |= cstatus & mask;
396}
397
398static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv)
399{
400 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
401 struct regmap *regmap = spdif_priv->regmap;
402 struct platform_device *pdev = spdif_priv->pdev;
403 u32 ch_status;
404
405 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) |
406 (bitrev8(ctrl->ch_status[1]) << 8) |
407 bitrev8(ctrl->ch_status[2]);
408 regmap_write(regmap, REG_SPDIF_STCSCH, ch_status);
409
410 dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status);
411
412 ch_status = bitrev8(ctrl->ch_status[3]) << 16;
413 regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);
414
415 dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);
416}
417
418
419static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv,
420 enum spdif_gainsel gainsel, int dpll_locked)
421{
422 struct regmap *regmap = spdif_priv->regmap;
423 u8 clksrc = spdif_priv->rxclk_src;
424
425 if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX)
426 return -EINVAL;
427
428 regmap_update_bits(regmap, REG_SPDIF_SRPC,
429 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
430 SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel));
431
432 return 0;
433}
434
435static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
436 int sample_rate)
437{
438 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
439 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
440 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
441 struct regmap *regmap = spdif_priv->regmap;
442 struct platform_device *pdev = spdif_priv->pdev;
443 unsigned long csfs = 0;
444 u32 stc, mask, rate;
445 u16 sysclk_df;
446 u8 clk, txclk_df;
447 int ret;
448
449 switch (sample_rate) {
450 case 32000:
451 rate = SPDIF_TXRATE_32000;
452 csfs = IEC958_AES3_CON_FS_32000;
453 break;
454 case 44100:
455 rate = SPDIF_TXRATE_44100;
456 csfs = IEC958_AES3_CON_FS_44100;
457 break;
458 case 48000:
459 rate = SPDIF_TXRATE_48000;
460 csfs = IEC958_AES3_CON_FS_48000;
461 break;
462 case 88200:
463 rate = SPDIF_TXRATE_88200;
464 csfs = IEC958_AES3_CON_FS_88200;
465 break;
466 case 96000:
467 rate = SPDIF_TXRATE_96000;
468 csfs = IEC958_AES3_CON_FS_96000;
469 break;
470 case 176400:
471 rate = SPDIF_TXRATE_176400;
472 csfs = IEC958_AES3_CON_FS_176400;
473 break;
474 case 192000:
475 rate = SPDIF_TXRATE_192000;
476 csfs = IEC958_AES3_CON_FS_192000;
477 break;
478 default:
479 dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate);
480 return -EINVAL;
481 }
482
483 clk = spdif_priv->txclk_src[rate];
484 if (clk >= STC_TXCLK_SRC_MAX) {
485 dev_err(&pdev->dev, "tx clock source is out of range\n");
486 return -EINVAL;
487 }
488
489 txclk_df = spdif_priv->txclk_df[rate];
490 if (txclk_df == 0) {
491 dev_err(&pdev->dev, "the txclk_df can't be zero\n");
492 return -EINVAL;
493 }
494
495 sysclk_df = spdif_priv->sysclk_df[rate];
496
497 if (!fsl_spdif_can_set_clk_rate(spdif_priv, clk))
498 goto clk_set_bypass;
499
500
501 ret = clk_set_rate(spdif_priv->txclk[rate],
502 64 * sample_rate * txclk_df);
503 if (ret) {
504 dev_err(&pdev->dev, "failed to set tx clock rate\n");
505 return ret;
506 }
507
508clk_set_bypass:
509 dev_dbg(&pdev->dev, "expected clock rate = %d\n",
510 (64 * sample_rate * txclk_df * sysclk_df));
511 dev_dbg(&pdev->dev, "actual clock rate = %ld\n",
512 clk_get_rate(spdif_priv->txclk[rate]));
513
514
515 spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs);
516
517
518 stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) |
519 STC_TXCLK_DF(txclk_df) | STC_SYSCLK_DF(sysclk_df);
520 mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK |
521 STC_TXCLK_DF_MASK | STC_SYSCLK_DF_MASK;
522 regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc);
523
524 dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n",
525 spdif_priv->txrate[rate], sample_rate);
526
527 return 0;
528}
529
530static int fsl_spdif_startup(struct snd_pcm_substream *substream,
531 struct snd_soc_dai *cpu_dai)
532{
533 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
534 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
535 struct platform_device *pdev = spdif_priv->pdev;
536 struct regmap *regmap = spdif_priv->regmap;
537 u32 scr, mask;
538 int ret;
539
540
541 if (!snd_soc_dai_active(cpu_dai)) {
542 ret = spdif_softreset(spdif_priv);
543 if (ret) {
544 dev_err(&pdev->dev, "failed to soft reset\n");
545 return ret;
546 }
547
548
549 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);
550 }
551
552 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
553 scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL |
554 SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP |
555 SCR_TXFIFO_FSEL_IF8;
556 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
557 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
558 SCR_TXFIFO_FSEL_MASK;
559 } else {
560 scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC;
561 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
562 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
563 }
564 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
565
566
567 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0);
568
569 return 0;
570}
571
572static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
573 struct snd_soc_dai *cpu_dai)
574{
575 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
576 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
577 struct regmap *regmap = spdif_priv->regmap;
578 u32 scr, mask;
579
580 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
581 scr = 0;
582 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
583 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
584 SCR_TXFIFO_FSEL_MASK;
585 } else {
586 scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO;
587 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
588 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
589 }
590 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
591
592
593 if (!snd_soc_dai_active(cpu_dai)) {
594 spdif_intr_status_clear(spdif_priv);
595 regmap_update_bits(regmap, REG_SPDIF_SCR,
596 SCR_LOW_POWER, SCR_LOW_POWER);
597 }
598}
599
600static int fsl_spdif_hw_params(struct snd_pcm_substream *substream,
601 struct snd_pcm_hw_params *params,
602 struct snd_soc_dai *dai)
603{
604 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
605 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
606 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
607 struct platform_device *pdev = spdif_priv->pdev;
608 u32 sample_rate = params_rate(params);
609 int ret = 0;
610
611 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
612 ret = spdif_set_sample_rate(substream, sample_rate);
613 if (ret) {
614 dev_err(&pdev->dev, "%s: set sample rate failed: %d\n",
615 __func__, sample_rate);
616 return ret;
617 }
618 spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK,
619 IEC958_AES3_CON_CLOCK_1000PPM);
620 spdif_write_channel_status(spdif_priv);
621 } else {
622
623 ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1);
624 }
625
626 return ret;
627}
628
629static int fsl_spdif_trigger(struct snd_pcm_substream *substream,
630 int cmd, struct snd_soc_dai *dai)
631{
632 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
633 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
634 struct regmap *regmap = spdif_priv->regmap;
635 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
636 u32 intr = SIE_INTR_FOR(tx);
637 u32 dmaen = SCR_DMA_xX_EN(tx);
638
639 switch (cmd) {
640 case SNDRV_PCM_TRIGGER_START:
641 case SNDRV_PCM_TRIGGER_RESUME:
642 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
643 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr);
644 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen);
645 break;
646 case SNDRV_PCM_TRIGGER_STOP:
647 case SNDRV_PCM_TRIGGER_SUSPEND:
648 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
649 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0);
650 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0);
651 break;
652 default:
653 return -EINVAL;
654 }
655
656 return 0;
657}
658
659static const struct snd_soc_dai_ops fsl_spdif_dai_ops = {
660 .startup = fsl_spdif_startup,
661 .hw_params = fsl_spdif_hw_params,
662 .trigger = fsl_spdif_trigger,
663 .shutdown = fsl_spdif_shutdown,
664};
665
666
667
668
669
670
671
672
673
674
675
676
677static int fsl_spdif_info(struct snd_kcontrol *kcontrol,
678 struct snd_ctl_elem_info *uinfo)
679{
680 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
681 uinfo->count = 1;
682
683 return 0;
684}
685
686static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol,
687 struct snd_ctl_elem_value *uvalue)
688{
689 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
690 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
691 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
692
693 uvalue->value.iec958.status[0] = ctrl->ch_status[0];
694 uvalue->value.iec958.status[1] = ctrl->ch_status[1];
695 uvalue->value.iec958.status[2] = ctrl->ch_status[2];
696 uvalue->value.iec958.status[3] = ctrl->ch_status[3];
697
698 return 0;
699}
700
701static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol,
702 struct snd_ctl_elem_value *uvalue)
703{
704 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
705 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
706 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
707
708 ctrl->ch_status[0] = uvalue->value.iec958.status[0];
709 ctrl->ch_status[1] = uvalue->value.iec958.status[1];
710 ctrl->ch_status[2] = uvalue->value.iec958.status[2];
711 ctrl->ch_status[3] = uvalue->value.iec958.status[3];
712
713 spdif_write_channel_status(spdif_priv);
714
715 return 0;
716}
717
718
719static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol,
720 struct snd_ctl_elem_value *ucontrol)
721{
722 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
723 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
724 struct regmap *regmap = spdif_priv->regmap;
725 u32 cstatus, val;
726
727 regmap_read(regmap, REG_SPDIF_SIS, &val);
728 if (!(val & INT_CNEW))
729 return -EAGAIN;
730
731 regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus);
732 ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF;
733 ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF;
734 ucontrol->value.iec958.status[2] = cstatus & 0xFF;
735
736 regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus);
737 ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF;
738 ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF;
739 ucontrol->value.iec958.status[5] = cstatus & 0xFF;
740
741
742 regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW);
743
744 return 0;
745}
746
747
748
749
750
751static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol,
752 struct snd_ctl_elem_value *ucontrol)
753{
754 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
755 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
756 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
757 unsigned long flags;
758 int ret = -EAGAIN;
759
760 spin_lock_irqsave(&ctrl->ctl_lock, flags);
761 if (ctrl->ready_buf) {
762 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE;
763 memcpy(&ucontrol->value.iec958.subcode[0],
764 &ctrl->subcode[idx], SPDIF_UBITS_SIZE);
765 ret = 0;
766 }
767 spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
768
769 return ret;
770}
771
772
773static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol,
774 struct snd_ctl_elem_info *uinfo)
775{
776 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
777 uinfo->count = SPDIF_QSUB_SIZE;
778
779 return 0;
780}
781
782
783static int fsl_spdif_qget(struct snd_kcontrol *kcontrol,
784 struct snd_ctl_elem_value *ucontrol)
785{
786 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
787 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
788 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
789 unsigned long flags;
790 int ret = -EAGAIN;
791
792 spin_lock_irqsave(&ctrl->ctl_lock, flags);
793 if (ctrl->ready_buf) {
794 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE;
795 memcpy(&ucontrol->value.bytes.data[0],
796 &ctrl->qsub[idx], SPDIF_QSUB_SIZE);
797 ret = 0;
798 }
799 spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
800
801 return ret;
802}
803
804
805static int fsl_spdif_rx_vbit_get(struct snd_kcontrol *kcontrol,
806 struct snd_ctl_elem_value *ucontrol)
807{
808 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
809 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
810 struct regmap *regmap = spdif_priv->regmap;
811 u32 val;
812
813 regmap_read(regmap, REG_SPDIF_SIS, &val);
814 ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0;
815 regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD);
816
817 return 0;
818}
819
820static int fsl_spdif_tx_vbit_get(struct snd_kcontrol *kcontrol,
821 struct snd_ctl_elem_value *ucontrol)
822{
823 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
824 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
825 struct regmap *regmap = spdif_priv->regmap;
826 u32 val;
827
828 regmap_read(regmap, REG_SPDIF_SCR, &val);
829 val = (val & SCR_VAL_MASK) >> SCR_VAL_OFFSET;
830 val = 1 - val;
831 ucontrol->value.integer.value[0] = val;
832
833 return 0;
834}
835
836static int fsl_spdif_tx_vbit_put(struct snd_kcontrol *kcontrol,
837 struct snd_ctl_elem_value *ucontrol)
838{
839 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
840 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
841 struct regmap *regmap = spdif_priv->regmap;
842 u32 val = (1 - ucontrol->value.integer.value[0]) << SCR_VAL_OFFSET;
843
844 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_VAL_MASK, val);
845
846 return 0;
847}
848
849
850static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol,
851 struct snd_ctl_elem_info *uinfo)
852{
853 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
854 uinfo->count = 1;
855 uinfo->value.integer.min = 16000;
856 uinfo->value.integer.max = 192000;
857
858 return 0;
859}
860
861static u32 gainsel_multi[GAINSEL_MULTI_MAX] = {
862 24, 16, 12, 8, 6, 4, 3,
863};
864
865
866static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv,
867 enum spdif_gainsel gainsel)
868{
869 struct regmap *regmap = spdif_priv->regmap;
870 struct platform_device *pdev = spdif_priv->pdev;
871 u64 tmpval64, busclk_freq = 0;
872 u32 freqmeas, phaseconf;
873 u8 clksrc;
874
875 regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas);
876 regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf);
877
878 clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf;
879
880
881 if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED))
882 busclk_freq = clk_get_rate(spdif_priv->sysclk);
883
884
885 tmpval64 = (u64) busclk_freq * freqmeas;
886 do_div(tmpval64, gainsel_multi[gainsel] * 1024);
887 do_div(tmpval64, 128 * 1024);
888
889 dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas);
890 dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq);
891 dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64);
892
893 return (int)tmpval64;
894}
895
896
897
898
899
900
901static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol,
902 struct snd_ctl_elem_value *ucontrol)
903{
904 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
905 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
906 int rate = 0;
907
908 if (spdif_priv->dpll_locked)
909 rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL);
910
911 ucontrol->value.integer.value[0] = rate;
912
913 return 0;
914}
915
916
917
918
919
920
921static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol,
922 struct snd_ctl_elem_value *ucontrol)
923{
924 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
925 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
926 struct regmap *regmap = spdif_priv->regmap;
927 u32 val;
928
929 regmap_read(regmap, REG_SPDIF_SRCD, &val);
930 ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0;
931
932 return 0;
933}
934
935
936
937
938
939
940static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol,
941 struct snd_ctl_elem_value *ucontrol)
942{
943 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
944 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
945 struct regmap *regmap = spdif_priv->regmap;
946 u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET;
947
948 regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val);
949
950 return 0;
951}
952
953
954static struct snd_kcontrol_new fsl_spdif_ctrls[] = {
955
956 {
957 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
958 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
959 .access = SNDRV_CTL_ELEM_ACCESS_READ |
960 SNDRV_CTL_ELEM_ACCESS_WRITE |
961 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
962 .info = fsl_spdif_info,
963 .get = fsl_spdif_pb_get,
964 .put = fsl_spdif_pb_put,
965 },
966 {
967 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
968 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
969 .access = SNDRV_CTL_ELEM_ACCESS_READ |
970 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
971 .info = fsl_spdif_info,
972 .get = fsl_spdif_capture_get,
973 },
974
975 {
976 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
977 .name = "IEC958 Subcode Capture Default",
978 .access = SNDRV_CTL_ELEM_ACCESS_READ |
979 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
980 .info = fsl_spdif_info,
981 .get = fsl_spdif_subcode_get,
982 },
983 {
984 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
985 .name = "IEC958 Q-subcode Capture Default",
986 .access = SNDRV_CTL_ELEM_ACCESS_READ |
987 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
988 .info = fsl_spdif_qinfo,
989 .get = fsl_spdif_qget,
990 },
991
992 {
993 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
994 .name = "IEC958 RX V-Bit Errors",
995 .access = SNDRV_CTL_ELEM_ACCESS_READ |
996 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
997 .info = snd_ctl_boolean_mono_info,
998 .get = fsl_spdif_rx_vbit_get,
999 },
1000 {
1001 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1002 .name = "IEC958 TX V-Bit",
1003 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1004 SNDRV_CTL_ELEM_ACCESS_WRITE |
1005 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1006 .info = snd_ctl_boolean_mono_info,
1007 .get = fsl_spdif_tx_vbit_get,
1008 .put = fsl_spdif_tx_vbit_put,
1009 },
1010
1011 {
1012 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1013 .name = "RX Sample Rate",
1014 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1015 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1016 .info = fsl_spdif_rxrate_info,
1017 .get = fsl_spdif_rxrate_get,
1018 },
1019
1020 {
1021 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1022 .name = "IEC958 USyncMode CDText",
1023 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1024 SNDRV_CTL_ELEM_ACCESS_WRITE |
1025 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1026 .info = snd_ctl_boolean_mono_info,
1027 .get = fsl_spdif_usync_get,
1028 .put = fsl_spdif_usync_put,
1029 },
1030};
1031
1032static int fsl_spdif_dai_probe(struct snd_soc_dai *dai)
1033{
1034 struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai);
1035
1036 snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx,
1037 &spdif_private->dma_params_rx);
1038
1039 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls));
1040
1041
1042 regmap_update_bits(spdif_private->regmap, REG_SPDIF_SCR,
1043 SCR_VAL_MASK, SCR_VAL_CLEAR);
1044
1045 return 0;
1046}
1047
1048static struct snd_soc_dai_driver fsl_spdif_dai = {
1049 .probe = &fsl_spdif_dai_probe,
1050 .playback = {
1051 .stream_name = "CPU-Playback",
1052 .channels_min = 2,
1053 .channels_max = 2,
1054 .rates = FSL_SPDIF_RATES_PLAYBACK,
1055 .formats = FSL_SPDIF_FORMATS_PLAYBACK,
1056 },
1057 .capture = {
1058 .stream_name = "CPU-Capture",
1059 .channels_min = 2,
1060 .channels_max = 2,
1061 .rates = FSL_SPDIF_RATES_CAPTURE,
1062 .formats = FSL_SPDIF_FORMATS_CAPTURE,
1063 },
1064 .ops = &fsl_spdif_dai_ops,
1065};
1066
1067static const struct snd_soc_component_driver fsl_spdif_component = {
1068 .name = "fsl-spdif",
1069};
1070
1071
1072static const struct reg_default fsl_spdif_reg_defaults[] = {
1073 {REG_SPDIF_SCR, 0x00000400},
1074 {REG_SPDIF_SRCD, 0x00000000},
1075 {REG_SPDIF_SIE, 0x00000000},
1076 {REG_SPDIF_STL, 0x00000000},
1077 {REG_SPDIF_STR, 0x00000000},
1078 {REG_SPDIF_STCSCH, 0x00000000},
1079 {REG_SPDIF_STCSCL, 0x00000000},
1080 {REG_SPDIF_STC, 0x00020f00},
1081};
1082
1083static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg)
1084{
1085 switch (reg) {
1086 case REG_SPDIF_SCR:
1087 case REG_SPDIF_SRCD:
1088 case REG_SPDIF_SRPC:
1089 case REG_SPDIF_SIE:
1090 case REG_SPDIF_SIS:
1091 case REG_SPDIF_SRL:
1092 case REG_SPDIF_SRR:
1093 case REG_SPDIF_SRCSH:
1094 case REG_SPDIF_SRCSL:
1095 case REG_SPDIF_SRU:
1096 case REG_SPDIF_SRQ:
1097 case REG_SPDIF_STCSCH:
1098 case REG_SPDIF_STCSCL:
1099 case REG_SPDIF_SRFM:
1100 case REG_SPDIF_STC:
1101 return true;
1102 default:
1103 return false;
1104 }
1105}
1106
1107static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg)
1108{
1109 switch (reg) {
1110 case REG_SPDIF_SRPC:
1111 case REG_SPDIF_SIS:
1112 case REG_SPDIF_SRL:
1113 case REG_SPDIF_SRR:
1114 case REG_SPDIF_SRCSH:
1115 case REG_SPDIF_SRCSL:
1116 case REG_SPDIF_SRU:
1117 case REG_SPDIF_SRQ:
1118 case REG_SPDIF_SRFM:
1119 return true;
1120 default:
1121 return false;
1122 }
1123}
1124
1125static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg)
1126{
1127 switch (reg) {
1128 case REG_SPDIF_SCR:
1129 case REG_SPDIF_SRCD:
1130 case REG_SPDIF_SRPC:
1131 case REG_SPDIF_SIE:
1132 case REG_SPDIF_SIC:
1133 case REG_SPDIF_STL:
1134 case REG_SPDIF_STR:
1135 case REG_SPDIF_STCSCH:
1136 case REG_SPDIF_STCSCL:
1137 case REG_SPDIF_STC:
1138 return true;
1139 default:
1140 return false;
1141 }
1142}
1143
1144static const struct regmap_config fsl_spdif_regmap_config = {
1145 .reg_bits = 32,
1146 .reg_stride = 4,
1147 .val_bits = 32,
1148
1149 .max_register = REG_SPDIF_STC,
1150 .reg_defaults = fsl_spdif_reg_defaults,
1151 .num_reg_defaults = ARRAY_SIZE(fsl_spdif_reg_defaults),
1152 .readable_reg = fsl_spdif_readable_reg,
1153 .volatile_reg = fsl_spdif_volatile_reg,
1154 .writeable_reg = fsl_spdif_writeable_reg,
1155 .cache_type = REGCACHE_FLAT,
1156};
1157
1158static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv,
1159 struct clk *clk, u64 savesub,
1160 enum spdif_txrate index, bool round)
1161{
1162 static const u32 rate[] = { 32000, 44100, 48000, 88200, 96000, 176400,
1163 192000, };
1164 bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk);
1165 u64 rate_ideal, rate_actual, sub;
1166 u32 arate;
1167 u16 sysclk_dfmin, sysclk_dfmax, sysclk_df;
1168 u8 txclk_df;
1169
1170
1171 sysclk_dfmin = is_sysclk ? 2 : 1;
1172 sysclk_dfmax = is_sysclk ? 512 : 1;
1173
1174 for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) {
1175 for (txclk_df = 1; txclk_df <= 128; txclk_df++) {
1176 rate_ideal = rate[index] * txclk_df * 64ULL;
1177 if (round)
1178 rate_actual = clk_round_rate(clk, rate_ideal);
1179 else
1180 rate_actual = clk_get_rate(clk);
1181
1182 arate = rate_actual / 64;
1183 arate /= txclk_df * sysclk_df;
1184
1185 if (arate == rate[index]) {
1186
1187 savesub = 0;
1188 spdif_priv->txclk_df[index] = txclk_df;
1189 spdif_priv->sysclk_df[index] = sysclk_df;
1190 spdif_priv->txrate[index] = arate;
1191 goto out;
1192 } else if (arate / rate[index] == 1) {
1193
1194 sub = (u64)(arate - rate[index]) * 100000;
1195 do_div(sub, rate[index]);
1196 if (sub >= savesub)
1197 continue;
1198 savesub = sub;
1199 spdif_priv->txclk_df[index] = txclk_df;
1200 spdif_priv->sysclk_df[index] = sysclk_df;
1201 spdif_priv->txrate[index] = arate;
1202 } else if (rate[index] / arate == 1) {
1203
1204 sub = (u64)(rate[index] - arate) * 100000;
1205 do_div(sub, rate[index]);
1206 if (sub >= savesub)
1207 continue;
1208 savesub = sub;
1209 spdif_priv->txclk_df[index] = txclk_df;
1210 spdif_priv->sysclk_df[index] = sysclk_df;
1211 spdif_priv->txrate[index] = arate;
1212 }
1213 }
1214 }
1215
1216out:
1217 return savesub;
1218}
1219
1220static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv,
1221 enum spdif_txrate index)
1222{
1223 static const u32 rate[] = { 32000, 44100, 48000, 88200, 96000, 176400,
1224 192000, };
1225 struct platform_device *pdev = spdif_priv->pdev;
1226 struct device *dev = &pdev->dev;
1227 u64 savesub = 100000, ret;
1228 struct clk *clk;
1229 char tmp[16];
1230 int i;
1231
1232 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
1233 sprintf(tmp, "rxtx%d", i);
1234 clk = devm_clk_get(dev, tmp);
1235 if (IS_ERR(clk)) {
1236 dev_err(dev, "no rxtx%d clock in devicetree\n", i);
1237 return PTR_ERR(clk);
1238 }
1239 if (!clk_get_rate(clk))
1240 continue;
1241
1242 ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index,
1243 fsl_spdif_can_set_clk_rate(spdif_priv, i));
1244 if (savesub == ret)
1245 continue;
1246
1247 savesub = ret;
1248 spdif_priv->txclk[index] = clk;
1249 spdif_priv->txclk_src[index] = i;
1250
1251
1252 if (savesub < 100)
1253 break;
1254 }
1255
1256 dev_dbg(dev, "use rxtx%d as tx clock source for %dHz sample rate\n",
1257 spdif_priv->txclk_src[index], rate[index]);
1258 dev_dbg(dev, "use txclk df %d for %dHz sample rate\n",
1259 spdif_priv->txclk_df[index], rate[index]);
1260 if (clk_is_match(spdif_priv->txclk[index], spdif_priv->sysclk))
1261 dev_dbg(dev, "use sysclk df %d for %dHz sample rate\n",
1262 spdif_priv->sysclk_df[index], rate[index]);
1263 dev_dbg(dev, "the best rate for %dHz sample rate is %dHz\n",
1264 rate[index], spdif_priv->txrate[index]);
1265
1266 return 0;
1267}
1268
1269static int fsl_spdif_probe(struct platform_device *pdev)
1270{
1271 struct fsl_spdif_priv *spdif_priv;
1272 struct spdif_mixer_control *ctrl;
1273 struct resource *res;
1274 void __iomem *regs;
1275 int irq, ret, i;
1276
1277 spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL);
1278 if (!spdif_priv)
1279 return -ENOMEM;
1280
1281 spdif_priv->pdev = pdev;
1282
1283 spdif_priv->soc = of_device_get_match_data(&pdev->dev);
1284
1285
1286 memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai));
1287 spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev);
1288 spdif_priv->cpu_dai_drv.playback.formats =
1289 spdif_priv->soc->tx_formats;
1290
1291
1292 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1293 regs = devm_ioremap_resource(&pdev->dev, res);
1294 if (IS_ERR(regs))
1295 return PTR_ERR(regs);
1296
1297 spdif_priv->regmap = devm_regmap_init_mmio(&pdev->dev, regs, &fsl_spdif_regmap_config);
1298 if (IS_ERR(spdif_priv->regmap)) {
1299 dev_err(&pdev->dev, "regmap init failed\n");
1300 return PTR_ERR(spdif_priv->regmap);
1301 }
1302
1303 for (i = 0; i < spdif_priv->soc->interrupts; i++) {
1304 irq = platform_get_irq(pdev, i);
1305 if (irq < 0) {
1306 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
1307 return irq;
1308 }
1309
1310 ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0,
1311 dev_name(&pdev->dev), spdif_priv);
1312 if (ret) {
1313 dev_err(&pdev->dev, "could not claim irq %u\n", irq);
1314 return ret;
1315 }
1316 }
1317
1318
1319 spdif_priv->sysclk = devm_clk_get(&pdev->dev, "rxtx5");
1320 if (IS_ERR(spdif_priv->sysclk)) {
1321 dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n");
1322 return PTR_ERR(spdif_priv->sysclk);
1323 }
1324
1325
1326 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core");
1327 if (IS_ERR(spdif_priv->coreclk)) {
1328 dev_err(&pdev->dev, "no core clock in devicetree\n");
1329 return PTR_ERR(spdif_priv->coreclk);
1330 }
1331
1332 spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
1333 if (IS_ERR(spdif_priv->spbaclk))
1334 dev_warn(&pdev->dev, "no spba clock in devicetree\n");
1335
1336
1337 spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1");
1338 if (IS_ERR(spdif_priv->rxclk)) {
1339 dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n");
1340 return PTR_ERR(spdif_priv->rxclk);
1341 }
1342 spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC;
1343
1344 for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
1345 ret = fsl_spdif_probe_txclk(spdif_priv, i);
1346 if (ret)
1347 return ret;
1348 }
1349
1350
1351 ctrl = &spdif_priv->fsl_spdif_control;
1352 spin_lock_init(&ctrl->ctl_lock);
1353
1354
1355 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT |
1356 IEC958_AES0_CON_EMPHASIS_5015;
1357 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID;
1358 ctrl->ch_status[2] = 0x00;
1359 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 |
1360 IEC958_AES3_CON_CLOCK_1000PPM;
1361
1362 spdif_priv->dpll_locked = false;
1363
1364 spdif_priv->dma_params_tx.maxburst = spdif_priv->soc->tx_burst;
1365 spdif_priv->dma_params_rx.maxburst = spdif_priv->soc->rx_burst;
1366 spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL;
1367 spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL;
1368
1369
1370 dev_set_drvdata(&pdev->dev, spdif_priv);
1371 pm_runtime_enable(&pdev->dev);
1372 regcache_cache_only(spdif_priv->regmap, true);
1373
1374 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component,
1375 &spdif_priv->cpu_dai_drv, 1);
1376 if (ret) {
1377 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1378 goto err_pm_disable;
1379 }
1380
1381 ret = imx_pcm_dma_init(pdev, IMX_SPDIF_DMABUF_SIZE);
1382 if (ret) {
1383 dev_err_probe(&pdev->dev, ret, "imx_pcm_dma_init failed\n");
1384 goto err_pm_disable;
1385 }
1386
1387 return ret;
1388
1389err_pm_disable:
1390 pm_runtime_disable(&pdev->dev);
1391 return ret;
1392}
1393
1394static int fsl_spdif_remove(struct platform_device *pdev)
1395{
1396 pm_runtime_disable(&pdev->dev);
1397
1398 return 0;
1399}
1400
1401#ifdef CONFIG_PM
1402static int fsl_spdif_runtime_suspend(struct device *dev)
1403{
1404 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
1405 int i;
1406
1407
1408 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SIE, 0xffffff, 0);
1409
1410 regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC,
1411 &spdif_priv->regcache_srpc);
1412 regcache_cache_only(spdif_priv->regmap, true);
1413
1414 clk_disable_unprepare(spdif_priv->rxclk);
1415
1416 for (i = 0; i < SPDIF_TXRATE_MAX; i++)
1417 clk_disable_unprepare(spdif_priv->txclk[i]);
1418
1419 if (!IS_ERR(spdif_priv->spbaclk))
1420 clk_disable_unprepare(spdif_priv->spbaclk);
1421 clk_disable_unprepare(spdif_priv->coreclk);
1422
1423 return 0;
1424}
1425
1426static int fsl_spdif_runtime_resume(struct device *dev)
1427{
1428 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
1429 int ret;
1430 int i;
1431
1432 ret = clk_prepare_enable(spdif_priv->coreclk);
1433 if (ret) {
1434 dev_err(dev, "failed to enable core clock\n");
1435 return ret;
1436 }
1437
1438 if (!IS_ERR(spdif_priv->spbaclk)) {
1439 ret = clk_prepare_enable(spdif_priv->spbaclk);
1440 if (ret) {
1441 dev_err(dev, "failed to enable spba clock\n");
1442 goto disable_core_clk;
1443 }
1444 }
1445
1446 for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
1447 ret = clk_prepare_enable(spdif_priv->txclk[i]);
1448 if (ret)
1449 goto disable_tx_clk;
1450 }
1451
1452 ret = clk_prepare_enable(spdif_priv->rxclk);
1453 if (ret)
1454 goto disable_tx_clk;
1455
1456 regcache_cache_only(spdif_priv->regmap, false);
1457 regcache_mark_dirty(spdif_priv->regmap);
1458
1459 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC,
1460 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
1461 spdif_priv->regcache_srpc);
1462
1463 ret = regcache_sync(spdif_priv->regmap);
1464 if (ret)
1465 goto disable_rx_clk;
1466
1467 return 0;
1468
1469disable_rx_clk:
1470 clk_disable_unprepare(spdif_priv->rxclk);
1471disable_tx_clk:
1472 for (i--; i >= 0; i--)
1473 clk_disable_unprepare(spdif_priv->txclk[i]);
1474 if (!IS_ERR(spdif_priv->spbaclk))
1475 clk_disable_unprepare(spdif_priv->spbaclk);
1476disable_core_clk:
1477 clk_disable_unprepare(spdif_priv->coreclk);
1478
1479 return ret;
1480}
1481#endif
1482
1483static const struct dev_pm_ops fsl_spdif_pm = {
1484 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1485 pm_runtime_force_resume)
1486 SET_RUNTIME_PM_OPS(fsl_spdif_runtime_suspend, fsl_spdif_runtime_resume,
1487 NULL)
1488};
1489
1490static const struct of_device_id fsl_spdif_dt_ids[] = {
1491 { .compatible = "fsl,imx35-spdif", .data = &fsl_spdif_imx35, },
1492 { .compatible = "fsl,vf610-spdif", .data = &fsl_spdif_vf610, },
1493 { .compatible = "fsl,imx6sx-spdif", .data = &fsl_spdif_imx6sx, },
1494 { .compatible = "fsl,imx8qm-spdif", .data = &fsl_spdif_imx8qm, },
1495 {}
1496};
1497MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids);
1498
1499static struct platform_driver fsl_spdif_driver = {
1500 .driver = {
1501 .name = "fsl-spdif-dai",
1502 .of_match_table = fsl_spdif_dt_ids,
1503 .pm = &fsl_spdif_pm,
1504 },
1505 .probe = fsl_spdif_probe,
1506 .remove = fsl_spdif_remove,
1507};
1508
1509module_platform_driver(fsl_spdif_driver);
1510
1511MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1512MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver");
1513MODULE_LICENSE("GPL v2");
1514MODULE_ALIAS("platform:fsl-spdif-dai");
1515
