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8#include <linux/clk.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/of_device.h>
13#include <linux/platform_device.h>
14#include <sound/pcm.h>
15#include <sound/pcm_params.h>
16#include <linux/regmap.h>
17#include <sound/soc.h>
18#include <sound/soc-dai.h>
19#include "lpass-lpaif-reg.h"
20#include "lpass.h"
21
22#define LPASS_CPU_MAX_MI2S_LINES 4
23#define LPASS_CPU_I2S_SD0_MASK BIT(0)
24#define LPASS_CPU_I2S_SD1_MASK BIT(1)
25#define LPASS_CPU_I2S_SD2_MASK BIT(2)
26#define LPASS_CPU_I2S_SD3_MASK BIT(3)
27#define LPASS_CPU_I2S_SD0_1_MASK GENMASK(1, 0)
28#define LPASS_CPU_I2S_SD2_3_MASK GENMASK(3, 2)
29#define LPASS_CPU_I2S_SD0_1_2_MASK GENMASK(2, 0)
30#define LPASS_CPU_I2S_SD0_1_2_3_MASK GENMASK(3, 0)
31
32static int lpass_cpu_init_i2sctl_bitfields(struct device *dev,
33 struct lpaif_i2sctl *i2sctl, struct regmap *map)
34{
35 struct lpass_data *drvdata = dev_get_drvdata(dev);
36 struct lpass_variant *v = drvdata->variant;
37
38 i2sctl->loopback = devm_regmap_field_alloc(dev, map, v->loopback);
39 i2sctl->spken = devm_regmap_field_alloc(dev, map, v->spken);
40 i2sctl->spkmode = devm_regmap_field_alloc(dev, map, v->spkmode);
41 i2sctl->spkmono = devm_regmap_field_alloc(dev, map, v->spkmono);
42 i2sctl->micen = devm_regmap_field_alloc(dev, map, v->micen);
43 i2sctl->micmode = devm_regmap_field_alloc(dev, map, v->micmode);
44 i2sctl->micmono = devm_regmap_field_alloc(dev, map, v->micmono);
45 i2sctl->wssrc = devm_regmap_field_alloc(dev, map, v->wssrc);
46 i2sctl->bitwidth = devm_regmap_field_alloc(dev, map, v->bitwidth);
47
48 if (IS_ERR(i2sctl->loopback) || IS_ERR(i2sctl->spken) ||
49 IS_ERR(i2sctl->spkmode) || IS_ERR(i2sctl->spkmono) ||
50 IS_ERR(i2sctl->micen) || IS_ERR(i2sctl->micmode) ||
51 IS_ERR(i2sctl->micmono) || IS_ERR(i2sctl->wssrc) ||
52 IS_ERR(i2sctl->bitwidth))
53 return -EINVAL;
54
55 return 0;
56}
57
58static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id,
59 unsigned int freq, int dir)
60{
61 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
62 int ret;
63
64 ret = clk_set_rate(drvdata->mi2s_osr_clk[dai->driver->id], freq);
65 if (ret)
66 dev_err(dai->dev, "error setting mi2s osrclk to %u: %d\n",
67 freq, ret);
68
69 return ret;
70}
71
72static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream,
73 struct snd_soc_dai *dai)
74{
75 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
76 int ret;
77
78 ret = clk_prepare_enable(drvdata->mi2s_osr_clk[dai->driver->id]);
79 if (ret) {
80 dev_err(dai->dev, "error in enabling mi2s osr clk: %d\n", ret);
81 return ret;
82 }
83 ret = clk_prepare(drvdata->mi2s_bit_clk[dai->driver->id]);
84 if (ret) {
85 dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
86 clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
87 return ret;
88 }
89 return 0;
90}
91
92static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream,
93 struct snd_soc_dai *dai)
94{
95 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
96 struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
97 unsigned int id = dai->driver->id;
98
99 clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
100
101
102
103
104
105 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
106 regmap_fields_write(i2sctl->spken, id, LPAIF_I2SCTL_SPKEN_DISABLE);
107 else
108 regmap_fields_write(i2sctl->micen, id, LPAIF_I2SCTL_MICEN_DISABLE);
109
110
111
112
113
114
115 if (drvdata->mi2s_was_prepared[dai->driver->id]) {
116 drvdata->mi2s_was_prepared[dai->driver->id] = false;
117 clk_disable(drvdata->mi2s_bit_clk[dai->driver->id]);
118 }
119
120 clk_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]);
121}
122
123static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream,
124 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
125{
126 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
127 struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
128 unsigned int id = dai->driver->id;
129 snd_pcm_format_t format = params_format(params);
130 unsigned int channels = params_channels(params);
131 unsigned int rate = params_rate(params);
132 unsigned int mode;
133 unsigned int regval;
134 int bitwidth, ret;
135
136 bitwidth = snd_pcm_format_width(format);
137 if (bitwidth < 0) {
138 dev_err(dai->dev, "invalid bit width given: %d\n", bitwidth);
139 return bitwidth;
140 }
141
142 ret = regmap_fields_write(i2sctl->loopback, id,
143 LPAIF_I2SCTL_LOOPBACK_DISABLE);
144 if (ret) {
145 dev_err(dai->dev, "error updating loopback field: %d\n", ret);
146 return ret;
147 }
148
149 ret = regmap_fields_write(i2sctl->wssrc, id,
150 LPAIF_I2SCTL_WSSRC_INTERNAL);
151 if (ret) {
152 dev_err(dai->dev, "error updating wssrc field: %d\n", ret);
153 return ret;
154 }
155
156 switch (bitwidth) {
157 case 16:
158 regval = LPAIF_I2SCTL_BITWIDTH_16;
159 break;
160 case 24:
161 regval = LPAIF_I2SCTL_BITWIDTH_24;
162 break;
163 case 32:
164 regval = LPAIF_I2SCTL_BITWIDTH_32;
165 break;
166 default:
167 dev_err(dai->dev, "invalid bitwidth given: %d\n", bitwidth);
168 return -EINVAL;
169 }
170
171 ret = regmap_fields_write(i2sctl->bitwidth, id, regval);
172 if (ret) {
173 dev_err(dai->dev, "error updating bitwidth field: %d\n", ret);
174 return ret;
175 }
176
177 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
178 mode = drvdata->mi2s_playback_sd_mode[id];
179 else
180 mode = drvdata->mi2s_capture_sd_mode[id];
181
182 if (!mode) {
183 dev_err(dai->dev, "no line is assigned\n");
184 return -EINVAL;
185 }
186
187 switch (channels) {
188 case 1:
189 case 2:
190 switch (mode) {
191 case LPAIF_I2SCTL_MODE_QUAD01:
192 case LPAIF_I2SCTL_MODE_6CH:
193 case LPAIF_I2SCTL_MODE_8CH:
194 mode = LPAIF_I2SCTL_MODE_SD0;
195 break;
196 case LPAIF_I2SCTL_MODE_QUAD23:
197 mode = LPAIF_I2SCTL_MODE_SD2;
198 break;
199 }
200
201 break;
202 case 4:
203 if (mode < LPAIF_I2SCTL_MODE_QUAD01) {
204 dev_err(dai->dev, "cannot configure 4 channels with mode %d\n",
205 mode);
206 return -EINVAL;
207 }
208
209 switch (mode) {
210 case LPAIF_I2SCTL_MODE_6CH:
211 case LPAIF_I2SCTL_MODE_8CH:
212 mode = LPAIF_I2SCTL_MODE_QUAD01;
213 break;
214 }
215 break;
216 case 6:
217 if (mode < LPAIF_I2SCTL_MODE_6CH) {
218 dev_err(dai->dev, "cannot configure 6 channels with mode %d\n",
219 mode);
220 return -EINVAL;
221 }
222
223 switch (mode) {
224 case LPAIF_I2SCTL_MODE_8CH:
225 mode = LPAIF_I2SCTL_MODE_6CH;
226 break;
227 }
228 break;
229 case 8:
230 if (mode < LPAIF_I2SCTL_MODE_8CH) {
231 dev_err(dai->dev, "cannot configure 8 channels with mode %d\n",
232 mode);
233 return -EINVAL;
234 }
235 break;
236 default:
237 dev_err(dai->dev, "invalid channels given: %u\n", channels);
238 return -EINVAL;
239 }
240
241 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
242 ret = regmap_fields_write(i2sctl->spkmode, id,
243 LPAIF_I2SCTL_SPKMODE(mode));
244 if (ret) {
245 dev_err(dai->dev, "error writing to i2sctl spkr mode: %d\n",
246 ret);
247 return ret;
248 }
249 if (channels >= 2)
250 ret = regmap_fields_write(i2sctl->spkmono, id,
251 LPAIF_I2SCTL_SPKMONO_STEREO);
252 else
253 ret = regmap_fields_write(i2sctl->spkmono, id,
254 LPAIF_I2SCTL_SPKMONO_MONO);
255 } else {
256 ret = regmap_fields_write(i2sctl->micmode, id,
257 LPAIF_I2SCTL_MICMODE(mode));
258 if (ret) {
259 dev_err(dai->dev, "error writing to i2sctl mic mode: %d\n",
260 ret);
261 return ret;
262 }
263 if (channels >= 2)
264 ret = regmap_fields_write(i2sctl->micmono, id,
265 LPAIF_I2SCTL_MICMONO_STEREO);
266 else
267 ret = regmap_fields_write(i2sctl->micmono, id,
268 LPAIF_I2SCTL_MICMONO_MONO);
269 }
270
271 if (ret) {
272 dev_err(dai->dev, "error writing to i2sctl channels mode: %d\n",
273 ret);
274 return ret;
275 }
276
277 ret = clk_set_rate(drvdata->mi2s_bit_clk[id],
278 rate * bitwidth * 2);
279 if (ret) {
280 dev_err(dai->dev, "error setting mi2s bitclk to %u: %d\n",
281 rate * bitwidth * 2, ret);
282 return ret;
283 }
284
285 return 0;
286}
287
288static int lpass_cpu_daiops_trigger(struct snd_pcm_substream *substream,
289 int cmd, struct snd_soc_dai *dai)
290{
291 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
292 struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
293 unsigned int id = dai->driver->id;
294 int ret = -EINVAL;
295
296 switch (cmd) {
297 case SNDRV_PCM_TRIGGER_START:
298 case SNDRV_PCM_TRIGGER_RESUME:
299 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
300
301
302
303
304
305
306
307
308
309
310
311
312 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
313 ret = regmap_fields_write(i2sctl->spken, id,
314 LPAIF_I2SCTL_SPKEN_ENABLE);
315 } else {
316 ret = regmap_fields_write(i2sctl->micen, id,
317 LPAIF_I2SCTL_MICEN_ENABLE);
318 }
319 if (ret)
320 dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
321 ret);
322
323 ret = clk_enable(drvdata->mi2s_bit_clk[id]);
324 if (ret) {
325 dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
326 clk_disable(drvdata->mi2s_osr_clk[id]);
327 return ret;
328 }
329 break;
330 case SNDRV_PCM_TRIGGER_STOP:
331 case SNDRV_PCM_TRIGGER_SUSPEND:
332 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
333
334
335
336
337 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
338 ret = regmap_fields_write(i2sctl->spken, id,
339 LPAIF_I2SCTL_SPKEN_DISABLE);
340 } else {
341 ret = regmap_fields_write(i2sctl->micen, id,
342 LPAIF_I2SCTL_MICEN_DISABLE);
343 }
344 if (ret)
345 dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
346 ret);
347
348 clk_disable(drvdata->mi2s_bit_clk[dai->driver->id]);
349
350 break;
351 }
352
353 return ret;
354}
355
356static int lpass_cpu_daiops_prepare(struct snd_pcm_substream *substream,
357 struct snd_soc_dai *dai)
358{
359 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
360 struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
361 unsigned int id = dai->driver->id;
362 int ret;
363
364
365
366
367
368
369
370 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
371 ret = regmap_fields_write(i2sctl->spken, id, LPAIF_I2SCTL_SPKEN_ENABLE);
372 else
373 ret = regmap_fields_write(i2sctl->micen, id, LPAIF_I2SCTL_MICEN_ENABLE);
374
375 if (ret) {
376 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);
377 return ret;
378 }
379
380
381
382
383
384
385 if (!drvdata->mi2s_was_prepared[dai->driver->id]) {
386 ret = clk_enable(drvdata->mi2s_bit_clk[id]);
387 if (ret) {
388 dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
389 return ret;
390 }
391 drvdata->mi2s_was_prepared[dai->driver->id] = true;
392 }
393 return 0;
394}
395
396const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops = {
397 .set_sysclk = lpass_cpu_daiops_set_sysclk,
398 .startup = lpass_cpu_daiops_startup,
399 .shutdown = lpass_cpu_daiops_shutdown,
400 .hw_params = lpass_cpu_daiops_hw_params,
401 .trigger = lpass_cpu_daiops_trigger,
402 .prepare = lpass_cpu_daiops_prepare,
403};
404EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_ops);
405
406int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai)
407{
408 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
409 int ret;
410
411
412 ret = regmap_write(drvdata->lpaif_map,
413 LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id), 0);
414 if (ret)
415 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);
416
417 return ret;
418}
419EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_probe);
420
421static int asoc_qcom_of_xlate_dai_name(struct snd_soc_component *component,
422 const struct of_phandle_args *args,
423 const char **dai_name)
424{
425 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
426 struct lpass_variant *variant = drvdata->variant;
427 int id = args->args[0];
428 int ret = -EINVAL;
429 int i;
430
431 for (i = 0; i < variant->num_dai; i++) {
432 if (variant->dai_driver[i].id == id) {
433 *dai_name = variant->dai_driver[i].name;
434 ret = 0;
435 break;
436 }
437 }
438
439 return ret;
440}
441
442static const struct snd_soc_component_driver lpass_cpu_comp_driver = {
443 .name = "lpass-cpu",
444 .of_xlate_dai_name = asoc_qcom_of_xlate_dai_name,
445};
446
447static bool lpass_cpu_regmap_writeable(struct device *dev, unsigned int reg)
448{
449 struct lpass_data *drvdata = dev_get_drvdata(dev);
450 struct lpass_variant *v = drvdata->variant;
451 int i;
452
453 for (i = 0; i < v->i2s_ports; ++i)
454 if (reg == LPAIF_I2SCTL_REG(v, i))
455 return true;
456
457 for (i = 0; i < v->irq_ports; ++i) {
458 if (reg == LPAIF_IRQEN_REG(v, i))
459 return true;
460 if (reg == LPAIF_IRQCLEAR_REG(v, i))
461 return true;
462 }
463
464 for (i = 0; i < v->rdma_channels; ++i) {
465 if (reg == LPAIF_RDMACTL_REG(v, i))
466 return true;
467 if (reg == LPAIF_RDMABASE_REG(v, i))
468 return true;
469 if (reg == LPAIF_RDMABUFF_REG(v, i))
470 return true;
471 if (reg == LPAIF_RDMAPER_REG(v, i))
472 return true;
473 }
474
475 for (i = 0; i < v->wrdma_channels; ++i) {
476 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
477 return true;
478 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
479 return true;
480 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
481 return true;
482 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
483 return true;
484 }
485
486 return false;
487}
488
489static bool lpass_cpu_regmap_readable(struct device *dev, unsigned int reg)
490{
491 struct lpass_data *drvdata = dev_get_drvdata(dev);
492 struct lpass_variant *v = drvdata->variant;
493 int i;
494
495 for (i = 0; i < v->i2s_ports; ++i)
496 if (reg == LPAIF_I2SCTL_REG(v, i))
497 return true;
498
499 for (i = 0; i < v->irq_ports; ++i) {
500 if (reg == LPAIF_IRQEN_REG(v, i))
501 return true;
502 if (reg == LPAIF_IRQSTAT_REG(v, i))
503 return true;
504 }
505
506 for (i = 0; i < v->rdma_channels; ++i) {
507 if (reg == LPAIF_RDMACTL_REG(v, i))
508 return true;
509 if (reg == LPAIF_RDMABASE_REG(v, i))
510 return true;
511 if (reg == LPAIF_RDMABUFF_REG(v, i))
512 return true;
513 if (reg == LPAIF_RDMACURR_REG(v, i))
514 return true;
515 if (reg == LPAIF_RDMAPER_REG(v, i))
516 return true;
517 }
518
519 for (i = 0; i < v->wrdma_channels; ++i) {
520 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
521 return true;
522 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
523 return true;
524 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
525 return true;
526 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
527 return true;
528 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
529 return true;
530 }
531
532 return false;
533}
534
535static bool lpass_cpu_regmap_volatile(struct device *dev, unsigned int reg)
536{
537 struct lpass_data *drvdata = dev_get_drvdata(dev);
538 struct lpass_variant *v = drvdata->variant;
539 int i;
540
541 for (i = 0; i < v->irq_ports; ++i)
542 if (reg == LPAIF_IRQSTAT_REG(v, i))
543 return true;
544
545 for (i = 0; i < v->rdma_channels; ++i)
546 if (reg == LPAIF_RDMACURR_REG(v, i))
547 return true;
548
549 for (i = 0; i < v->wrdma_channels; ++i)
550 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
551 return true;
552
553 return false;
554}
555
556static struct regmap_config lpass_cpu_regmap_config = {
557 .name = "lpass_cpu",
558 .reg_bits = 32,
559 .reg_stride = 4,
560 .val_bits = 32,
561 .writeable_reg = lpass_cpu_regmap_writeable,
562 .readable_reg = lpass_cpu_regmap_readable,
563 .volatile_reg = lpass_cpu_regmap_volatile,
564 .cache_type = REGCACHE_FLAT,
565};
566
567static int lpass_hdmi_init_bitfields(struct device *dev, struct regmap *map)
568{
569 struct lpass_data *drvdata = dev_get_drvdata(dev);
570 struct lpass_variant *v = drvdata->variant;
571 unsigned int i;
572 struct lpass_hdmi_tx_ctl *tx_ctl;
573 struct regmap_field *legacy_en;
574 struct lpass_vbit_ctrl *vbit_ctl;
575 struct regmap_field *tx_parity;
576 struct lpass_dp_metadata_ctl *meta_ctl;
577 struct lpass_sstream_ctl *sstream_ctl;
578 struct regmap_field *ch_msb;
579 struct regmap_field *ch_lsb;
580 struct lpass_hdmitx_dmactl *tx_dmactl;
581 int rval;
582
583 tx_ctl = devm_kzalloc(dev, sizeof(*tx_ctl), GFP_KERNEL);
584 if (!tx_ctl)
585 return -ENOMEM;
586
587 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->soft_reset, tx_ctl->soft_reset);
588 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->force_reset, tx_ctl->force_reset);
589 drvdata->tx_ctl = tx_ctl;
590
591 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->legacy_en, legacy_en);
592 drvdata->hdmitx_legacy_en = legacy_en;
593
594 vbit_ctl = devm_kzalloc(dev, sizeof(*vbit_ctl), GFP_KERNEL);
595 if (!vbit_ctl)
596 return -ENOMEM;
597
598 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->replace_vbit, vbit_ctl->replace_vbit);
599 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->vbit_stream, vbit_ctl->vbit_stream);
600 drvdata->vbit_ctl = vbit_ctl;
601
602
603 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->calc_en, tx_parity);
604 drvdata->hdmitx_parity_calc_en = tx_parity;
605
606 meta_ctl = devm_kzalloc(dev, sizeof(*meta_ctl), GFP_KERNEL);
607 if (!meta_ctl)
608 return -ENOMEM;
609
610 rval = devm_regmap_field_bulk_alloc(dev, map, &meta_ctl->mute, &v->mute, 7);
611 if (rval)
612 return rval;
613 drvdata->meta_ctl = meta_ctl;
614
615 sstream_ctl = devm_kzalloc(dev, sizeof(*sstream_ctl), GFP_KERNEL);
616 if (!sstream_ctl)
617 return -ENOMEM;
618
619 rval = devm_regmap_field_bulk_alloc(dev, map, &sstream_ctl->sstream_en, &v->sstream_en, 9);
620 if (rval)
621 return rval;
622
623 drvdata->sstream_ctl = sstream_ctl;
624
625 for (i = 0; i < LPASS_MAX_HDMI_DMA_CHANNELS; i++) {
626 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->msb_bits, ch_msb);
627 drvdata->hdmitx_ch_msb[i] = ch_msb;
628
629 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->lsb_bits, ch_lsb);
630 drvdata->hdmitx_ch_lsb[i] = ch_lsb;
631
632 tx_dmactl = devm_kzalloc(dev, sizeof(*tx_dmactl), GFP_KERNEL);
633 if (!tx_dmactl)
634 return -ENOMEM;
635
636 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_chs, tx_dmactl->use_hw_chs);
637 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_usr, tx_dmactl->use_hw_usr);
638 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_chs_sel, tx_dmactl->hw_chs_sel);
639 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_usr_sel, tx_dmactl->hw_usr_sel);
640 drvdata->hdmi_tx_dmactl[i] = tx_dmactl;
641 }
642 return 0;
643}
644
645static bool lpass_hdmi_regmap_writeable(struct device *dev, unsigned int reg)
646{
647 struct lpass_data *drvdata = dev_get_drvdata(dev);
648 struct lpass_variant *v = drvdata->variant;
649 int i;
650
651 if (reg == LPASS_HDMI_TX_CTL_ADDR(v))
652 return true;
653 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
654 return true;
655 if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v))
656 return true;
657 if (reg == LPASS_HDMI_TX_PARITY_ADDR(v))
658 return true;
659 if (reg == LPASS_HDMI_TX_DP_ADDR(v))
660 return true;
661 if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v))
662 return true;
663 if (reg == LPASS_HDMITX_APP_IRQEN_REG(v))
664 return true;
665 if (reg == LPASS_HDMITX_APP_IRQCLEAR_REG(v))
666 return true;
667
668 for (i = 0; i < v->hdmi_rdma_channels; i++) {
669 if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i))
670 return true;
671 if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i))
672 return true;
673 if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i))
674 return true;
675 }
676
677 for (i = 0; i < v->hdmi_rdma_channels; ++i) {
678 if (reg == LPAIF_HDMI_RDMACTL_REG(v, i))
679 return true;
680 if (reg == LPAIF_HDMI_RDMABASE_REG(v, i))
681 return true;
682 if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i))
683 return true;
684 if (reg == LPAIF_HDMI_RDMAPER_REG(v, i))
685 return true;
686 }
687 return false;
688}
689
690static bool lpass_hdmi_regmap_readable(struct device *dev, unsigned int reg)
691{
692 struct lpass_data *drvdata = dev_get_drvdata(dev);
693 struct lpass_variant *v = drvdata->variant;
694 int i;
695
696 if (reg == LPASS_HDMI_TX_CTL_ADDR(v))
697 return true;
698 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
699 return true;
700 if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v))
701 return true;
702
703 for (i = 0; i < v->hdmi_rdma_channels; i++) {
704 if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i))
705 return true;
706 if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i))
707 return true;
708 if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i))
709 return true;
710 }
711
712 if (reg == LPASS_HDMI_TX_PARITY_ADDR(v))
713 return true;
714 if (reg == LPASS_HDMI_TX_DP_ADDR(v))
715 return true;
716 if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v))
717 return true;
718 if (reg == LPASS_HDMITX_APP_IRQEN_REG(v))
719 return true;
720 if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v))
721 return true;
722
723 for (i = 0; i < v->hdmi_rdma_channels; ++i) {
724 if (reg == LPAIF_HDMI_RDMACTL_REG(v, i))
725 return true;
726 if (reg == LPAIF_HDMI_RDMABASE_REG(v, i))
727 return true;
728 if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i))
729 return true;
730 if (reg == LPAIF_HDMI_RDMAPER_REG(v, i))
731 return true;
732 if (reg == LPAIF_HDMI_RDMACURR_REG(v, i))
733 return true;
734 }
735
736 return false;
737}
738
739static bool lpass_hdmi_regmap_volatile(struct device *dev, unsigned int reg)
740{
741 struct lpass_data *drvdata = dev_get_drvdata(dev);
742 struct lpass_variant *v = drvdata->variant;
743 int i;
744
745 if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v))
746 return true;
747 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
748 return true;
749
750 for (i = 0; i < v->hdmi_rdma_channels; ++i) {
751 if (reg == LPAIF_HDMI_RDMACURR_REG(v, i))
752 return true;
753 }
754 return false;
755}
756
757static struct regmap_config lpass_hdmi_regmap_config = {
758 .name = "lpass_hdmi",
759 .reg_bits = 32,
760 .reg_stride = 4,
761 .val_bits = 32,
762 .writeable_reg = lpass_hdmi_regmap_writeable,
763 .readable_reg = lpass_hdmi_regmap_readable,
764 .volatile_reg = lpass_hdmi_regmap_volatile,
765 .cache_type = REGCACHE_FLAT,
766};
767
768static unsigned int of_lpass_cpu_parse_sd_lines(struct device *dev,
769 struct device_node *node,
770 const char *name)
771{
772 unsigned int lines[LPASS_CPU_MAX_MI2S_LINES];
773 unsigned int sd_line_mask = 0;
774 int num_lines, i;
775
776 num_lines = of_property_read_variable_u32_array(node, name, lines, 0,
777 LPASS_CPU_MAX_MI2S_LINES);
778 if (num_lines < 0)
779 return LPAIF_I2SCTL_MODE_NONE;
780
781 for (i = 0; i < num_lines; i++)
782 sd_line_mask |= BIT(lines[i]);
783
784 switch (sd_line_mask) {
785 case LPASS_CPU_I2S_SD0_MASK:
786 return LPAIF_I2SCTL_MODE_SD0;
787 case LPASS_CPU_I2S_SD1_MASK:
788 return LPAIF_I2SCTL_MODE_SD1;
789 case LPASS_CPU_I2S_SD2_MASK:
790 return LPAIF_I2SCTL_MODE_SD2;
791 case LPASS_CPU_I2S_SD3_MASK:
792 return LPAIF_I2SCTL_MODE_SD3;
793 case LPASS_CPU_I2S_SD0_1_MASK:
794 return LPAIF_I2SCTL_MODE_QUAD01;
795 case LPASS_CPU_I2S_SD2_3_MASK:
796 return LPAIF_I2SCTL_MODE_QUAD23;
797 case LPASS_CPU_I2S_SD0_1_2_MASK:
798 return LPAIF_I2SCTL_MODE_6CH;
799 case LPASS_CPU_I2S_SD0_1_2_3_MASK:
800 return LPAIF_I2SCTL_MODE_8CH;
801 default:
802 dev_err(dev, "Unsupported SD line mask: %#x\n", sd_line_mask);
803 return LPAIF_I2SCTL_MODE_NONE;
804 }
805}
806
807static void of_lpass_cpu_parse_dai_data(struct device *dev,
808 struct lpass_data *data)
809{
810 struct device_node *node;
811 int ret, id;
812
813
814 for (id = 0; id < data->variant->num_dai; id++) {
815 data->mi2s_playback_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH;
816 data->mi2s_capture_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH;
817 }
818
819 for_each_child_of_node(dev->of_node, node) {
820 ret = of_property_read_u32(node, "reg", &id);
821 if (ret || id < 0) {
822 dev_err(dev, "valid dai id not found: %d\n", ret);
823 continue;
824 }
825 if (id == LPASS_DP_RX) {
826 data->hdmi_port_enable = 1;
827 } else {
828 data->mi2s_playback_sd_mode[id] =
829 of_lpass_cpu_parse_sd_lines(dev, node,
830 "qcom,playback-sd-lines");
831 data->mi2s_capture_sd_mode[id] =
832 of_lpass_cpu_parse_sd_lines(dev, node,
833 "qcom,capture-sd-lines");
834 }
835 }
836}
837
838int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev)
839{
840 struct lpass_data *drvdata;
841 struct device_node *dsp_of_node;
842 struct resource *res;
843 struct lpass_variant *variant;
844 struct device *dev = &pdev->dev;
845 const struct of_device_id *match;
846 int ret, i, dai_id;
847
848 dsp_of_node = of_parse_phandle(pdev->dev.of_node, "qcom,adsp", 0);
849 if (dsp_of_node) {
850 dev_err(dev, "DSP exists and holds audio resources\n");
851 return -EBUSY;
852 }
853
854 drvdata = devm_kzalloc(dev, sizeof(struct lpass_data), GFP_KERNEL);
855 if (!drvdata)
856 return -ENOMEM;
857 platform_set_drvdata(pdev, drvdata);
858
859 match = of_match_device(dev->driver->of_match_table, dev);
860 if (!match || !match->data)
861 return -EINVAL;
862
863 drvdata->variant = (struct lpass_variant *)match->data;
864 variant = drvdata->variant;
865
866 of_lpass_cpu_parse_dai_data(dev, drvdata);
867
868 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-lpaif");
869
870 drvdata->lpaif = devm_ioremap_resource(dev, res);
871 if (IS_ERR(drvdata->lpaif))
872 return PTR_ERR(drvdata->lpaif);
873
874 lpass_cpu_regmap_config.max_register = LPAIF_WRDMAPER_REG(variant,
875 variant->wrdma_channels +
876 variant->wrdma_channel_start);
877
878 drvdata->lpaif_map = devm_regmap_init_mmio(dev, drvdata->lpaif,
879 &lpass_cpu_regmap_config);
880 if (IS_ERR(drvdata->lpaif_map)) {
881 dev_err(dev, "error initializing regmap: %ld\n",
882 PTR_ERR(drvdata->lpaif_map));
883 return PTR_ERR(drvdata->lpaif_map);
884 }
885
886 if (drvdata->hdmi_port_enable) {
887 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-hdmiif");
888
889 drvdata->hdmiif = devm_ioremap_resource(dev, res);
890 if (IS_ERR(drvdata->hdmiif))
891 return PTR_ERR(drvdata->hdmiif);
892
893 lpass_hdmi_regmap_config.max_register = LPAIF_HDMI_RDMAPER_REG(variant,
894 variant->hdmi_rdma_channels - 1);
895 drvdata->hdmiif_map = devm_regmap_init_mmio(dev, drvdata->hdmiif,
896 &lpass_hdmi_regmap_config);
897 if (IS_ERR(drvdata->hdmiif_map)) {
898 dev_err(dev, "error initializing regmap: %ld\n",
899 PTR_ERR(drvdata->hdmiif_map));
900 return PTR_ERR(drvdata->hdmiif_map);
901 }
902 }
903
904 if (variant->init) {
905 ret = variant->init(pdev);
906 if (ret) {
907 dev_err(dev, "error initializing variant: %d\n", ret);
908 return ret;
909 }
910 }
911
912 for (i = 0; i < variant->num_dai; i++) {
913 dai_id = variant->dai_driver[i].id;
914 if (dai_id == LPASS_DP_RX)
915 continue;
916
917 drvdata->mi2s_osr_clk[dai_id] = devm_clk_get_optional(dev,
918 variant->dai_osr_clk_names[i]);
919 drvdata->mi2s_bit_clk[dai_id] = devm_clk_get(dev,
920 variant->dai_bit_clk_names[i]);
921 if (IS_ERR(drvdata->mi2s_bit_clk[dai_id])) {
922 dev_err(dev,
923 "error getting %s: %ld\n",
924 variant->dai_bit_clk_names[i],
925 PTR_ERR(drvdata->mi2s_bit_clk[dai_id]));
926 return PTR_ERR(drvdata->mi2s_bit_clk[dai_id]);
927 }
928 }
929
930
931 drvdata->i2sctl = devm_kzalloc(&pdev->dev, sizeof(struct lpaif_i2sctl),
932 GFP_KERNEL);
933
934
935 ret = lpass_cpu_init_i2sctl_bitfields(dev, drvdata->i2sctl,
936 drvdata->lpaif_map);
937 if (ret) {
938 dev_err(dev, "error init i2sctl field: %d\n", ret);
939 return ret;
940 }
941
942 if (drvdata->hdmi_port_enable) {
943 ret = lpass_hdmi_init_bitfields(dev, drvdata->hdmiif_map);
944 if (ret) {
945 dev_err(dev, "%s error hdmi init failed\n", __func__);
946 return ret;
947 }
948 }
949 ret = devm_snd_soc_register_component(dev,
950 &lpass_cpu_comp_driver,
951 variant->dai_driver,
952 variant->num_dai);
953 if (ret) {
954 dev_err(dev, "error registering cpu driver: %d\n", ret);
955 goto err;
956 }
957
958 ret = asoc_qcom_lpass_platform_register(pdev);
959 if (ret) {
960 dev_err(dev, "error registering platform driver: %d\n", ret);
961 goto err;
962 }
963
964err:
965 return ret;
966}
967EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_probe);
968
969int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev)
970{
971 struct lpass_data *drvdata = platform_get_drvdata(pdev);
972
973 if (drvdata->variant->exit)
974 drvdata->variant->exit(pdev);
975
976
977 return 0;
978}
979EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_remove);
980
981void asoc_qcom_lpass_cpu_platform_shutdown(struct platform_device *pdev)
982{
983 struct lpass_data *drvdata = platform_get_drvdata(pdev);
984
985 if (drvdata->variant->exit)
986 drvdata->variant->exit(pdev);
987
988}
989EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_shutdown);
990
991MODULE_DESCRIPTION("QTi LPASS CPU Driver");
992MODULE_LICENSE("GPL v2");
993
