linux/drivers/crypto/mxs-dcp.c
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   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Freescale i.MX23/i.MX28 Data Co-Processor driver
   4 *
   5 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
   6 */
   7
   8#include <linux/dma-mapping.h>
   9#include <linux/interrupt.h>
  10#include <linux/io.h>
  11#include <linux/kernel.h>
  12#include <linux/kthread.h>
  13#include <linux/module.h>
  14#include <linux/of.h>
  15#include <linux/platform_device.h>
  16#include <linux/stmp_device.h>
  17#include <linux/clk.h>
  18
  19#include <crypto/aes.h>
  20#include <crypto/sha1.h>
  21#include <crypto/sha2.h>
  22#include <crypto/internal/hash.h>
  23#include <crypto/internal/skcipher.h>
  24#include <crypto/scatterwalk.h>
  25
  26#define DCP_MAX_CHANS   4
  27#define DCP_BUF_SZ      PAGE_SIZE
  28#define DCP_SHA_PAY_SZ  64
  29
  30#define DCP_ALIGNMENT   64
  31
  32/*
  33 * Null hashes to align with hw behavior on imx6sl and ull
  34 * these are flipped for consistency with hw output
  35 */
  36static const uint8_t sha1_null_hash[] =
  37        "\x09\x07\xd8\xaf\x90\x18\x60\x95\xef\xbf"
  38        "\x55\x32\x0d\x4b\x6b\x5e\xee\xa3\x39\xda";
  39
  40static const uint8_t sha256_null_hash[] =
  41        "\x55\xb8\x52\x78\x1b\x99\x95\xa4"
  42        "\x4c\x93\x9b\x64\xe4\x41\xae\x27"
  43        "\x24\xb9\x6f\x99\xc8\xf4\xfb\x9a"
  44        "\x14\x1c\xfc\x98\x42\xc4\xb0\xe3";
  45
  46/* DCP DMA descriptor. */
  47struct dcp_dma_desc {
  48        uint32_t        next_cmd_addr;
  49        uint32_t        control0;
  50        uint32_t        control1;
  51        uint32_t        source;
  52        uint32_t        destination;
  53        uint32_t        size;
  54        uint32_t        payload;
  55        uint32_t        status;
  56};
  57
  58/* Coherent aligned block for bounce buffering. */
  59struct dcp_coherent_block {
  60        uint8_t                 aes_in_buf[DCP_BUF_SZ];
  61        uint8_t                 aes_out_buf[DCP_BUF_SZ];
  62        uint8_t                 sha_in_buf[DCP_BUF_SZ];
  63        uint8_t                 sha_out_buf[DCP_SHA_PAY_SZ];
  64
  65        uint8_t                 aes_key[2 * AES_KEYSIZE_128];
  66
  67        struct dcp_dma_desc     desc[DCP_MAX_CHANS];
  68};
  69
  70struct dcp {
  71        struct device                   *dev;
  72        void __iomem                    *base;
  73
  74        uint32_t                        caps;
  75
  76        struct dcp_coherent_block       *coh;
  77
  78        struct completion               completion[DCP_MAX_CHANS];
  79        spinlock_t                      lock[DCP_MAX_CHANS];
  80        struct task_struct              *thread[DCP_MAX_CHANS];
  81        struct crypto_queue             queue[DCP_MAX_CHANS];
  82        struct clk                      *dcp_clk;
  83};
  84
  85enum dcp_chan {
  86        DCP_CHAN_HASH_SHA       = 0,
  87        DCP_CHAN_CRYPTO         = 2,
  88};
  89
  90struct dcp_async_ctx {
  91        /* Common context */
  92        enum dcp_chan   chan;
  93        uint32_t        fill;
  94
  95        /* SHA Hash-specific context */
  96        struct mutex                    mutex;
  97        uint32_t                        alg;
  98        unsigned int                    hot:1;
  99
 100        /* Crypto-specific context */
 101        struct crypto_skcipher          *fallback;
 102        unsigned int                    key_len;
 103        uint8_t                         key[AES_KEYSIZE_128];
 104};
 105
 106struct dcp_aes_req_ctx {
 107        unsigned int    enc:1;
 108        unsigned int    ecb:1;
 109        struct skcipher_request fallback_req;   // keep at the end
 110};
 111
 112struct dcp_sha_req_ctx {
 113        unsigned int    init:1;
 114        unsigned int    fini:1;
 115};
 116
 117struct dcp_export_state {
 118        struct dcp_sha_req_ctx req_ctx;
 119        struct dcp_async_ctx async_ctx;
 120};
 121
 122/*
 123 * There can even be only one instance of the MXS DCP due to the
 124 * design of Linux Crypto API.
 125 */
 126static struct dcp *global_sdcp;
 127
 128/* DCP register layout. */
 129#define MXS_DCP_CTRL                            0x00
 130#define MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES     (1 << 23)
 131#define MXS_DCP_CTRL_ENABLE_CONTEXT_CACHING     (1 << 22)
 132
 133#define MXS_DCP_STAT                            0x10
 134#define MXS_DCP_STAT_CLR                        0x18
 135#define MXS_DCP_STAT_IRQ_MASK                   0xf
 136
 137#define MXS_DCP_CHANNELCTRL                     0x20
 138#define MXS_DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK 0xff
 139
 140#define MXS_DCP_CAPABILITY1                     0x40
 141#define MXS_DCP_CAPABILITY1_SHA256              (4 << 16)
 142#define MXS_DCP_CAPABILITY1_SHA1                (1 << 16)
 143#define MXS_DCP_CAPABILITY1_AES128              (1 << 0)
 144
 145#define MXS_DCP_CONTEXT                         0x50
 146
 147#define MXS_DCP_CH_N_CMDPTR(n)                  (0x100 + ((n) * 0x40))
 148
 149#define MXS_DCP_CH_N_SEMA(n)                    (0x110 + ((n) * 0x40))
 150
 151#define MXS_DCP_CH_N_STAT(n)                    (0x120 + ((n) * 0x40))
 152#define MXS_DCP_CH_N_STAT_CLR(n)                (0x128 + ((n) * 0x40))
 153
 154/* DMA descriptor bits. */
 155#define MXS_DCP_CONTROL0_HASH_TERM              (1 << 13)
 156#define MXS_DCP_CONTROL0_HASH_INIT              (1 << 12)
 157#define MXS_DCP_CONTROL0_PAYLOAD_KEY            (1 << 11)
 158#define MXS_DCP_CONTROL0_CIPHER_ENCRYPT         (1 << 8)
 159#define MXS_DCP_CONTROL0_CIPHER_INIT            (1 << 9)
 160#define MXS_DCP_CONTROL0_ENABLE_HASH            (1 << 6)
 161#define MXS_DCP_CONTROL0_ENABLE_CIPHER          (1 << 5)
 162#define MXS_DCP_CONTROL0_DECR_SEMAPHORE         (1 << 1)
 163#define MXS_DCP_CONTROL0_INTERRUPT              (1 << 0)
 164
 165#define MXS_DCP_CONTROL1_HASH_SELECT_SHA256     (2 << 16)
 166#define MXS_DCP_CONTROL1_HASH_SELECT_SHA1       (0 << 16)
 167#define MXS_DCP_CONTROL1_CIPHER_MODE_CBC        (1 << 4)
 168#define MXS_DCP_CONTROL1_CIPHER_MODE_ECB        (0 << 4)
 169#define MXS_DCP_CONTROL1_CIPHER_SELECT_AES128   (0 << 0)
 170
 171static int mxs_dcp_start_dma(struct dcp_async_ctx *actx)
 172{
 173        int dma_err;
 174        struct dcp *sdcp = global_sdcp;
 175        const int chan = actx->chan;
 176        uint32_t stat;
 177        unsigned long ret;
 178        struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan];
 179        dma_addr_t desc_phys = dma_map_single(sdcp->dev, desc, sizeof(*desc),
 180                                              DMA_TO_DEVICE);
 181
 182        dma_err = dma_mapping_error(sdcp->dev, desc_phys);
 183        if (dma_err)
 184                return dma_err;
 185
 186        reinit_completion(&sdcp->completion[chan]);
 187
 188        /* Clear status register. */
 189        writel(0xffffffff, sdcp->base + MXS_DCP_CH_N_STAT_CLR(chan));
 190
 191        /* Load the DMA descriptor. */
 192        writel(desc_phys, sdcp->base + MXS_DCP_CH_N_CMDPTR(chan));
 193
 194        /* Increment the semaphore to start the DMA transfer. */
 195        writel(1, sdcp->base + MXS_DCP_CH_N_SEMA(chan));
 196
 197        ret = wait_for_completion_timeout(&sdcp->completion[chan],
 198                                          msecs_to_jiffies(1000));
 199        if (!ret) {
 200                dev_err(sdcp->dev, "Channel %i timeout (DCP_STAT=0x%08x)\n",
 201                        chan, readl(sdcp->base + MXS_DCP_STAT));
 202                return -ETIMEDOUT;
 203        }
 204
 205        stat = readl(sdcp->base + MXS_DCP_CH_N_STAT(chan));
 206        if (stat & 0xff) {
 207                dev_err(sdcp->dev, "Channel %i error (CH_STAT=0x%08x)\n",
 208                        chan, stat);
 209                return -EINVAL;
 210        }
 211
 212        dma_unmap_single(sdcp->dev, desc_phys, sizeof(*desc), DMA_TO_DEVICE);
 213
 214        return 0;
 215}
 216
 217/*
 218 * Encryption (AES128)
 219 */
 220static int mxs_dcp_run_aes(struct dcp_async_ctx *actx,
 221                           struct skcipher_request *req, int init)
 222{
 223        dma_addr_t key_phys, src_phys, dst_phys;
 224        struct dcp *sdcp = global_sdcp;
 225        struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan];
 226        struct dcp_aes_req_ctx *rctx = skcipher_request_ctx(req);
 227        int ret;
 228
 229        key_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_key,
 230                                  2 * AES_KEYSIZE_128, DMA_TO_DEVICE);
 231        ret = dma_mapping_error(sdcp->dev, key_phys);
 232        if (ret)
 233                return ret;
 234
 235        src_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_in_buf,
 236                                  DCP_BUF_SZ, DMA_TO_DEVICE);
 237        ret = dma_mapping_error(sdcp->dev, src_phys);
 238        if (ret)
 239                goto err_src;
 240
 241        dst_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_out_buf,
 242                                  DCP_BUF_SZ, DMA_FROM_DEVICE);
 243        ret = dma_mapping_error(sdcp->dev, dst_phys);
 244        if (ret)
 245                goto err_dst;
 246
 247        if (actx->fill % AES_BLOCK_SIZE) {
 248                dev_err(sdcp->dev, "Invalid block size!\n");
 249                ret = -EINVAL;
 250                goto aes_done_run;
 251        }
 252
 253        /* Fill in the DMA descriptor. */
 254        desc->control0 = MXS_DCP_CONTROL0_DECR_SEMAPHORE |
 255                    MXS_DCP_CONTROL0_INTERRUPT |
 256                    MXS_DCP_CONTROL0_ENABLE_CIPHER;
 257
 258        /* Payload contains the key. */
 259        desc->control0 |= MXS_DCP_CONTROL0_PAYLOAD_KEY;
 260
 261        if (rctx->enc)
 262                desc->control0 |= MXS_DCP_CONTROL0_CIPHER_ENCRYPT;
 263        if (init)
 264                desc->control0 |= MXS_DCP_CONTROL0_CIPHER_INIT;
 265
 266        desc->control1 = MXS_DCP_CONTROL1_CIPHER_SELECT_AES128;
 267
 268        if (rctx->ecb)
 269                desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_ECB;
 270        else
 271                desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_CBC;
 272
 273        desc->next_cmd_addr = 0;
 274        desc->source = src_phys;
 275        desc->destination = dst_phys;
 276        desc->size = actx->fill;
 277        desc->payload = key_phys;
 278        desc->status = 0;
 279
 280        ret = mxs_dcp_start_dma(actx);
 281
 282aes_done_run:
 283        dma_unmap_single(sdcp->dev, dst_phys, DCP_BUF_SZ, DMA_FROM_DEVICE);
 284err_dst:
 285        dma_unmap_single(sdcp->dev, src_phys, DCP_BUF_SZ, DMA_TO_DEVICE);
 286err_src:
 287        dma_unmap_single(sdcp->dev, key_phys, 2 * AES_KEYSIZE_128,
 288                         DMA_TO_DEVICE);
 289
 290        return ret;
 291}
 292
 293static int mxs_dcp_aes_block_crypt(struct crypto_async_request *arq)
 294{
 295        struct dcp *sdcp = global_sdcp;
 296
 297        struct skcipher_request *req = skcipher_request_cast(arq);
 298        struct dcp_async_ctx *actx = crypto_tfm_ctx(arq->tfm);
 299        struct dcp_aes_req_ctx *rctx = skcipher_request_ctx(req);
 300
 301        struct scatterlist *dst = req->dst;
 302        struct scatterlist *src = req->src;
 303        const int nents = sg_nents(req->src);
 304
 305        const int out_off = DCP_BUF_SZ;
 306        uint8_t *in_buf = sdcp->coh->aes_in_buf;
 307        uint8_t *out_buf = sdcp->coh->aes_out_buf;
 308
 309        uint8_t *out_tmp, *src_buf, *dst_buf = NULL;
 310        uint32_t dst_off = 0;
 311        uint32_t last_out_len = 0;
 312
 313        uint8_t *key = sdcp->coh->aes_key;
 314
 315        int ret = 0;
 316        int split = 0;
 317        unsigned int i, len, clen, rem = 0, tlen = 0;
 318        int init = 0;
 319        bool limit_hit = false;
 320
 321        actx->fill = 0;
 322
 323        /* Copy the key from the temporary location. */
 324        memcpy(key, actx->key, actx->key_len);
 325
 326        if (!rctx->ecb) {
 327                /* Copy the CBC IV just past the key. */
 328                memcpy(key + AES_KEYSIZE_128, req->iv, AES_KEYSIZE_128);
 329                /* CBC needs the INIT set. */
 330                init = 1;
 331        } else {
 332                memset(key + AES_KEYSIZE_128, 0, AES_KEYSIZE_128);
 333        }
 334
 335        for_each_sg(req->src, src, nents, i) {
 336                src_buf = sg_virt(src);
 337                len = sg_dma_len(src);
 338                tlen += len;
 339                limit_hit = tlen > req->cryptlen;
 340
 341                if (limit_hit)
 342                        len = req->cryptlen - (tlen - len);
 343
 344                do {
 345                        if (actx->fill + len > out_off)
 346                                clen = out_off - actx->fill;
 347                        else
 348                                clen = len;
 349
 350                        memcpy(in_buf + actx->fill, src_buf, clen);
 351                        len -= clen;
 352                        src_buf += clen;
 353                        actx->fill += clen;
 354
 355                        /*
 356                         * If we filled the buffer or this is the last SG,
 357                         * submit the buffer.
 358                         */
 359                        if (actx->fill == out_off || sg_is_last(src) ||
 360                                limit_hit) {
 361                                ret = mxs_dcp_run_aes(actx, req, init);
 362                                if (ret)
 363                                        return ret;
 364                                init = 0;
 365
 366                                out_tmp = out_buf;
 367                                last_out_len = actx->fill;
 368                                while (dst && actx->fill) {
 369                                        if (!split) {
 370                                                dst_buf = sg_virt(dst);
 371                                                dst_off = 0;
 372                                        }
 373                                        rem = min(sg_dma_len(dst) - dst_off,
 374                                                  actx->fill);
 375
 376                                        memcpy(dst_buf + dst_off, out_tmp, rem);
 377                                        out_tmp += rem;
 378                                        dst_off += rem;
 379                                        actx->fill -= rem;
 380
 381                                        if (dst_off == sg_dma_len(dst)) {
 382                                                dst = sg_next(dst);
 383                                                split = 0;
 384                                        } else {
 385                                                split = 1;
 386                                        }
 387                                }
 388                        }
 389                } while (len);
 390
 391                if (limit_hit)
 392                        break;
 393        }
 394
 395        /* Copy the IV for CBC for chaining */
 396        if (!rctx->ecb) {
 397                if (rctx->enc)
 398                        memcpy(req->iv, out_buf+(last_out_len-AES_BLOCK_SIZE),
 399                                AES_BLOCK_SIZE);
 400                else
 401                        memcpy(req->iv, in_buf+(last_out_len-AES_BLOCK_SIZE),
 402                                AES_BLOCK_SIZE);
 403        }
 404
 405        return ret;
 406}
 407
 408static int dcp_chan_thread_aes(void *data)
 409{
 410        struct dcp *sdcp = global_sdcp;
 411        const int chan = DCP_CHAN_CRYPTO;
 412
 413        struct crypto_async_request *backlog;
 414        struct crypto_async_request *arq;
 415
 416        int ret;
 417
 418        while (!kthread_should_stop()) {
 419                set_current_state(TASK_INTERRUPTIBLE);
 420
 421                spin_lock(&sdcp->lock[chan]);
 422                backlog = crypto_get_backlog(&sdcp->queue[chan]);
 423                arq = crypto_dequeue_request(&sdcp->queue[chan]);
 424                spin_unlock(&sdcp->lock[chan]);
 425
 426                if (!backlog && !arq) {
 427                        schedule();
 428                        continue;
 429                }
 430
 431                set_current_state(TASK_RUNNING);
 432
 433                if (backlog)
 434                        backlog->complete(backlog, -EINPROGRESS);
 435
 436                if (arq) {
 437                        ret = mxs_dcp_aes_block_crypt(arq);
 438                        arq->complete(arq, ret);
 439                }
 440        }
 441
 442        return 0;
 443}
 444
 445static int mxs_dcp_block_fallback(struct skcipher_request *req, int enc)
 446{
 447        struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
 448        struct dcp_aes_req_ctx *rctx = skcipher_request_ctx(req);
 449        struct dcp_async_ctx *ctx = crypto_skcipher_ctx(tfm);
 450        int ret;
 451
 452        skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback);
 453        skcipher_request_set_callback(&rctx->fallback_req, req->base.flags,
 454                                      req->base.complete, req->base.data);
 455        skcipher_request_set_crypt(&rctx->fallback_req, req->src, req->dst,
 456                                   req->cryptlen, req->iv);
 457
 458        if (enc)
 459                ret = crypto_skcipher_encrypt(&rctx->fallback_req);
 460        else
 461                ret = crypto_skcipher_decrypt(&rctx->fallback_req);
 462
 463        return ret;
 464}
 465
 466static int mxs_dcp_aes_enqueue(struct skcipher_request *req, int enc, int ecb)
 467{
 468        struct dcp *sdcp = global_sdcp;
 469        struct crypto_async_request *arq = &req->base;
 470        struct dcp_async_ctx *actx = crypto_tfm_ctx(arq->tfm);
 471        struct dcp_aes_req_ctx *rctx = skcipher_request_ctx(req);
 472        int ret;
 473
 474        if (unlikely(actx->key_len != AES_KEYSIZE_128))
 475                return mxs_dcp_block_fallback(req, enc);
 476
 477        rctx->enc = enc;
 478        rctx->ecb = ecb;
 479        actx->chan = DCP_CHAN_CRYPTO;
 480
 481        spin_lock(&sdcp->lock[actx->chan]);
 482        ret = crypto_enqueue_request(&sdcp->queue[actx->chan], &req->base);
 483        spin_unlock(&sdcp->lock[actx->chan]);
 484
 485        wake_up_process(sdcp->thread[actx->chan]);
 486
 487        return ret;
 488}
 489
 490static int mxs_dcp_aes_ecb_decrypt(struct skcipher_request *req)
 491{
 492        return mxs_dcp_aes_enqueue(req, 0, 1);
 493}
 494
 495static int mxs_dcp_aes_ecb_encrypt(struct skcipher_request *req)
 496{
 497        return mxs_dcp_aes_enqueue(req, 1, 1);
 498}
 499
 500static int mxs_dcp_aes_cbc_decrypt(struct skcipher_request *req)
 501{
 502        return mxs_dcp_aes_enqueue(req, 0, 0);
 503}
 504
 505static int mxs_dcp_aes_cbc_encrypt(struct skcipher_request *req)
 506{
 507        return mxs_dcp_aes_enqueue(req, 1, 0);
 508}
 509
 510static int mxs_dcp_aes_setkey(struct crypto_skcipher *tfm, const u8 *key,
 511                              unsigned int len)
 512{
 513        struct dcp_async_ctx *actx = crypto_skcipher_ctx(tfm);
 514
 515        /*
 516         * AES 128 is supposed by the hardware, store key into temporary
 517         * buffer and exit. We must use the temporary buffer here, since
 518         * there can still be an operation in progress.
 519         */
 520        actx->key_len = len;
 521        if (len == AES_KEYSIZE_128) {
 522                memcpy(actx->key, key, len);
 523                return 0;
 524        }
 525
 526        /*
 527         * If the requested AES key size is not supported by the hardware,
 528         * but is supported by in-kernel software implementation, we use
 529         * software fallback.
 530         */
 531        crypto_skcipher_clear_flags(actx->fallback, CRYPTO_TFM_REQ_MASK);
 532        crypto_skcipher_set_flags(actx->fallback,
 533                                  tfm->base.crt_flags & CRYPTO_TFM_REQ_MASK);
 534        return crypto_skcipher_setkey(actx->fallback, key, len);
 535}
 536
 537static int mxs_dcp_aes_fallback_init_tfm(struct crypto_skcipher *tfm)
 538{
 539        const char *name = crypto_tfm_alg_name(crypto_skcipher_tfm(tfm));
 540        struct dcp_async_ctx *actx = crypto_skcipher_ctx(tfm);
 541        struct crypto_skcipher *blk;
 542
 543        blk = crypto_alloc_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK);
 544        if (IS_ERR(blk))
 545                return PTR_ERR(blk);
 546
 547        actx->fallback = blk;
 548        crypto_skcipher_set_reqsize(tfm, sizeof(struct dcp_aes_req_ctx) +
 549                                         crypto_skcipher_reqsize(blk));
 550        return 0;
 551}
 552
 553static void mxs_dcp_aes_fallback_exit_tfm(struct crypto_skcipher *tfm)
 554{
 555        struct dcp_async_ctx *actx = crypto_skcipher_ctx(tfm);
 556
 557        crypto_free_skcipher(actx->fallback);
 558}
 559
 560/*
 561 * Hashing (SHA1/SHA256)
 562 */
 563static int mxs_dcp_run_sha(struct ahash_request *req)
 564{
 565        struct dcp *sdcp = global_sdcp;
 566        int ret;
 567
 568        struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 569        struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
 570        struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
 571        struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan];
 572
 573        dma_addr_t digest_phys = 0;
 574        dma_addr_t buf_phys = dma_map_single(sdcp->dev, sdcp->coh->sha_in_buf,
 575                                             DCP_BUF_SZ, DMA_TO_DEVICE);
 576
 577        ret = dma_mapping_error(sdcp->dev, buf_phys);
 578        if (ret)
 579                return ret;
 580
 581        /* Fill in the DMA descriptor. */
 582        desc->control0 = MXS_DCP_CONTROL0_DECR_SEMAPHORE |
 583                    MXS_DCP_CONTROL0_INTERRUPT |
 584                    MXS_DCP_CONTROL0_ENABLE_HASH;
 585        if (rctx->init)
 586                desc->control0 |= MXS_DCP_CONTROL0_HASH_INIT;
 587
 588        desc->control1 = actx->alg;
 589        desc->next_cmd_addr = 0;
 590        desc->source = buf_phys;
 591        desc->destination = 0;
 592        desc->size = actx->fill;
 593        desc->payload = 0;
 594        desc->status = 0;
 595
 596        /*
 597         * Align driver with hw behavior when generating null hashes
 598         */
 599        if (rctx->init && rctx->fini && desc->size == 0) {
 600                struct hash_alg_common *halg = crypto_hash_alg_common(tfm);
 601                const uint8_t *sha_buf =
 602                        (actx->alg == MXS_DCP_CONTROL1_HASH_SELECT_SHA1) ?
 603                        sha1_null_hash : sha256_null_hash;
 604                memcpy(sdcp->coh->sha_out_buf, sha_buf, halg->digestsize);
 605                ret = 0;
 606                goto done_run;
 607        }
 608
 609        /* Set HASH_TERM bit for last transfer block. */
 610        if (rctx->fini) {
 611                digest_phys = dma_map_single(sdcp->dev, sdcp->coh->sha_out_buf,
 612                                             DCP_SHA_PAY_SZ, DMA_FROM_DEVICE);
 613                ret = dma_mapping_error(sdcp->dev, digest_phys);
 614                if (ret)
 615                        goto done_run;
 616
 617                desc->control0 |= MXS_DCP_CONTROL0_HASH_TERM;
 618                desc->payload = digest_phys;
 619        }
 620
 621        ret = mxs_dcp_start_dma(actx);
 622
 623        if (rctx->fini)
 624                dma_unmap_single(sdcp->dev, digest_phys, DCP_SHA_PAY_SZ,
 625                                 DMA_FROM_DEVICE);
 626
 627done_run:
 628        dma_unmap_single(sdcp->dev, buf_phys, DCP_BUF_SZ, DMA_TO_DEVICE);
 629
 630        return ret;
 631}
 632
 633static int dcp_sha_req_to_buf(struct crypto_async_request *arq)
 634{
 635        struct dcp *sdcp = global_sdcp;
 636
 637        struct ahash_request *req = ahash_request_cast(arq);
 638        struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 639        struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
 640        struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
 641        struct hash_alg_common *halg = crypto_hash_alg_common(tfm);
 642
 643        uint8_t *in_buf = sdcp->coh->sha_in_buf;
 644        uint8_t *out_buf = sdcp->coh->sha_out_buf;
 645
 646        struct scatterlist *src;
 647
 648        unsigned int i, len, clen, oft = 0;
 649        int ret;
 650
 651        int fin = rctx->fini;
 652        if (fin)
 653                rctx->fini = 0;
 654
 655        src = req->src;
 656        len = req->nbytes;
 657
 658        while (len) {
 659                if (actx->fill + len > DCP_BUF_SZ)
 660                        clen = DCP_BUF_SZ - actx->fill;
 661                else
 662                        clen = len;
 663
 664                scatterwalk_map_and_copy(in_buf + actx->fill, src, oft, clen,
 665                                         0);
 666
 667                len -= clen;
 668                oft += clen;
 669                actx->fill += clen;
 670
 671                /*
 672                 * If we filled the buffer and still have some
 673                 * more data, submit the buffer.
 674                 */
 675                if (len && actx->fill == DCP_BUF_SZ) {
 676                        ret = mxs_dcp_run_sha(req);
 677                        if (ret)
 678                                return ret;
 679                        actx->fill = 0;
 680                        rctx->init = 0;
 681                }
 682        }
 683
 684        if (fin) {
 685                rctx->fini = 1;
 686
 687                /* Submit whatever is left. */
 688                if (!req->result)
 689                        return -EINVAL;
 690
 691                ret = mxs_dcp_run_sha(req);
 692                if (ret)
 693                        return ret;
 694
 695                actx->fill = 0;
 696
 697                /* For some reason the result is flipped */
 698                for (i = 0; i < halg->digestsize; i++)
 699                        req->result[i] = out_buf[halg->digestsize - i - 1];
 700        }
 701
 702        return 0;
 703}
 704
 705static int dcp_chan_thread_sha(void *data)
 706{
 707        struct dcp *sdcp = global_sdcp;
 708        const int chan = DCP_CHAN_HASH_SHA;
 709
 710        struct crypto_async_request *backlog;
 711        struct crypto_async_request *arq;
 712        int ret;
 713
 714        while (!kthread_should_stop()) {
 715                set_current_state(TASK_INTERRUPTIBLE);
 716
 717                spin_lock(&sdcp->lock[chan]);
 718                backlog = crypto_get_backlog(&sdcp->queue[chan]);
 719                arq = crypto_dequeue_request(&sdcp->queue[chan]);
 720                spin_unlock(&sdcp->lock[chan]);
 721
 722                if (!backlog && !arq) {
 723                        schedule();
 724                        continue;
 725                }
 726
 727                set_current_state(TASK_RUNNING);
 728
 729                if (backlog)
 730                        backlog->complete(backlog, -EINPROGRESS);
 731
 732                if (arq) {
 733                        ret = dcp_sha_req_to_buf(arq);
 734                        arq->complete(arq, ret);
 735                }
 736        }
 737
 738        return 0;
 739}
 740
 741static int dcp_sha_init(struct ahash_request *req)
 742{
 743        struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 744        struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
 745
 746        struct hash_alg_common *halg = crypto_hash_alg_common(tfm);
 747
 748        /*
 749         * Start hashing session. The code below only inits the
 750         * hashing session context, nothing more.
 751         */
 752        memset(actx, 0, sizeof(*actx));
 753
 754        if (strcmp(halg->base.cra_name, "sha1") == 0)
 755                actx->alg = MXS_DCP_CONTROL1_HASH_SELECT_SHA1;
 756        else
 757                actx->alg = MXS_DCP_CONTROL1_HASH_SELECT_SHA256;
 758
 759        actx->fill = 0;
 760        actx->hot = 0;
 761        actx->chan = DCP_CHAN_HASH_SHA;
 762
 763        mutex_init(&actx->mutex);
 764
 765        return 0;
 766}
 767
 768static int dcp_sha_update_fx(struct ahash_request *req, int fini)
 769{
 770        struct dcp *sdcp = global_sdcp;
 771
 772        struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
 773        struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 774        struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
 775
 776        int ret;
 777
 778        /*
 779         * Ignore requests that have no data in them and are not
 780         * the trailing requests in the stream of requests.
 781         */
 782        if (!req->nbytes && !fini)
 783                return 0;
 784
 785        mutex_lock(&actx->mutex);
 786
 787        rctx->fini = fini;
 788
 789        if (!actx->hot) {
 790                actx->hot = 1;
 791                rctx->init = 1;
 792        }
 793
 794        spin_lock(&sdcp->lock[actx->chan]);
 795        ret = crypto_enqueue_request(&sdcp->queue[actx->chan], &req->base);
 796        spin_unlock(&sdcp->lock[actx->chan]);
 797
 798        wake_up_process(sdcp->thread[actx->chan]);
 799        mutex_unlock(&actx->mutex);
 800
 801        return ret;
 802}
 803
 804static int dcp_sha_update(struct ahash_request *req)
 805{
 806        return dcp_sha_update_fx(req, 0);
 807}
 808
 809static int dcp_sha_final(struct ahash_request *req)
 810{
 811        ahash_request_set_crypt(req, NULL, req->result, 0);
 812        req->nbytes = 0;
 813        return dcp_sha_update_fx(req, 1);
 814}
 815
 816static int dcp_sha_finup(struct ahash_request *req)
 817{
 818        return dcp_sha_update_fx(req, 1);
 819}
 820
 821static int dcp_sha_digest(struct ahash_request *req)
 822{
 823        int ret;
 824
 825        ret = dcp_sha_init(req);
 826        if (ret)
 827                return ret;
 828
 829        return dcp_sha_finup(req);
 830}
 831
 832static int dcp_sha_import(struct ahash_request *req, const void *in)
 833{
 834        struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
 835        struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 836        struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
 837        const struct dcp_export_state *export = in;
 838
 839        memset(rctx, 0, sizeof(struct dcp_sha_req_ctx));
 840        memset(actx, 0, sizeof(struct dcp_async_ctx));
 841        memcpy(rctx, &export->req_ctx, sizeof(struct dcp_sha_req_ctx));
 842        memcpy(actx, &export->async_ctx, sizeof(struct dcp_async_ctx));
 843
 844        return 0;
 845}
 846
 847static int dcp_sha_export(struct ahash_request *req, void *out)
 848{
 849        struct dcp_sha_req_ctx *rctx_state = ahash_request_ctx(req);
 850        struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 851        struct dcp_async_ctx *actx_state = crypto_ahash_ctx(tfm);
 852        struct dcp_export_state *export = out;
 853
 854        memcpy(&export->req_ctx, rctx_state, sizeof(struct dcp_sha_req_ctx));
 855        memcpy(&export->async_ctx, actx_state, sizeof(struct dcp_async_ctx));
 856
 857        return 0;
 858}
 859
 860static int dcp_sha_cra_init(struct crypto_tfm *tfm)
 861{
 862        crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
 863                                 sizeof(struct dcp_sha_req_ctx));
 864        return 0;
 865}
 866
 867static void dcp_sha_cra_exit(struct crypto_tfm *tfm)
 868{
 869}
 870
 871/* AES 128 ECB and AES 128 CBC */
 872static struct skcipher_alg dcp_aes_algs[] = {
 873        {
 874                .base.cra_name          = "ecb(aes)",
 875                .base.cra_driver_name   = "ecb-aes-dcp",
 876                .base.cra_priority      = 400,
 877                .base.cra_alignmask     = 15,
 878                .base.cra_flags         = CRYPTO_ALG_ASYNC |
 879                                          CRYPTO_ALG_NEED_FALLBACK,
 880                .base.cra_blocksize     = AES_BLOCK_SIZE,
 881                .base.cra_ctxsize       = sizeof(struct dcp_async_ctx),
 882                .base.cra_module        = THIS_MODULE,
 883
 884                .min_keysize            = AES_MIN_KEY_SIZE,
 885                .max_keysize            = AES_MAX_KEY_SIZE,
 886                .setkey                 = mxs_dcp_aes_setkey,
 887                .encrypt                = mxs_dcp_aes_ecb_encrypt,
 888                .decrypt                = mxs_dcp_aes_ecb_decrypt,
 889                .init                   = mxs_dcp_aes_fallback_init_tfm,
 890                .exit                   = mxs_dcp_aes_fallback_exit_tfm,
 891        }, {
 892                .base.cra_name          = "cbc(aes)",
 893                .base.cra_driver_name   = "cbc-aes-dcp",
 894                .base.cra_priority      = 400,
 895                .base.cra_alignmask     = 15,
 896                .base.cra_flags         = CRYPTO_ALG_ASYNC |
 897                                          CRYPTO_ALG_NEED_FALLBACK,
 898                .base.cra_blocksize     = AES_BLOCK_SIZE,
 899                .base.cra_ctxsize       = sizeof(struct dcp_async_ctx),
 900                .base.cra_module        = THIS_MODULE,
 901
 902                .min_keysize            = AES_MIN_KEY_SIZE,
 903                .max_keysize            = AES_MAX_KEY_SIZE,
 904                .setkey                 = mxs_dcp_aes_setkey,
 905                .encrypt                = mxs_dcp_aes_cbc_encrypt,
 906                .decrypt                = mxs_dcp_aes_cbc_decrypt,
 907                .ivsize                 = AES_BLOCK_SIZE,
 908                .init                   = mxs_dcp_aes_fallback_init_tfm,
 909                .exit                   = mxs_dcp_aes_fallback_exit_tfm,
 910        },
 911};
 912
 913/* SHA1 */
 914static struct ahash_alg dcp_sha1_alg = {
 915        .init   = dcp_sha_init,
 916        .update = dcp_sha_update,
 917        .final  = dcp_sha_final,
 918        .finup  = dcp_sha_finup,
 919        .digest = dcp_sha_digest,
 920        .import = dcp_sha_import,
 921        .export = dcp_sha_export,
 922        .halg   = {
 923                .digestsize     = SHA1_DIGEST_SIZE,
 924                .statesize      = sizeof(struct dcp_export_state),
 925                .base           = {
 926                        .cra_name               = "sha1",
 927                        .cra_driver_name        = "sha1-dcp",
 928                        .cra_priority           = 400,
 929                        .cra_alignmask          = 63,
 930                        .cra_flags              = CRYPTO_ALG_ASYNC,
 931                        .cra_blocksize          = SHA1_BLOCK_SIZE,
 932                        .cra_ctxsize            = sizeof(struct dcp_async_ctx),
 933                        .cra_module             = THIS_MODULE,
 934                        .cra_init               = dcp_sha_cra_init,
 935                        .cra_exit               = dcp_sha_cra_exit,
 936                },
 937        },
 938};
 939
 940/* SHA256 */
 941static struct ahash_alg dcp_sha256_alg = {
 942        .init   = dcp_sha_init,
 943        .update = dcp_sha_update,
 944        .final  = dcp_sha_final,
 945        .finup  = dcp_sha_finup,
 946        .digest = dcp_sha_digest,
 947        .import = dcp_sha_import,
 948        .export = dcp_sha_export,
 949        .halg   = {
 950                .digestsize     = SHA256_DIGEST_SIZE,
 951                .statesize      = sizeof(struct dcp_export_state),
 952                .base           = {
 953                        .cra_name               = "sha256",
 954                        .cra_driver_name        = "sha256-dcp",
 955                        .cra_priority           = 400,
 956                        .cra_alignmask          = 63,
 957                        .cra_flags              = CRYPTO_ALG_ASYNC,
 958                        .cra_blocksize          = SHA256_BLOCK_SIZE,
 959                        .cra_ctxsize            = sizeof(struct dcp_async_ctx),
 960                        .cra_module             = THIS_MODULE,
 961                        .cra_init               = dcp_sha_cra_init,
 962                        .cra_exit               = dcp_sha_cra_exit,
 963                },
 964        },
 965};
 966
 967static irqreturn_t mxs_dcp_irq(int irq, void *context)
 968{
 969        struct dcp *sdcp = context;
 970        uint32_t stat;
 971        int i;
 972
 973        stat = readl(sdcp->base + MXS_DCP_STAT);
 974        stat &= MXS_DCP_STAT_IRQ_MASK;
 975        if (!stat)
 976                return IRQ_NONE;
 977
 978        /* Clear the interrupts. */
 979        writel(stat, sdcp->base + MXS_DCP_STAT_CLR);
 980
 981        /* Complete the DMA requests that finished. */
 982        for (i = 0; i < DCP_MAX_CHANS; i++)
 983                if (stat & (1 << i))
 984                        complete(&sdcp->completion[i]);
 985
 986        return IRQ_HANDLED;
 987}
 988
 989static int mxs_dcp_probe(struct platform_device *pdev)
 990{
 991        struct device *dev = &pdev->dev;
 992        struct dcp *sdcp = NULL;
 993        int i, ret;
 994        int dcp_vmi_irq, dcp_irq;
 995
 996        if (global_sdcp) {
 997                dev_err(dev, "Only one DCP instance allowed!\n");
 998                return -ENODEV;
 999        }
1000
1001        dcp_vmi_irq = platform_get_irq(pdev, 0);
1002        if (dcp_vmi_irq < 0)
1003                return dcp_vmi_irq;
1004
1005        dcp_irq = platform_get_irq(pdev, 1);
1006        if (dcp_irq < 0)
1007                return dcp_irq;
1008
1009        sdcp = devm_kzalloc(dev, sizeof(*sdcp), GFP_KERNEL);
1010        if (!sdcp)
1011                return -ENOMEM;
1012
1013        sdcp->dev = dev;
1014        sdcp->base = devm_platform_ioremap_resource(pdev, 0);
1015        if (IS_ERR(sdcp->base))
1016                return PTR_ERR(sdcp->base);
1017
1018
1019        ret = devm_request_irq(dev, dcp_vmi_irq, mxs_dcp_irq, 0,
1020                               "dcp-vmi-irq", sdcp);
1021        if (ret) {
1022                dev_err(dev, "Failed to claim DCP VMI IRQ!\n");
1023                return ret;
1024        }
1025
1026        ret = devm_request_irq(dev, dcp_irq, mxs_dcp_irq, 0,
1027                               "dcp-irq", sdcp);
1028        if (ret) {
1029                dev_err(dev, "Failed to claim DCP IRQ!\n");
1030                return ret;
1031        }
1032
1033        /* Allocate coherent helper block. */
1034        sdcp->coh = devm_kzalloc(dev, sizeof(*sdcp->coh) + DCP_ALIGNMENT,
1035                                   GFP_KERNEL);
1036        if (!sdcp->coh)
1037                return -ENOMEM;
1038
1039        /* Re-align the structure so it fits the DCP constraints. */
1040        sdcp->coh = PTR_ALIGN(sdcp->coh, DCP_ALIGNMENT);
1041
1042        /* DCP clock is optional, only used on some SOCs */
1043        sdcp->dcp_clk = devm_clk_get(dev, "dcp");
1044        if (IS_ERR(sdcp->dcp_clk)) {
1045                if (sdcp->dcp_clk != ERR_PTR(-ENOENT))
1046                        return PTR_ERR(sdcp->dcp_clk);
1047                sdcp->dcp_clk = NULL;
1048        }
1049        ret = clk_prepare_enable(sdcp->dcp_clk);
1050        if (ret)
1051                return ret;
1052
1053        /* Restart the DCP block. */
1054        ret = stmp_reset_block(sdcp->base);
1055        if (ret) {
1056                dev_err(dev, "Failed reset\n");
1057                goto err_disable_unprepare_clk;
1058        }
1059
1060        /* Initialize control register. */
1061        writel(MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES |
1062               MXS_DCP_CTRL_ENABLE_CONTEXT_CACHING | 0xf,
1063               sdcp->base + MXS_DCP_CTRL);
1064
1065        /* Enable all DCP DMA channels. */
1066        writel(MXS_DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK,
1067               sdcp->base + MXS_DCP_CHANNELCTRL);
1068
1069        /*
1070         * We do not enable context switching. Give the context buffer a
1071         * pointer to an illegal address so if context switching is
1072         * inadvertantly enabled, the DCP will return an error instead of
1073         * trashing good memory. The DCP DMA cannot access ROM, so any ROM
1074         * address will do.
1075         */
1076        writel(0xffff0000, sdcp->base + MXS_DCP_CONTEXT);
1077        for (i = 0; i < DCP_MAX_CHANS; i++)
1078                writel(0xffffffff, sdcp->base + MXS_DCP_CH_N_STAT_CLR(i));
1079        writel(0xffffffff, sdcp->base + MXS_DCP_STAT_CLR);
1080
1081        global_sdcp = sdcp;
1082
1083        platform_set_drvdata(pdev, sdcp);
1084
1085        for (i = 0; i < DCP_MAX_CHANS; i++) {
1086                spin_lock_init(&sdcp->lock[i]);
1087                init_completion(&sdcp->completion[i]);
1088                crypto_init_queue(&sdcp->queue[i], 50);
1089        }
1090
1091        /* Create the SHA and AES handler threads. */
1092        sdcp->thread[DCP_CHAN_HASH_SHA] = kthread_run(dcp_chan_thread_sha,
1093                                                      NULL, "mxs_dcp_chan/sha");
1094        if (IS_ERR(sdcp->thread[DCP_CHAN_HASH_SHA])) {
1095                dev_err(dev, "Error starting SHA thread!\n");
1096                ret = PTR_ERR(sdcp->thread[DCP_CHAN_HASH_SHA]);
1097                goto err_disable_unprepare_clk;
1098        }
1099
1100        sdcp->thread[DCP_CHAN_CRYPTO] = kthread_run(dcp_chan_thread_aes,
1101                                                    NULL, "mxs_dcp_chan/aes");
1102        if (IS_ERR(sdcp->thread[DCP_CHAN_CRYPTO])) {
1103                dev_err(dev, "Error starting SHA thread!\n");
1104                ret = PTR_ERR(sdcp->thread[DCP_CHAN_CRYPTO]);
1105                goto err_destroy_sha_thread;
1106        }
1107
1108        /* Register the various crypto algorithms. */
1109        sdcp->caps = readl(sdcp->base + MXS_DCP_CAPABILITY1);
1110
1111        if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128) {
1112                ret = crypto_register_skciphers(dcp_aes_algs,
1113                                                ARRAY_SIZE(dcp_aes_algs));
1114                if (ret) {
1115                        /* Failed to register algorithm. */
1116                        dev_err(dev, "Failed to register AES crypto!\n");
1117                        goto err_destroy_aes_thread;
1118                }
1119        }
1120
1121        if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1) {
1122                ret = crypto_register_ahash(&dcp_sha1_alg);
1123                if (ret) {
1124                        dev_err(dev, "Failed to register %s hash!\n",
1125                                dcp_sha1_alg.halg.base.cra_name);
1126                        goto err_unregister_aes;
1127                }
1128        }
1129
1130        if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA256) {
1131                ret = crypto_register_ahash(&dcp_sha256_alg);
1132                if (ret) {
1133                        dev_err(dev, "Failed to register %s hash!\n",
1134                                dcp_sha256_alg.halg.base.cra_name);
1135                        goto err_unregister_sha1;
1136                }
1137        }
1138
1139        return 0;
1140
1141err_unregister_sha1:
1142        if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1)
1143                crypto_unregister_ahash(&dcp_sha1_alg);
1144
1145err_unregister_aes:
1146        if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128)
1147                crypto_unregister_skciphers(dcp_aes_algs, ARRAY_SIZE(dcp_aes_algs));
1148
1149err_destroy_aes_thread:
1150        kthread_stop(sdcp->thread[DCP_CHAN_CRYPTO]);
1151
1152err_destroy_sha_thread:
1153        kthread_stop(sdcp->thread[DCP_CHAN_HASH_SHA]);
1154
1155err_disable_unprepare_clk:
1156        clk_disable_unprepare(sdcp->dcp_clk);
1157
1158        return ret;
1159}
1160
1161static int mxs_dcp_remove(struct platform_device *pdev)
1162{
1163        struct dcp *sdcp = platform_get_drvdata(pdev);
1164
1165        if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA256)
1166                crypto_unregister_ahash(&dcp_sha256_alg);
1167
1168        if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1)
1169                crypto_unregister_ahash(&dcp_sha1_alg);
1170
1171        if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128)
1172                crypto_unregister_skciphers(dcp_aes_algs, ARRAY_SIZE(dcp_aes_algs));
1173
1174        kthread_stop(sdcp->thread[DCP_CHAN_HASH_SHA]);
1175        kthread_stop(sdcp->thread[DCP_CHAN_CRYPTO]);
1176
1177        clk_disable_unprepare(sdcp->dcp_clk);
1178
1179        platform_set_drvdata(pdev, NULL);
1180
1181        global_sdcp = NULL;
1182
1183        return 0;
1184}
1185
1186static const struct of_device_id mxs_dcp_dt_ids[] = {
1187        { .compatible = "fsl,imx23-dcp", .data = NULL, },
1188        { .compatible = "fsl,imx28-dcp", .data = NULL, },
1189        { /* sentinel */ }
1190};
1191
1192MODULE_DEVICE_TABLE(of, mxs_dcp_dt_ids);
1193
1194static struct platform_driver mxs_dcp_driver = {
1195        .probe  = mxs_dcp_probe,
1196        .remove = mxs_dcp_remove,
1197        .driver = {
1198                .name           = "mxs-dcp",
1199                .of_match_table = mxs_dcp_dt_ids,
1200        },
1201};
1202
1203module_platform_driver(mxs_dcp_driver);
1204
1205MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
1206MODULE_DESCRIPTION("Freescale MXS DCP Driver");
1207MODULE_LICENSE("GPL");
1208MODULE_ALIAS("platform:mxs-dcp");
1209