linux/drivers/scsi/qla2xxx/qla_nx.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * QLogic Fibre Channel HBA Driver
   4 * Copyright (c)  2003-2014 QLogic Corporation
   5 */
   6#include "qla_def.h"
   7#include <linux/delay.h>
   8#include <linux/io-64-nonatomic-lo-hi.h>
   9#include <linux/pci.h>
  10#include <linux/ratelimit.h>
  11#include <linux/vmalloc.h>
  12#include <scsi/scsi_tcq.h>
  13
  14#define MASK(n)                 ((1ULL<<(n))-1)
  15#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
  16        ((addr >> 25) & 0x3ff))
  17#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
  18        ((addr >> 25) & 0x3ff))
  19#define MS_WIN(addr) (addr & 0x0ffc0000)
  20#define QLA82XX_PCI_MN_2M   (0)
  21#define QLA82XX_PCI_MS_2M   (0x80000)
  22#define QLA82XX_PCI_OCM0_2M (0xc0000)
  23#define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
  24#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
  25#define BLOCK_PROTECT_BITS 0x0F
  26
  27/* CRB window related */
  28#define CRB_BLK(off)    ((off >> 20) & 0x3f)
  29#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  30#define CRB_WINDOW_2M   (0x130060)
  31#define QLA82XX_PCI_CAMQM_2M_END        (0x04800800UL)
  32#define CRB_HI(off)     ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
  33                        ((off) & 0xf0000))
  34#define QLA82XX_PCI_CAMQM_2M_BASE       (0x000ff800UL)
  35#define CRB_INDIRECT_2M (0x1e0000UL)
  36
  37#define MAX_CRB_XFORM 60
  38static unsigned long crb_addr_xform[MAX_CRB_XFORM];
  39static int qla82xx_crb_table_initialized;
  40
  41#define qla82xx_crb_addr_transform(name) \
  42        (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
  43        QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
  44
  45const int MD_MIU_TEST_AGT_RDDATA[] = {
  46        0x410000A8, 0x410000AC,
  47        0x410000B8, 0x410000BC
  48};
  49
  50static void qla82xx_crb_addr_transform_setup(void)
  51{
  52        qla82xx_crb_addr_transform(XDMA);
  53        qla82xx_crb_addr_transform(TIMR);
  54        qla82xx_crb_addr_transform(SRE);
  55        qla82xx_crb_addr_transform(SQN3);
  56        qla82xx_crb_addr_transform(SQN2);
  57        qla82xx_crb_addr_transform(SQN1);
  58        qla82xx_crb_addr_transform(SQN0);
  59        qla82xx_crb_addr_transform(SQS3);
  60        qla82xx_crb_addr_transform(SQS2);
  61        qla82xx_crb_addr_transform(SQS1);
  62        qla82xx_crb_addr_transform(SQS0);
  63        qla82xx_crb_addr_transform(RPMX7);
  64        qla82xx_crb_addr_transform(RPMX6);
  65        qla82xx_crb_addr_transform(RPMX5);
  66        qla82xx_crb_addr_transform(RPMX4);
  67        qla82xx_crb_addr_transform(RPMX3);
  68        qla82xx_crb_addr_transform(RPMX2);
  69        qla82xx_crb_addr_transform(RPMX1);
  70        qla82xx_crb_addr_transform(RPMX0);
  71        qla82xx_crb_addr_transform(ROMUSB);
  72        qla82xx_crb_addr_transform(SN);
  73        qla82xx_crb_addr_transform(QMN);
  74        qla82xx_crb_addr_transform(QMS);
  75        qla82xx_crb_addr_transform(PGNI);
  76        qla82xx_crb_addr_transform(PGND);
  77        qla82xx_crb_addr_transform(PGN3);
  78        qla82xx_crb_addr_transform(PGN2);
  79        qla82xx_crb_addr_transform(PGN1);
  80        qla82xx_crb_addr_transform(PGN0);
  81        qla82xx_crb_addr_transform(PGSI);
  82        qla82xx_crb_addr_transform(PGSD);
  83        qla82xx_crb_addr_transform(PGS3);
  84        qla82xx_crb_addr_transform(PGS2);
  85        qla82xx_crb_addr_transform(PGS1);
  86        qla82xx_crb_addr_transform(PGS0);
  87        qla82xx_crb_addr_transform(PS);
  88        qla82xx_crb_addr_transform(PH);
  89        qla82xx_crb_addr_transform(NIU);
  90        qla82xx_crb_addr_transform(I2Q);
  91        qla82xx_crb_addr_transform(EG);
  92        qla82xx_crb_addr_transform(MN);
  93        qla82xx_crb_addr_transform(MS);
  94        qla82xx_crb_addr_transform(CAS2);
  95        qla82xx_crb_addr_transform(CAS1);
  96        qla82xx_crb_addr_transform(CAS0);
  97        qla82xx_crb_addr_transform(CAM);
  98        qla82xx_crb_addr_transform(C2C1);
  99        qla82xx_crb_addr_transform(C2C0);
 100        qla82xx_crb_addr_transform(SMB);
 101        qla82xx_crb_addr_transform(OCM0);
 102        /*
 103         * Used only in P3 just define it for P2 also.
 104         */
 105        qla82xx_crb_addr_transform(I2C0);
 106
 107        qla82xx_crb_table_initialized = 1;
 108}
 109
 110static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
 111        {{{0, 0,         0,         0} } },
 112        {{{1, 0x0100000, 0x0102000, 0x120000},
 113        {1, 0x0110000, 0x0120000, 0x130000},
 114        {1, 0x0120000, 0x0122000, 0x124000},
 115        {1, 0x0130000, 0x0132000, 0x126000},
 116        {1, 0x0140000, 0x0142000, 0x128000},
 117        {1, 0x0150000, 0x0152000, 0x12a000},
 118        {1, 0x0160000, 0x0170000, 0x110000},
 119        {1, 0x0170000, 0x0172000, 0x12e000},
 120        {0, 0x0000000, 0x0000000, 0x000000},
 121        {0, 0x0000000, 0x0000000, 0x000000},
 122        {0, 0x0000000, 0x0000000, 0x000000},
 123        {0, 0x0000000, 0x0000000, 0x000000},
 124        {0, 0x0000000, 0x0000000, 0x000000},
 125        {0, 0x0000000, 0x0000000, 0x000000},
 126        {1, 0x01e0000, 0x01e0800, 0x122000},
 127        {0, 0x0000000, 0x0000000, 0x000000} } } ,
 128        {{{1, 0x0200000, 0x0210000, 0x180000} } },
 129        {{{0, 0,         0,         0} } },
 130        {{{1, 0x0400000, 0x0401000, 0x169000} } },
 131        {{{1, 0x0500000, 0x0510000, 0x140000} } },
 132        {{{1, 0x0600000, 0x0610000, 0x1c0000} } },
 133        {{{1, 0x0700000, 0x0704000, 0x1b8000} } },
 134        {{{1, 0x0800000, 0x0802000, 0x170000},
 135        {0, 0x0000000, 0x0000000, 0x000000},
 136        {0, 0x0000000, 0x0000000, 0x000000},
 137        {0, 0x0000000, 0x0000000, 0x000000},
 138        {0, 0x0000000, 0x0000000, 0x000000},
 139        {0, 0x0000000, 0x0000000, 0x000000},
 140        {0, 0x0000000, 0x0000000, 0x000000},
 141        {0, 0x0000000, 0x0000000, 0x000000},
 142        {0, 0x0000000, 0x0000000, 0x000000},
 143        {0, 0x0000000, 0x0000000, 0x000000},
 144        {0, 0x0000000, 0x0000000, 0x000000},
 145        {0, 0x0000000, 0x0000000, 0x000000},
 146        {0, 0x0000000, 0x0000000, 0x000000},
 147        {0, 0x0000000, 0x0000000, 0x000000},
 148        {0, 0x0000000, 0x0000000, 0x000000},
 149        {1, 0x08f0000, 0x08f2000, 0x172000} } },
 150        {{{1, 0x0900000, 0x0902000, 0x174000},
 151        {0, 0x0000000, 0x0000000, 0x000000},
 152        {0, 0x0000000, 0x0000000, 0x000000},
 153        {0, 0x0000000, 0x0000000, 0x000000},
 154        {0, 0x0000000, 0x0000000, 0x000000},
 155        {0, 0x0000000, 0x0000000, 0x000000},
 156        {0, 0x0000000, 0x0000000, 0x000000},
 157        {0, 0x0000000, 0x0000000, 0x000000},
 158        {0, 0x0000000, 0x0000000, 0x000000},
 159        {0, 0x0000000, 0x0000000, 0x000000},
 160        {0, 0x0000000, 0x0000000, 0x000000},
 161        {0, 0x0000000, 0x0000000, 0x000000},
 162        {0, 0x0000000, 0x0000000, 0x000000},
 163        {0, 0x0000000, 0x0000000, 0x000000},
 164        {0, 0x0000000, 0x0000000, 0x000000},
 165        {1, 0x09f0000, 0x09f2000, 0x176000} } },
 166        {{{0, 0x0a00000, 0x0a02000, 0x178000},
 167        {0, 0x0000000, 0x0000000, 0x000000},
 168        {0, 0x0000000, 0x0000000, 0x000000},
 169        {0, 0x0000000, 0x0000000, 0x000000},
 170        {0, 0x0000000, 0x0000000, 0x000000},
 171        {0, 0x0000000, 0x0000000, 0x000000},
 172        {0, 0x0000000, 0x0000000, 0x000000},
 173        {0, 0x0000000, 0x0000000, 0x000000},
 174        {0, 0x0000000, 0x0000000, 0x000000},
 175        {0, 0x0000000, 0x0000000, 0x000000},
 176        {0, 0x0000000, 0x0000000, 0x000000},
 177        {0, 0x0000000, 0x0000000, 0x000000},
 178        {0, 0x0000000, 0x0000000, 0x000000},
 179        {0, 0x0000000, 0x0000000, 0x000000},
 180        {0, 0x0000000, 0x0000000, 0x000000},
 181        {1, 0x0af0000, 0x0af2000, 0x17a000} } },
 182        {{{0, 0x0b00000, 0x0b02000, 0x17c000},
 183        {0, 0x0000000, 0x0000000, 0x000000},
 184        {0, 0x0000000, 0x0000000, 0x000000},
 185        {0, 0x0000000, 0x0000000, 0x000000},
 186        {0, 0x0000000, 0x0000000, 0x000000},
 187        {0, 0x0000000, 0x0000000, 0x000000},
 188        {0, 0x0000000, 0x0000000, 0x000000},
 189        {0, 0x0000000, 0x0000000, 0x000000},
 190        {0, 0x0000000, 0x0000000, 0x000000},
 191        {0, 0x0000000, 0x0000000, 0x000000},
 192        {0, 0x0000000, 0x0000000, 0x000000},
 193        {0, 0x0000000, 0x0000000, 0x000000},
 194        {0, 0x0000000, 0x0000000, 0x000000},
 195        {0, 0x0000000, 0x0000000, 0x000000},
 196        {0, 0x0000000, 0x0000000, 0x000000},
 197        {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
 198        {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },
 199        {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },
 200        {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },
 201        {{{1, 0x0f00000, 0x0f01000, 0x164000} } },
 202        {{{0, 0x1000000, 0x1004000, 0x1a8000} } },
 203        {{{1, 0x1100000, 0x1101000, 0x160000} } },
 204        {{{1, 0x1200000, 0x1201000, 0x161000} } },
 205        {{{1, 0x1300000, 0x1301000, 0x162000} } },
 206        {{{1, 0x1400000, 0x1401000, 0x163000} } },
 207        {{{1, 0x1500000, 0x1501000, 0x165000} } },
 208        {{{1, 0x1600000, 0x1601000, 0x166000} } },
 209        {{{0, 0,         0,         0} } },
 210        {{{0, 0,         0,         0} } },
 211        {{{0, 0,         0,         0} } },
 212        {{{0, 0,         0,         0} } },
 213        {{{0, 0,         0,         0} } },
 214        {{{0, 0,         0,         0} } },
 215        {{{1, 0x1d00000, 0x1d10000, 0x190000} } },
 216        {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },
 217        {{{1, 0x1f00000, 0x1f10000, 0x150000} } },
 218        {{{0} } },
 219        {{{1, 0x2100000, 0x2102000, 0x120000},
 220        {1, 0x2110000, 0x2120000, 0x130000},
 221        {1, 0x2120000, 0x2122000, 0x124000},
 222        {1, 0x2130000, 0x2132000, 0x126000},
 223        {1, 0x2140000, 0x2142000, 0x128000},
 224        {1, 0x2150000, 0x2152000, 0x12a000},
 225        {1, 0x2160000, 0x2170000, 0x110000},
 226        {1, 0x2170000, 0x2172000, 0x12e000},
 227        {0, 0x0000000, 0x0000000, 0x000000},
 228        {0, 0x0000000, 0x0000000, 0x000000},
 229        {0, 0x0000000, 0x0000000, 0x000000},
 230        {0, 0x0000000, 0x0000000, 0x000000},
 231        {0, 0x0000000, 0x0000000, 0x000000},
 232        {0, 0x0000000, 0x0000000, 0x000000},
 233        {0, 0x0000000, 0x0000000, 0x000000},
 234        {0, 0x0000000, 0x0000000, 0x000000} } },
 235        {{{1, 0x2200000, 0x2204000, 0x1b0000} } },
 236        {{{0} } },
 237        {{{0} } },
 238        {{{0} } },
 239        {{{0} } },
 240        {{{0} } },
 241        {{{1, 0x2800000, 0x2804000, 0x1a4000} } },
 242        {{{1, 0x2900000, 0x2901000, 0x16b000} } },
 243        {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },
 244        {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },
 245        {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },
 246        {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },
 247        {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },
 248        {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },
 249        {{{1, 0x3000000, 0x3000400, 0x1adc00} } },
 250        {{{0, 0x3100000, 0x3104000, 0x1a8000} } },
 251        {{{1, 0x3200000, 0x3204000, 0x1d4000} } },
 252        {{{1, 0x3300000, 0x3304000, 0x1a0000} } },
 253        {{{0} } },
 254        {{{1, 0x3500000, 0x3500400, 0x1ac000} } },
 255        {{{1, 0x3600000, 0x3600400, 0x1ae000} } },
 256        {{{1, 0x3700000, 0x3700400, 0x1ae400} } },
 257        {{{1, 0x3800000, 0x3804000, 0x1d0000} } },
 258        {{{1, 0x3900000, 0x3904000, 0x1b4000} } },
 259        {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },
 260        {{{0} } },
 261        {{{0} } },
 262        {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },
 263        {{{1, 0x3e00000, 0x3e01000, 0x167000} } },
 264        {{{1, 0x3f00000, 0x3f01000, 0x168000} } }
 265};
 266
 267/*
 268 * top 12 bits of crb internal address (hub, agent)
 269 */
 270static unsigned qla82xx_crb_hub_agt[64] = {
 271        0,
 272        QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
 273        QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
 274        QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
 275        0,
 276        QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
 277        QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
 278        QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
 279        QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
 280        QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
 281        QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
 282        QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
 283        QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
 284        QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
 285        QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
 286        QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
 287        QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
 288        QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
 289        QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
 290        QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
 291        QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
 292        QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
 293        QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
 294        QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
 295        QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
 296        QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
 297        QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
 298        0,
 299        QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
 300        QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
 301        0,
 302        QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
 303        0,
 304        QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
 305        QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
 306        0,
 307        0,
 308        0,
 309        0,
 310        0,
 311        QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
 312        0,
 313        QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
 314        QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
 315        QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
 316        QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
 317        QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
 318        QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
 319        QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
 320        QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
 321        QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
 322        QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
 323        0,
 324        QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
 325        QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
 326        QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
 327        QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
 328        0,
 329        QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
 330        QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
 331        QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
 332        0,
 333        QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
 334        0,
 335};
 336
 337/* Device states */
 338static char *q_dev_state[] = {
 339         "Unknown",
 340        "Cold",
 341        "Initializing",
 342        "Ready",
 343        "Need Reset",
 344        "Need Quiescent",
 345        "Failed",
 346        "Quiescent",
 347};
 348
 349char *qdev_state(uint32_t dev_state)
 350{
 351        return q_dev_state[dev_state];
 352}
 353
 354/*
 355 * In: 'off_in' is offset from CRB space in 128M pci map
 356 * Out: 'off_out' is 2M pci map addr
 357 * side effect: lock crb window
 358 */
 359static void
 360qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong off_in,
 361                             void __iomem **off_out)
 362{
 363        u32 win_read;
 364        scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 365
 366        ha->crb_win = CRB_HI(off_in);
 367        writel(ha->crb_win, CRB_WINDOW_2M + ha->nx_pcibase);
 368
 369        /* Read back value to make sure write has gone through before trying
 370         * to use it.
 371         */
 372        win_read = rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase);
 373        if (win_read != ha->crb_win) {
 374                ql_dbg(ql_dbg_p3p, vha, 0xb000,
 375                    "%s: Written crbwin (0x%x) "
 376                    "!= Read crbwin (0x%x), off=0x%lx.\n",
 377                    __func__, ha->crb_win, win_read, off_in);
 378        }
 379        *off_out = (off_in & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
 380}
 381
 382static int
 383qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong off_in,
 384                            void __iomem **off_out)
 385{
 386        struct crb_128M_2M_sub_block_map *m;
 387
 388        if (off_in >= QLA82XX_CRB_MAX)
 389                return -1;
 390
 391        if (off_in >= QLA82XX_PCI_CAMQM && off_in < QLA82XX_PCI_CAMQM_2M_END) {
 392                *off_out = (off_in - QLA82XX_PCI_CAMQM) +
 393                    QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
 394                return 0;
 395        }
 396
 397        if (off_in < QLA82XX_PCI_CRBSPACE)
 398                return -1;
 399
 400        off_in -= QLA82XX_PCI_CRBSPACE;
 401
 402        /* Try direct map */
 403        m = &crb_128M_2M_map[CRB_BLK(off_in)].sub_block[CRB_SUBBLK(off_in)];
 404
 405        if (m->valid && (m->start_128M <= off_in) && (m->end_128M > off_in)) {
 406                *off_out = off_in + m->start_2M - m->start_128M + ha->nx_pcibase;
 407                return 0;
 408        }
 409        /* Not in direct map, use crb window */
 410        *off_out = (void __iomem *)off_in;
 411        return 1;
 412}
 413
 414#define CRB_WIN_LOCK_TIMEOUT 100000000
 415static int qla82xx_crb_win_lock(struct qla_hw_data *ha)
 416{
 417        int done = 0, timeout = 0;
 418
 419        while (!done) {
 420                /* acquire semaphore3 from PCI HW block */
 421                done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
 422                if (done == 1)
 423                        break;
 424                if (timeout >= CRB_WIN_LOCK_TIMEOUT)
 425                        return -1;
 426                timeout++;
 427        }
 428        qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum);
 429        return 0;
 430}
 431
 432int
 433qla82xx_wr_32(struct qla_hw_data *ha, ulong off_in, u32 data)
 434{
 435        void __iomem *off;
 436        unsigned long flags = 0;
 437        int rv;
 438
 439        rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off);
 440
 441        BUG_ON(rv == -1);
 442
 443        if (rv == 1) {
 444#ifndef __CHECKER__
 445                write_lock_irqsave(&ha->hw_lock, flags);
 446#endif
 447                qla82xx_crb_win_lock(ha);
 448                qla82xx_pci_set_crbwindow_2M(ha, off_in, &off);
 449        }
 450
 451        writel(data, (void __iomem *)off);
 452
 453        if (rv == 1) {
 454                qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
 455#ifndef __CHECKER__
 456                write_unlock_irqrestore(&ha->hw_lock, flags);
 457#endif
 458        }
 459        return 0;
 460}
 461
 462int
 463qla82xx_rd_32(struct qla_hw_data *ha, ulong off_in)
 464{
 465        void __iomem *off;
 466        unsigned long flags = 0;
 467        int rv;
 468        u32 data;
 469
 470        rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off);
 471
 472        BUG_ON(rv == -1);
 473
 474        if (rv == 1) {
 475#ifndef __CHECKER__
 476                write_lock_irqsave(&ha->hw_lock, flags);
 477#endif
 478                qla82xx_crb_win_lock(ha);
 479                qla82xx_pci_set_crbwindow_2M(ha, off_in, &off);
 480        }
 481        data = rd_reg_dword(off);
 482
 483        if (rv == 1) {
 484                qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
 485#ifndef __CHECKER__
 486                write_unlock_irqrestore(&ha->hw_lock, flags);
 487#endif
 488        }
 489        return data;
 490}
 491
 492/*
 493 * Context: task, might sleep
 494 */
 495int qla82xx_idc_lock(struct qla_hw_data *ha)
 496{
 497        const int delay_ms = 100, timeout_ms = 2000;
 498        int done, total = 0;
 499
 500        might_sleep();
 501
 502        while (true) {
 503                /* acquire semaphore5 from PCI HW block */
 504                done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
 505                if (done == 1)
 506                        break;
 507                if (WARN_ON_ONCE(total >= timeout_ms))
 508                        return -1;
 509
 510                total += delay_ms;
 511                msleep(delay_ms);
 512        }
 513
 514        return 0;
 515}
 516
 517void qla82xx_idc_unlock(struct qla_hw_data *ha)
 518{
 519        qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
 520}
 521
 522/*
 523 * check memory access boundary.
 524 * used by test agent. support ddr access only for now
 525 */
 526static unsigned long
 527qla82xx_pci_mem_bound_check(struct qla_hw_data *ha,
 528        unsigned long long addr, int size)
 529{
 530        if (!addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
 531                QLA82XX_ADDR_DDR_NET_MAX) ||
 532                !addr_in_range(addr + size - 1, QLA82XX_ADDR_DDR_NET,
 533                QLA82XX_ADDR_DDR_NET_MAX) ||
 534                ((size != 1) && (size != 2) && (size != 4) && (size != 8)))
 535                        return 0;
 536        else
 537                return 1;
 538}
 539
 540static int qla82xx_pci_set_window_warning_count;
 541
 542static unsigned long
 543qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr)
 544{
 545        int window;
 546        u32 win_read;
 547        scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 548
 549        if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
 550                QLA82XX_ADDR_DDR_NET_MAX)) {
 551                /* DDR network side */
 552                window = MN_WIN(addr);
 553                ha->ddr_mn_window = window;
 554                qla82xx_wr_32(ha,
 555                        ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
 556                win_read = qla82xx_rd_32(ha,
 557                        ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
 558                if ((win_read << 17) != window) {
 559                        ql_dbg(ql_dbg_p3p, vha, 0xb003,
 560                            "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n",
 561                            __func__, window, win_read);
 562                }
 563                addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
 564        } else if (addr_in_range(addr, QLA82XX_ADDR_OCM0,
 565                QLA82XX_ADDR_OCM0_MAX)) {
 566                unsigned int temp1;
 567
 568                if ((addr & 0x00ff800) == 0xff800) {
 569                        ql_log(ql_log_warn, vha, 0xb004,
 570                            "%s: QM access not handled.\n", __func__);
 571                        addr = -1UL;
 572                }
 573                window = OCM_WIN(addr);
 574                ha->ddr_mn_window = window;
 575                qla82xx_wr_32(ha,
 576                        ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
 577                win_read = qla82xx_rd_32(ha,
 578                        ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
 579                temp1 = ((window & 0x1FF) << 7) |
 580                    ((window & 0x0FFFE0000) >> 17);
 581                if (win_read != temp1) {
 582                        ql_log(ql_log_warn, vha, 0xb005,
 583                            "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n",
 584                            __func__, temp1, win_read);
 585                }
 586                addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
 587
 588        } else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET,
 589                QLA82XX_P3_ADDR_QDR_NET_MAX)) {
 590                /* QDR network side */
 591                window = MS_WIN(addr);
 592                ha->qdr_sn_window = window;
 593                qla82xx_wr_32(ha,
 594                        ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window);
 595                win_read = qla82xx_rd_32(ha,
 596                        ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
 597                if (win_read != window) {
 598                        ql_log(ql_log_warn, vha, 0xb006,
 599                            "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n",
 600                            __func__, window, win_read);
 601                }
 602                addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
 603        } else {
 604                /*
 605                 * peg gdb frequently accesses memory that doesn't exist,
 606                 * this limits the chit chat so debugging isn't slowed down.
 607                 */
 608                if ((qla82xx_pci_set_window_warning_count++ < 8) ||
 609                    (qla82xx_pci_set_window_warning_count%64 == 0)) {
 610                        ql_log(ql_log_warn, vha, 0xb007,
 611                            "%s: Warning:%s Unknown address range!.\n",
 612                            __func__, QLA2XXX_DRIVER_NAME);
 613                }
 614                addr = -1UL;
 615        }
 616        return addr;
 617}
 618
 619/* check if address is in the same windows as the previous access */
 620static int qla82xx_pci_is_same_window(struct qla_hw_data *ha,
 621        unsigned long long addr)
 622{
 623        int                     window;
 624        unsigned long long      qdr_max;
 625
 626        qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
 627
 628        /* DDR network side */
 629        if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
 630                QLA82XX_ADDR_DDR_NET_MAX))
 631                BUG();
 632        else if (addr_in_range(addr, QLA82XX_ADDR_OCM0,
 633                QLA82XX_ADDR_OCM0_MAX))
 634                return 1;
 635        else if (addr_in_range(addr, QLA82XX_ADDR_OCM1,
 636                QLA82XX_ADDR_OCM1_MAX))
 637                return 1;
 638        else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) {
 639                /* QDR network side */
 640                window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
 641                if (ha->qdr_sn_window == window)
 642                        return 1;
 643        }
 644        return 0;
 645}
 646
 647static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha,
 648        u64 off, void *data, int size)
 649{
 650        unsigned long   flags;
 651        void __iomem *addr = NULL;
 652        int             ret = 0;
 653        u64             start;
 654        uint8_t __iomem  *mem_ptr = NULL;
 655        unsigned long   mem_base;
 656        unsigned long   mem_page;
 657        scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 658
 659        write_lock_irqsave(&ha->hw_lock, flags);
 660
 661        /*
 662         * If attempting to access unknown address or straddle hw windows,
 663         * do not access.
 664         */
 665        start = qla82xx_pci_set_window(ha, off);
 666        if ((start == -1UL) ||
 667                (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
 668                write_unlock_irqrestore(&ha->hw_lock, flags);
 669                ql_log(ql_log_fatal, vha, 0xb008,
 670                    "%s out of bound pci memory "
 671                    "access, offset is 0x%llx.\n",
 672                    QLA2XXX_DRIVER_NAME, off);
 673                return -1;
 674        }
 675
 676        write_unlock_irqrestore(&ha->hw_lock, flags);
 677        mem_base = pci_resource_start(ha->pdev, 0);
 678        mem_page = start & PAGE_MASK;
 679        /* Map two pages whenever user tries to access addresses in two
 680        * consecutive pages.
 681        */
 682        if (mem_page != ((start + size - 1) & PAGE_MASK))
 683                mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
 684        else
 685                mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
 686        if (mem_ptr == NULL) {
 687                *(u8  *)data = 0;
 688                return -1;
 689        }
 690        addr = mem_ptr;
 691        addr += start & (PAGE_SIZE - 1);
 692        write_lock_irqsave(&ha->hw_lock, flags);
 693
 694        switch (size) {
 695        case 1:
 696                *(u8  *)data = readb(addr);
 697                break;
 698        case 2:
 699                *(u16 *)data = readw(addr);
 700                break;
 701        case 4:
 702                *(u32 *)data = readl(addr);
 703                break;
 704        case 8:
 705                *(u64 *)data = readq(addr);
 706                break;
 707        default:
 708                ret = -1;
 709                break;
 710        }
 711        write_unlock_irqrestore(&ha->hw_lock, flags);
 712
 713        if (mem_ptr)
 714                iounmap(mem_ptr);
 715        return ret;
 716}
 717
 718static int
 719qla82xx_pci_mem_write_direct(struct qla_hw_data *ha,
 720        u64 off, void *data, int size)
 721{
 722        unsigned long   flags;
 723        void  __iomem *addr = NULL;
 724        int             ret = 0;
 725        u64             start;
 726        uint8_t __iomem *mem_ptr = NULL;
 727        unsigned long   mem_base;
 728        unsigned long   mem_page;
 729        scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 730
 731        write_lock_irqsave(&ha->hw_lock, flags);
 732
 733        /*
 734         * If attempting to access unknown address or straddle hw windows,
 735         * do not access.
 736         */
 737        start = qla82xx_pci_set_window(ha, off);
 738        if ((start == -1UL) ||
 739                (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
 740                write_unlock_irqrestore(&ha->hw_lock, flags);
 741                ql_log(ql_log_fatal, vha, 0xb009,
 742                    "%s out of bound memory "
 743                    "access, offset is 0x%llx.\n",
 744                    QLA2XXX_DRIVER_NAME, off);
 745                return -1;
 746        }
 747
 748        write_unlock_irqrestore(&ha->hw_lock, flags);
 749        mem_base = pci_resource_start(ha->pdev, 0);
 750        mem_page = start & PAGE_MASK;
 751        /* Map two pages whenever user tries to access addresses in two
 752         * consecutive pages.
 753         */
 754        if (mem_page != ((start + size - 1) & PAGE_MASK))
 755                mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
 756        else
 757                mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
 758        if (mem_ptr == NULL)
 759                return -1;
 760
 761        addr = mem_ptr;
 762        addr += start & (PAGE_SIZE - 1);
 763        write_lock_irqsave(&ha->hw_lock, flags);
 764
 765        switch (size) {
 766        case 1:
 767                writeb(*(u8  *)data, addr);
 768                break;
 769        case 2:
 770                writew(*(u16 *)data, addr);
 771                break;
 772        case 4:
 773                writel(*(u32 *)data, addr);
 774                break;
 775        case 8:
 776                writeq(*(u64 *)data, addr);
 777                break;
 778        default:
 779                ret = -1;
 780                break;
 781        }
 782        write_unlock_irqrestore(&ha->hw_lock, flags);
 783        if (mem_ptr)
 784                iounmap(mem_ptr);
 785        return ret;
 786}
 787
 788#define MTU_FUDGE_FACTOR 100
 789static unsigned long
 790qla82xx_decode_crb_addr(unsigned long addr)
 791{
 792        int i;
 793        unsigned long base_addr, offset, pci_base;
 794
 795        if (!qla82xx_crb_table_initialized)
 796                qla82xx_crb_addr_transform_setup();
 797
 798        pci_base = ADDR_ERROR;
 799        base_addr = addr & 0xfff00000;
 800        offset = addr & 0x000fffff;
 801
 802        for (i = 0; i < MAX_CRB_XFORM; i++) {
 803                if (crb_addr_xform[i] == base_addr) {
 804                        pci_base = i << 20;
 805                        break;
 806                }
 807        }
 808        if (pci_base == ADDR_ERROR)
 809                return pci_base;
 810        return pci_base + offset;
 811}
 812
 813static long rom_max_timeout = 100;
 814static long qla82xx_rom_lock_timeout = 100;
 815
 816static int
 817qla82xx_rom_lock(struct qla_hw_data *ha)
 818{
 819        int done = 0, timeout = 0;
 820        uint32_t lock_owner = 0;
 821        scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 822
 823        while (!done) {
 824                /* acquire semaphore2 from PCI HW block */
 825                done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
 826                if (done == 1)
 827                        break;
 828                if (timeout >= qla82xx_rom_lock_timeout) {
 829                        lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
 830                        ql_dbg(ql_dbg_p3p, vha, 0xb157,
 831                            "%s: Simultaneous flash access by following ports, active port = %d: accessing port = %d",
 832                            __func__, ha->portnum, lock_owner);
 833                        return -1;
 834                }
 835                timeout++;
 836        }
 837        qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ha->portnum);
 838        return 0;
 839}
 840
 841static void
 842qla82xx_rom_unlock(struct qla_hw_data *ha)
 843{
 844        qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, 0xffffffff);
 845        qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
 846}
 847
 848static int
 849qla82xx_wait_rom_busy(struct qla_hw_data *ha)
 850{
 851        long timeout = 0;
 852        long done = 0 ;
 853        scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 854
 855        while (done == 0) {
 856                done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
 857                done &= 4;
 858                timeout++;
 859                if (timeout >= rom_max_timeout) {
 860                        ql_dbg(ql_dbg_p3p, vha, 0xb00a,
 861                            "%s: Timeout reached waiting for rom busy.\n",
 862                            QLA2XXX_DRIVER_NAME);
 863                        return -1;
 864                }
 865        }
 866        return 0;
 867}
 868
 869static int
 870qla82xx_wait_rom_done(struct qla_hw_data *ha)
 871{
 872        long timeout = 0;
 873        long done = 0 ;
 874        scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 875
 876        while (done == 0) {
 877                done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
 878                done &= 2;
 879                timeout++;
 880                if (timeout >= rom_max_timeout) {
 881                        ql_dbg(ql_dbg_p3p, vha, 0xb00b,
 882                            "%s: Timeout reached waiting for rom done.\n",
 883                            QLA2XXX_DRIVER_NAME);
 884                        return -1;
 885                }
 886        }
 887        return 0;
 888}
 889
 890static int
 891qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag)
 892{
 893        uint32_t  off_value, rval = 0;
 894
 895        wrt_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase, off & 0xFFFF0000);
 896
 897        /* Read back value to make sure write has gone through */
 898        rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase);
 899        off_value  = (off & 0x0000FFFF);
 900
 901        if (flag)
 902                wrt_reg_dword(off_value + CRB_INDIRECT_2M + ha->nx_pcibase,
 903                              data);
 904        else
 905                rval = rd_reg_dword(off_value + CRB_INDIRECT_2M +
 906                                    ha->nx_pcibase);
 907
 908        return rval;
 909}
 910
 911static int
 912qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
 913{
 914        /* Dword reads to flash. */
 915        qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1);
 916        *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE +
 917            (addr & 0x0000FFFF), 0, 0);
 918
 919        return 0;
 920}
 921
 922static int
 923qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
 924{
 925        int ret, loops = 0;
 926        uint32_t lock_owner = 0;
 927        scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 928
 929        while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
 930                udelay(100);
 931                schedule();
 932                loops++;
 933        }
 934        if (loops >= 50000) {
 935                lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
 936                ql_log(ql_log_fatal, vha, 0x00b9,
 937                    "Failed to acquire SEM2 lock, Lock Owner %u.\n",
 938                    lock_owner);
 939                return -1;
 940        }
 941        ret = qla82xx_do_rom_fast_read(ha, addr, valp);
 942        qla82xx_rom_unlock(ha);
 943        return ret;
 944}
 945
 946static int
 947qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val)
 948{
 949        scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 950
 951        qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR);
 952        qla82xx_wait_rom_busy(ha);
 953        if (qla82xx_wait_rom_done(ha)) {
 954                ql_log(ql_log_warn, vha, 0xb00c,
 955                    "Error waiting for rom done.\n");
 956                return -1;
 957        }
 958        *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
 959        return 0;
 960}
 961
 962static int
 963qla82xx_flash_wait_write_finish(struct qla_hw_data *ha)
 964{
 965        uint32_t val = 0;
 966        int i, ret;
 967        scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 968
 969        qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
 970        for (i = 0; i < 50000; i++) {
 971                ret = qla82xx_read_status_reg(ha, &val);
 972                if (ret < 0 || (val & 1) == 0)
 973                        return ret;
 974                udelay(10);
 975                cond_resched();
 976        }
 977        ql_log(ql_log_warn, vha, 0xb00d,
 978               "Timeout reached waiting for write finish.\n");
 979        return -1;
 980}
 981
 982static int
 983qla82xx_flash_set_write_enable(struct qla_hw_data *ha)
 984{
 985        uint32_t val;
 986
 987        qla82xx_wait_rom_busy(ha);
 988        qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
 989        qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN);
 990        qla82xx_wait_rom_busy(ha);
 991        if (qla82xx_wait_rom_done(ha))
 992                return -1;
 993        if (qla82xx_read_status_reg(ha, &val) != 0)
 994                return -1;
 995        if ((val & 2) != 2)
 996                return -1;
 997        return 0;
 998}
 999
1000static int
1001qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val)
1002{
1003        scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1004
1005        if (qla82xx_flash_set_write_enable(ha))
1006                return -1;
1007        qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val);
1008        qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1);
1009        if (qla82xx_wait_rom_done(ha)) {
1010                ql_log(ql_log_warn, vha, 0xb00e,
1011                    "Error waiting for rom done.\n");
1012                return -1;
1013        }
1014        return qla82xx_flash_wait_write_finish(ha);
1015}
1016
1017static int
1018qla82xx_write_disable_flash(struct qla_hw_data *ha)
1019{
1020        scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1021
1022        qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI);
1023        if (qla82xx_wait_rom_done(ha)) {
1024                ql_log(ql_log_warn, vha, 0xb00f,
1025                    "Error waiting for rom done.\n");
1026                return -1;
1027        }
1028        return 0;
1029}
1030
1031static int
1032ql82xx_rom_lock_d(struct qla_hw_data *ha)
1033{
1034        int loops = 0;
1035        uint32_t lock_owner = 0;
1036        scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1037
1038        while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
1039                udelay(100);
1040                cond_resched();
1041                loops++;
1042        }
1043        if (loops >= 50000) {
1044                lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
1045                ql_log(ql_log_warn, vha, 0xb010,
1046                    "ROM lock failed, Lock Owner %u.\n", lock_owner);
1047                return -1;
1048        }
1049        return 0;
1050}
1051
1052static int
1053qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr,
1054        uint32_t data)
1055{
1056        int ret = 0;
1057        scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1058
1059        ret = ql82xx_rom_lock_d(ha);
1060        if (ret < 0) {
1061                ql_log(ql_log_warn, vha, 0xb011,
1062                    "ROM lock failed.\n");
1063                return ret;
1064        }
1065
1066        ret = qla82xx_flash_set_write_enable(ha);
1067        if (ret < 0)
1068                goto done_write;
1069
1070        qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data);
1071        qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr);
1072        qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
1073        qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP);
1074        qla82xx_wait_rom_busy(ha);
1075        if (qla82xx_wait_rom_done(ha)) {
1076                ql_log(ql_log_warn, vha, 0xb012,
1077                    "Error waiting for rom done.\n");
1078                ret = -1;
1079                goto done_write;
1080        }
1081
1082        ret = qla82xx_flash_wait_write_finish(ha);
1083
1084done_write:
1085        qla82xx_rom_unlock(ha);
1086        return ret;
1087}
1088
1089/* This routine does CRB initialize sequence
1090 *  to put the ISP into operational state
1091 */
1092static int
1093qla82xx_pinit_from_rom(scsi_qla_host_t *vha)
1094{
1095        int addr, val;
1096        int i ;
1097        struct crb_addr_pair *buf;
1098        unsigned long off;
1099        unsigned offset, n;
1100        struct qla_hw_data *ha = vha->hw;
1101
1102        struct crb_addr_pair {
1103                long addr;
1104                long data;
1105        };
1106
1107        /* Halt all the individual PEGs and other blocks of the ISP */
1108        qla82xx_rom_lock(ha);
1109
1110        /* disable all I2Q */
1111        qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
1112        qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
1113        qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
1114        qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
1115        qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
1116        qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
1117
1118        /* disable all niu interrupts */
1119        qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
1120        /* disable xge rx/tx */
1121        qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
1122        /* disable xg1 rx/tx */
1123        qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
1124        /* disable sideband mac */
1125        qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
1126        /* disable ap0 mac */
1127        qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
1128        /* disable ap1 mac */
1129        qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
1130
1131        /* halt sre */
1132        val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1133        qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
1134
1135        /* halt epg */
1136        qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
1137
1138        /* halt timers */
1139        qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1140        qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1141        qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1142        qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1143        qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
1144        qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
1145
1146        /* halt pegs */
1147        qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1148        qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1149        qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1150        qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1151        qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
1152        msleep(20);
1153
1154        /* big hammer */
1155        if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
1156                /* don't reset CAM block on reset */
1157                qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1158        else
1159                qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
1160        qla82xx_rom_unlock(ha);
1161
1162        /* Read the signature value from the flash.
1163         * Offset 0: Contain signature (0xcafecafe)
1164         * Offset 4: Offset and number of addr/value pairs
1165         * that present in CRB initialize sequence
1166         */
1167        n = 0;
1168        if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1169            qla82xx_rom_fast_read(ha, 4, &n) != 0) {
1170                ql_log(ql_log_fatal, vha, 0x006e,
1171                    "Error Reading crb_init area: n: %08x.\n", n);
1172                return -1;
1173        }
1174
1175        /* Offset in flash = lower 16 bits
1176         * Number of entries = upper 16 bits
1177         */
1178        offset = n & 0xffffU;
1179        n = (n >> 16) & 0xffffU;
1180
1181        /* number of addr/value pair should not exceed 1024 entries */
1182        if (n  >= 1024) {
1183                ql_log(ql_log_fatal, vha, 0x0071,
1184                    "Card flash not initialized:n=0x%x.\n", n);
1185                return -1;
1186        }
1187
1188        ql_log(ql_log_info, vha, 0x0072,
1189            "%d CRB init values found in ROM.\n", n);
1190
1191        buf = kmalloc_array(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
1192        if (buf == NULL) {
1193                ql_log(ql_log_fatal, vha, 0x010c,
1194                    "Unable to allocate memory.\n");
1195                return -ENOMEM;
1196        }
1197
1198        for (i = 0; i < n; i++) {
1199                if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1200                    qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) {
1201                        kfree(buf);
1202                        return -1;
1203                }
1204
1205                buf[i].addr = addr;
1206                buf[i].data = val;
1207        }
1208
1209        for (i = 0; i < n; i++) {
1210                /* Translate internal CRB initialization
1211                 * address to PCI bus address
1212                 */
1213                off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) +
1214                    QLA82XX_PCI_CRBSPACE;
1215                /* Not all CRB  addr/value pair to be written,
1216                 * some of them are skipped
1217                 */
1218
1219                /* skipping cold reboot MAGIC */
1220                if (off == QLA82XX_CAM_RAM(0x1fc))
1221                        continue;
1222
1223                /* do not reset PCI */
1224                if (off == (ROMUSB_GLB + 0xbc))
1225                        continue;
1226
1227                /* skip core clock, so that firmware can increase the clock */
1228                if (off == (ROMUSB_GLB + 0xc8))
1229                        continue;
1230
1231                /* skip the function enable register */
1232                if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1233                        continue;
1234
1235                if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1236                        continue;
1237
1238                if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1239                        continue;
1240
1241                if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1242                        continue;
1243
1244                if (off == ADDR_ERROR) {
1245                        ql_log(ql_log_fatal, vha, 0x0116,
1246                            "Unknown addr: 0x%08lx.\n", buf[i].addr);
1247                        continue;
1248                }
1249
1250                qla82xx_wr_32(ha, off, buf[i].data);
1251
1252                /* ISP requires much bigger delay to settle down,
1253                 * else crb_window returns 0xffffffff
1254                 */
1255                if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1256                        msleep(1000);
1257
1258                /* ISP requires millisec delay between
1259                 * successive CRB register updation
1260                 */
1261                msleep(1);
1262        }
1263
1264        kfree(buf);
1265
1266        /* Resetting the data and instruction cache */
1267        qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1268        qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1269        qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1270
1271        /* Clear all protocol processing engines */
1272        qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1273        qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1274        qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1275        qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1276        qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1277        qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1278        qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1279        qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1280        return 0;
1281}
1282
1283static int
1284qla82xx_pci_mem_write_2M(struct qla_hw_data *ha,
1285                u64 off, void *data, int size)
1286{
1287        int i, j, ret = 0, loop, sz[2], off0;
1288        int scale, shift_amount, startword;
1289        uint32_t temp;
1290        uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1291
1292        /*
1293         * If not MN, go check for MS or invalid.
1294         */
1295        if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1296                mem_crb = QLA82XX_CRB_QDR_NET;
1297        else {
1298                mem_crb = QLA82XX_CRB_DDR_NET;
1299                if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1300                        return qla82xx_pci_mem_write_direct(ha,
1301                            off, data, size);
1302        }
1303
1304        off0 = off & 0x7;
1305        sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1306        sz[1] = size - sz[0];
1307
1308        off8 = off & 0xfffffff0;
1309        loop = (((off & 0xf) + size - 1) >> 4) + 1;
1310        shift_amount = 4;
1311        scale = 2;
1312        startword = (off & 0xf)/8;
1313
1314        for (i = 0; i < loop; i++) {
1315                if (qla82xx_pci_mem_read_2M(ha, off8 +
1316                    (i << shift_amount), &word[i * scale], 8))
1317                        return -1;
1318        }
1319
1320        switch (size) {
1321        case 1:
1322                tmpw = *((uint8_t *)data);
1323                break;
1324        case 2:
1325                tmpw = *((uint16_t *)data);
1326                break;
1327        case 4:
1328                tmpw = *((uint32_t *)data);
1329                break;
1330        case 8:
1331        default:
1332                tmpw = *((uint64_t *)data);
1333                break;
1334        }
1335
1336        if (sz[0] == 8) {
1337                word[startword] = tmpw;
1338        } else {
1339                word[startword] &=
1340                        ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1341                word[startword] |= tmpw << (off0 * 8);
1342        }
1343        if (sz[1] != 0) {
1344                word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1345                word[startword+1] |= tmpw >> (sz[0] * 8);
1346        }
1347
1348        for (i = 0; i < loop; i++) {
1349                temp = off8 + (i << shift_amount);
1350                qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1351                temp = 0;
1352                qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1353                temp = word[i * scale] & 0xffffffff;
1354                qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1355                temp = (word[i * scale] >> 32) & 0xffffffff;
1356                qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1357                temp = word[i*scale + 1] & 0xffffffff;
1358                qla82xx_wr_32(ha, mem_crb +
1359                    MIU_TEST_AGT_WRDATA_UPPER_LO, temp);
1360                temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1361                qla82xx_wr_32(ha, mem_crb +
1362                    MIU_TEST_AGT_WRDATA_UPPER_HI, temp);
1363
1364                temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1365                qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1366                temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1367                qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1368
1369                for (j = 0; j < MAX_CTL_CHECK; j++) {
1370                        temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1371                        if ((temp & MIU_TA_CTL_BUSY) == 0)
1372                                break;
1373                }
1374
1375                if (j >= MAX_CTL_CHECK) {
1376                        if (printk_ratelimit())
1377                                dev_err(&ha->pdev->dev,
1378                                    "failed to write through agent.\n");
1379                        ret = -1;
1380                        break;
1381                }
1382        }
1383
1384        return ret;
1385}
1386
1387static int
1388qla82xx_fw_load_from_flash(struct qla_hw_data *ha)
1389{
1390        int  i;
1391        long size = 0;
1392        long flashaddr = ha->flt_region_bootload << 2;
1393        long memaddr = BOOTLD_START;
1394        u64 data;
1395        u32 high, low;
1396
1397        size = (IMAGE_START - BOOTLD_START) / 8;
1398
1399        for (i = 0; i < size; i++) {
1400                if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1401                    (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) {
1402                        return -1;
1403                }
1404                data = ((u64)high << 32) | low ;
1405                qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
1406                flashaddr += 8;
1407                memaddr += 8;
1408
1409                if (i % 0x1000 == 0)
1410                        msleep(1);
1411        }
1412        udelay(100);
1413        read_lock(&ha->hw_lock);
1414        qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1415        qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1416        read_unlock(&ha->hw_lock);
1417        return 0;
1418}
1419
1420int
1421qla82xx_pci_mem_read_2M(struct qla_hw_data *ha,
1422                u64 off, void *data, int size)
1423{
1424        int i, j = 0, k, start, end, loop, sz[2], off0[2];
1425        int           shift_amount;
1426        uint32_t      temp;
1427        uint64_t      off8, val, mem_crb, word[2] = {0, 0};
1428
1429        /*
1430         * If not MN, go check for MS or invalid.
1431         */
1432
1433        if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1434                mem_crb = QLA82XX_CRB_QDR_NET;
1435        else {
1436                mem_crb = QLA82XX_CRB_DDR_NET;
1437                if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1438                        return qla82xx_pci_mem_read_direct(ha,
1439                            off, data, size);
1440        }
1441
1442        off8 = off & 0xfffffff0;
1443        off0[0] = off & 0xf;
1444        sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1445        shift_amount = 4;
1446        loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1447        off0[1] = 0;
1448        sz[1] = size - sz[0];
1449
1450        for (i = 0; i < loop; i++) {
1451                temp = off8 + (i << shift_amount);
1452                qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1453                temp = 0;
1454                qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1455                temp = MIU_TA_CTL_ENABLE;
1456                qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1457                temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1458                qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1459
1460                for (j = 0; j < MAX_CTL_CHECK; j++) {
1461                        temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1462                        if ((temp & MIU_TA_CTL_BUSY) == 0)
1463                                break;
1464                }
1465
1466                if (j >= MAX_CTL_CHECK) {
1467                        if (printk_ratelimit())
1468                                dev_err(&ha->pdev->dev,
1469                                    "failed to read through agent.\n");
1470                        break;
1471                }
1472
1473                start = off0[i] >> 2;
1474                end   = (off0[i] + sz[i] - 1) >> 2;
1475                for (k = start; k <= end; k++) {
1476                        temp = qla82xx_rd_32(ha,
1477                                        mem_crb + MIU_TEST_AGT_RDDATA(k));
1478                        word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1479                }
1480        }
1481
1482        if (j >= MAX_CTL_CHECK)
1483                return -1;
1484
1485        if ((off0[0] & 7) == 0) {
1486                val = word[0];
1487        } else {
1488                val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1489                        ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1490        }
1491
1492        switch (size) {
1493        case 1:
1494                *(uint8_t  *)data = val;
1495                break;
1496        case 2:
1497                *(uint16_t *)data = val;
1498                break;
1499        case 4:
1500                *(uint32_t *)data = val;
1501                break;
1502        case 8:
1503                *(uint64_t *)data = val;
1504                break;
1505        }
1506        return 0;
1507}
1508
1509
1510static struct qla82xx_uri_table_desc *
1511qla82xx_get_table_desc(const u8 *unirom, int section)
1512{
1513        uint32_t i;
1514        struct qla82xx_uri_table_desc *directory =
1515                (struct qla82xx_uri_table_desc *)&unirom[0];
1516        uint32_t offset;
1517        uint32_t tab_type;
1518        uint32_t entries = le32_to_cpu(directory->num_entries);
1519
1520        for (i = 0; i < entries; i++) {
1521                offset = le32_to_cpu(directory->findex) +
1522                    (i * le32_to_cpu(directory->entry_size));
1523                tab_type = get_unaligned_le32((u32 *)&unirom[offset] + 8);
1524
1525                if (tab_type == section)
1526                        return (struct qla82xx_uri_table_desc *)&unirom[offset];
1527        }
1528
1529        return NULL;
1530}
1531
1532static struct qla82xx_uri_data_desc *
1533qla82xx_get_data_desc(struct qla_hw_data *ha,
1534        u32 section, u32 idx_offset)
1535{
1536        const u8 *unirom = ha->hablob->fw->data;
1537        int idx = get_unaligned_le32((u32 *)&unirom[ha->file_prd_off] +
1538                                     idx_offset);
1539        struct qla82xx_uri_table_desc *tab_desc = NULL;
1540        uint32_t offset;
1541
1542        tab_desc = qla82xx_get_table_desc(unirom, section);
1543        if (!tab_desc)
1544                return NULL;
1545
1546        offset = le32_to_cpu(tab_desc->findex) +
1547            (le32_to_cpu(tab_desc->entry_size) * idx);
1548
1549        return (struct qla82xx_uri_data_desc *)&unirom[offset];
1550}
1551
1552static u8 *
1553qla82xx_get_bootld_offset(struct qla_hw_data *ha)
1554{
1555        u32 offset = BOOTLD_START;
1556        struct qla82xx_uri_data_desc *uri_desc = NULL;
1557
1558        if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1559                uri_desc = qla82xx_get_data_desc(ha,
1560                    QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF);
1561                if (uri_desc)
1562                        offset = le32_to_cpu(uri_desc->findex);
1563        }
1564
1565        return (u8 *)&ha->hablob->fw->data[offset];
1566}
1567
1568static u32 qla82xx_get_fw_size(struct qla_hw_data *ha)
1569{
1570        struct qla82xx_uri_data_desc *uri_desc = NULL;
1571
1572        if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1573                uri_desc =  qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1574                    QLA82XX_URI_FIRMWARE_IDX_OFF);
1575                if (uri_desc)
1576                        return le32_to_cpu(uri_desc->size);
1577        }
1578
1579        return get_unaligned_le32(&ha->hablob->fw->data[FW_SIZE_OFFSET]);
1580}
1581
1582static u8 *
1583qla82xx_get_fw_offs(struct qla_hw_data *ha)
1584{
1585        u32 offset = IMAGE_START;
1586        struct qla82xx_uri_data_desc *uri_desc = NULL;
1587
1588        if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1589                uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1590                        QLA82XX_URI_FIRMWARE_IDX_OFF);
1591                if (uri_desc)
1592                        offset = le32_to_cpu(uri_desc->findex);
1593        }
1594
1595        return (u8 *)&ha->hablob->fw->data[offset];
1596}
1597
1598/* PCI related functions */
1599int qla82xx_pci_region_offset(struct pci_dev *pdev, int region)
1600{
1601        unsigned long val = 0;
1602        u32 control;
1603
1604        switch (region) {
1605        case 0:
1606                val = 0;
1607                break;
1608        case 1:
1609                pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control);
1610                val = control + QLA82XX_MSIX_TBL_SPACE;
1611                break;
1612        }
1613        return val;
1614}
1615
1616
1617int
1618qla82xx_iospace_config(struct qla_hw_data *ha)
1619{
1620        uint32_t len = 0;
1621
1622        if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) {
1623                ql_log_pci(ql_log_fatal, ha->pdev, 0x000c,
1624                    "Failed to reserver selected regions.\n");
1625                goto iospace_error_exit;
1626        }
1627
1628        /* Use MMIO operations for all accesses. */
1629        if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1630                ql_log_pci(ql_log_fatal, ha->pdev, 0x000d,
1631                    "Region #0 not an MMIO resource, aborting.\n");
1632                goto iospace_error_exit;
1633        }
1634
1635        len = pci_resource_len(ha->pdev, 0);
1636        ha->nx_pcibase = ioremap(pci_resource_start(ha->pdev, 0), len);
1637        if (!ha->nx_pcibase) {
1638                ql_log_pci(ql_log_fatal, ha->pdev, 0x000e,
1639                    "Cannot remap pcibase MMIO, aborting.\n");
1640                goto iospace_error_exit;
1641        }
1642
1643        /* Mapping of IO base pointer */
1644        if (IS_QLA8044(ha)) {
1645                ha->iobase = ha->nx_pcibase;
1646        } else if (IS_QLA82XX(ha)) {
1647                ha->iobase = ha->nx_pcibase + 0xbc000 + (ha->pdev->devfn << 11);
1648        }
1649
1650        if (!ql2xdbwr) {
1651                ha->nxdb_wr_ptr = ioremap((pci_resource_start(ha->pdev, 4) +
1652                    (ha->pdev->devfn << 12)), 4);
1653                if (!ha->nxdb_wr_ptr) {
1654                        ql_log_pci(ql_log_fatal, ha->pdev, 0x000f,
1655                            "Cannot remap MMIO, aborting.\n");
1656                        goto iospace_error_exit;
1657                }
1658
1659                /* Mapping of IO base pointer,
1660                 * door bell read and write pointer
1661                 */
1662                ha->nxdb_rd_ptr = ha->nx_pcibase + (512 * 1024) +
1663                    (ha->pdev->devfn * 8);
1664        } else {
1665                ha->nxdb_wr_ptr = (void __iomem *)(ha->pdev->devfn == 6 ?
1666                        QLA82XX_CAMRAM_DB1 :
1667                        QLA82XX_CAMRAM_DB2);
1668        }
1669
1670        ha->max_req_queues = ha->max_rsp_queues = 1;
1671        ha->msix_count = ha->max_rsp_queues + 1;
1672        ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006,
1673            "nx_pci_base=%p iobase=%p "
1674            "max_req_queues=%d msix_count=%d.\n",
1675            ha->nx_pcibase, ha->iobase,
1676            ha->max_req_queues, ha->msix_count);
1677        ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010,
1678            "nx_pci_base=%p iobase=%p "
1679            "max_req_queues=%d msix_count=%d.\n",
1680            ha->nx_pcibase, ha->iobase,
1681            ha->max_req_queues, ha->msix_count);
1682        return 0;
1683
1684iospace_error_exit:
1685        return -ENOMEM;
1686}
1687
1688/* GS related functions */
1689
1690/* Initialization related functions */
1691
1692/**
1693 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers.
1694 * @vha: HA context
1695 *
1696 * Returns 0 on success.
1697*/
1698int
1699qla82xx_pci_config(scsi_qla_host_t *vha)
1700{
1701        struct qla_hw_data *ha = vha->hw;
1702        int ret;
1703
1704        pci_set_master(ha->pdev);
1705        ret = pci_set_mwi(ha->pdev);
1706        ha->chip_revision = ha->pdev->revision;
1707        ql_dbg(ql_dbg_init, vha, 0x0043,
1708            "Chip revision:%d; pci_set_mwi() returned %d.\n",
1709            ha->chip_revision, ret);
1710        return 0;
1711}
1712
1713/**
1714 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers.
1715 * @vha: HA context
1716 *
1717 * Returns 0 on success.
1718 */
1719int
1720qla82xx_reset_chip(scsi_qla_host_t *vha)
1721{
1722        struct qla_hw_data *ha = vha->hw;
1723
1724        ha->isp_ops->disable_intrs(ha);
1725
1726        return QLA_SUCCESS;
1727}
1728
1729void qla82xx_config_rings(struct scsi_qla_host *vha)
1730{
1731        struct qla_hw_data *ha = vha->hw;
1732        struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1733        struct init_cb_81xx *icb;
1734        struct req_que *req = ha->req_q_map[0];
1735        struct rsp_que *rsp = ha->rsp_q_map[0];
1736
1737        /* Setup ring parameters in initialization control block. */
1738        icb = (struct init_cb_81xx *)ha->init_cb;
1739        icb->request_q_outpointer = cpu_to_le16(0);
1740        icb->response_q_inpointer = cpu_to_le16(0);
1741        icb->request_q_length = cpu_to_le16(req->length);
1742        icb->response_q_length = cpu_to_le16(rsp->length);
1743        put_unaligned_le64(req->dma, &icb->request_q_address);
1744        put_unaligned_le64(rsp->dma, &icb->response_q_address);
1745
1746        wrt_reg_dword(&reg->req_q_out[0], 0);
1747        wrt_reg_dword(&reg->rsp_q_in[0], 0);
1748        wrt_reg_dword(&reg->rsp_q_out[0], 0);
1749}
1750
1751static int
1752qla82xx_fw_load_from_blob(struct qla_hw_data *ha)
1753{
1754        u64 *ptr64;
1755        u32 i, flashaddr, size;
1756        __le64 data;
1757
1758        size = (IMAGE_START - BOOTLD_START) / 8;
1759
1760        ptr64 = (u64 *)qla82xx_get_bootld_offset(ha);
1761        flashaddr = BOOTLD_START;
1762
1763        for (i = 0; i < size; i++) {
1764                data = cpu_to_le64(ptr64[i]);
1765                if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1766                        return -EIO;
1767                flashaddr += 8;
1768        }
1769
1770        flashaddr = FLASH_ADDR_START;
1771        size = qla82xx_get_fw_size(ha) / 8;
1772        ptr64 = (u64 *)qla82xx_get_fw_offs(ha);
1773
1774        for (i = 0; i < size; i++) {
1775                data = cpu_to_le64(ptr64[i]);
1776
1777                if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1778                        return -EIO;
1779                flashaddr += 8;
1780        }
1781        udelay(100);
1782
1783        /* Write a magic value to CAMRAM register
1784         * at a specified offset to indicate
1785         * that all data is written and
1786         * ready for firmware to initialize.
1787         */
1788        qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC);
1789
1790        read_lock(&ha->hw_lock);
1791        qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1792        qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1793        read_unlock(&ha->hw_lock);
1794        return 0;
1795}
1796
1797static int
1798qla82xx_set_product_offset(struct qla_hw_data *ha)
1799{
1800        struct qla82xx_uri_table_desc *ptab_desc = NULL;
1801        const uint8_t *unirom = ha->hablob->fw->data;
1802        uint32_t i;
1803        uint32_t entries;
1804        uint32_t flags, file_chiprev, offset;
1805        uint8_t chiprev = ha->chip_revision;
1806        /* Hardcoding mn_present flag for P3P */
1807        int mn_present = 0;
1808        uint32_t flagbit;
1809
1810        ptab_desc = qla82xx_get_table_desc(unirom,
1811                 QLA82XX_URI_DIR_SECT_PRODUCT_TBL);
1812        if (!ptab_desc)
1813                return -1;
1814
1815        entries = le32_to_cpu(ptab_desc->num_entries);
1816
1817        for (i = 0; i < entries; i++) {
1818                offset = le32_to_cpu(ptab_desc->findex) +
1819                        (i * le32_to_cpu(ptab_desc->entry_size));
1820                flags = le32_to_cpu(*((__le32 *)&unirom[offset] +
1821                        QLA82XX_URI_FLAGS_OFF));
1822                file_chiprev = le32_to_cpu(*((__le32 *)&unirom[offset] +
1823                        QLA82XX_URI_CHIP_REV_OFF));
1824
1825                flagbit = mn_present ? 1 : 2;
1826
1827                if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) {
1828                        ha->file_prd_off = offset;
1829                        return 0;
1830                }
1831        }
1832        return -1;
1833}
1834
1835static int
1836qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type)
1837{
1838        uint32_t val;
1839        uint32_t min_size;
1840        struct qla_hw_data *ha = vha->hw;
1841        const struct firmware *fw = ha->hablob->fw;
1842
1843        ha->fw_type = fw_type;
1844
1845        if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1846                if (qla82xx_set_product_offset(ha))
1847                        return -EINVAL;
1848
1849                min_size = QLA82XX_URI_FW_MIN_SIZE;
1850        } else {
1851                val = get_unaligned_le32(&fw->data[QLA82XX_FW_MAGIC_OFFSET]);
1852                if (val != QLA82XX_BDINFO_MAGIC)
1853                        return -EINVAL;
1854
1855                min_size = QLA82XX_FW_MIN_SIZE;
1856        }
1857
1858        if (fw->size < min_size)
1859                return -EINVAL;
1860        return 0;
1861}
1862
1863static int
1864qla82xx_check_cmdpeg_state(struct qla_hw_data *ha)
1865{
1866        u32 val = 0;
1867        int retries = 60;
1868        scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1869
1870        do {
1871                read_lock(&ha->hw_lock);
1872                val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE);
1873                read_unlock(&ha->hw_lock);
1874
1875                switch (val) {
1876                case PHAN_INITIALIZE_COMPLETE:
1877                case PHAN_INITIALIZE_ACK:
1878                        return QLA_SUCCESS;
1879                case PHAN_INITIALIZE_FAILED:
1880                        break;
1881                default:
1882                        break;
1883                }
1884                ql_log(ql_log_info, vha, 0x00a8,
1885                    "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n",
1886                    val, retries);
1887
1888                msleep(500);
1889
1890        } while (--retries);
1891
1892        ql_log(ql_log_fatal, vha, 0x00a9,
1893            "Cmd Peg initialization failed: 0x%x.\n", val);
1894
1895        val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1896        read_lock(&ha->hw_lock);
1897        qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
1898        read_unlock(&ha->hw_lock);
1899        return QLA_FUNCTION_FAILED;
1900}
1901
1902static int
1903qla82xx_check_rcvpeg_state(struct qla_hw_data *ha)
1904{
1905        u32 val = 0;
1906        int retries = 60;
1907        scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1908
1909        do {
1910                read_lock(&ha->hw_lock);
1911                val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE);
1912                read_unlock(&ha->hw_lock);
1913
1914                switch (val) {
1915                case PHAN_INITIALIZE_COMPLETE:
1916                case PHAN_INITIALIZE_ACK:
1917                        return QLA_SUCCESS;
1918                case PHAN_INITIALIZE_FAILED:
1919                        break;
1920                default:
1921                        break;
1922                }
1923                ql_log(ql_log_info, vha, 0x00ab,
1924                    "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n",
1925                    val, retries);
1926
1927                msleep(500);
1928
1929        } while (--retries);
1930
1931        ql_log(ql_log_fatal, vha, 0x00ac,
1932            "Rcv Peg initialization failed: 0x%x.\n", val);
1933        read_lock(&ha->hw_lock);
1934        qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED);
1935        read_unlock(&ha->hw_lock);
1936        return QLA_FUNCTION_FAILED;
1937}
1938
1939/* ISR related functions */
1940static struct qla82xx_legacy_intr_set legacy_intr[] =
1941        QLA82XX_LEGACY_INTR_CONFIG;
1942
1943/*
1944 * qla82xx_mbx_completion() - Process mailbox command completions.
1945 * @ha: SCSI driver HA context
1946 * @mb0: Mailbox0 register
1947 */
1948void
1949qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
1950{
1951        uint16_t        cnt;
1952        __le16 __iomem *wptr;
1953        struct qla_hw_data *ha = vha->hw;
1954        struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1955
1956        wptr = &reg->mailbox_out[1];
1957
1958        /* Load return mailbox registers. */
1959        ha->flags.mbox_int = 1;
1960        ha->mailbox_out[0] = mb0;
1961
1962        for (cnt = 1; cnt < ha->mbx_count; cnt++) {
1963                ha->mailbox_out[cnt] = rd_reg_word(wptr);
1964                wptr++;
1965        }
1966
1967        if (!ha->mcp)
1968                ql_dbg(ql_dbg_async, vha, 0x5053,
1969                    "MBX pointer ERROR.\n");
1970}
1971
1972/**
1973 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
1974 * @irq: interrupt number
1975 * @dev_id: SCSI driver HA context
1976 *
1977 * Called by system whenever the host adapter generates an interrupt.
1978 *
1979 * Returns handled flag.
1980 */
1981irqreturn_t
1982qla82xx_intr_handler(int irq, void *dev_id)
1983{
1984        scsi_qla_host_t *vha;
1985        struct qla_hw_data *ha;
1986        struct rsp_que *rsp;
1987        struct device_reg_82xx __iomem *reg;
1988        int status = 0, status1 = 0;
1989        unsigned long   flags;
1990        unsigned long   iter;
1991        uint32_t        stat = 0;
1992        uint16_t        mb[8];
1993
1994        rsp = (struct rsp_que *) dev_id;
1995        if (!rsp) {
1996                ql_log(ql_log_info, NULL, 0xb053,
1997                    "%s: NULL response queue pointer.\n", __func__);
1998                return IRQ_NONE;
1999        }
2000        ha = rsp->hw;
2001
2002        if (!ha->flags.msi_enabled) {
2003                status = qla82xx_rd_32(ha, ISR_INT_VECTOR);
2004                if (!(status & ha->nx_legacy_intr.int_vec_bit))
2005                        return IRQ_NONE;
2006
2007                status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG);
2008                if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1))
2009                        return IRQ_NONE;
2010        }
2011
2012        /* clear the interrupt */
2013        qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff);
2014
2015        /* read twice to ensure write is flushed */
2016        qla82xx_rd_32(ha, ISR_INT_VECTOR);
2017        qla82xx_rd_32(ha, ISR_INT_VECTOR);
2018
2019        reg = &ha->iobase->isp82;
2020
2021        spin_lock_irqsave(&ha->hardware_lock, flags);
2022        vha = pci_get_drvdata(ha->pdev);
2023        for (iter = 1; iter--; ) {
2024
2025                if (rd_reg_dword(&reg->host_int)) {
2026                        stat = rd_reg_dword(&reg->host_status);
2027
2028                        switch (stat & 0xff) {
2029                        case 0x1:
2030                        case 0x2:
2031                        case 0x10:
2032                        case 0x11:
2033                                qla82xx_mbx_completion(vha, MSW(stat));
2034                                status |= MBX_INTERRUPT;
2035                                break;
2036                        case 0x12:
2037                                mb[0] = MSW(stat);
2038                                mb[1] = rd_reg_word(&reg->mailbox_out[1]);
2039                                mb[2] = rd_reg_word(&reg->mailbox_out[2]);
2040                                mb[3] = rd_reg_word(&reg->mailbox_out[3]);
2041                                qla2x00_async_event(vha, rsp, mb);
2042                                break;
2043                        case 0x13:
2044                                qla24xx_process_response_queue(vha, rsp);
2045                                break;
2046                        default:
2047                                ql_dbg(ql_dbg_async, vha, 0x5054,
2048                                    "Unrecognized interrupt type (%d).\n",
2049                                    stat & 0xff);
2050                                break;
2051                        }
2052                }
2053                wrt_reg_dword(&reg->host_int, 0);
2054        }
2055
2056        qla2x00_handle_mbx_completion(ha, status);
2057        spin_unlock_irqrestore(&ha->hardware_lock, flags);
2058
2059        if (!ha->flags.msi_enabled)
2060                qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2061
2062        return IRQ_HANDLED;
2063}
2064
2065irqreturn_t
2066qla82xx_msix_default(int irq, void *dev_id)
2067{
2068        scsi_qla_host_t *vha;
2069        struct qla_hw_data *ha;
2070        struct rsp_que *rsp;
2071        struct device_reg_82xx __iomem *reg;
2072        int status = 0;
2073        unsigned long flags;
2074        uint32_t stat = 0;
2075        uint32_t host_int = 0;
2076        uint16_t mb[8];
2077
2078        rsp = (struct rsp_que *) dev_id;
2079        if (!rsp) {
2080                printk(KERN_INFO
2081                        "%s(): NULL response queue pointer.\n", __func__);
2082                return IRQ_NONE;
2083        }
2084        ha = rsp->hw;
2085
2086        reg = &ha->iobase->isp82;
2087
2088        spin_lock_irqsave(&ha->hardware_lock, flags);
2089        vha = pci_get_drvdata(ha->pdev);
2090        do {
2091                host_int = rd_reg_dword(&reg->host_int);
2092                if (qla2x00_check_reg32_for_disconnect(vha, host_int))
2093                        break;
2094                if (host_int) {
2095                        stat = rd_reg_dword(&reg->host_status);
2096
2097                        switch (stat & 0xff) {
2098                        case 0x1:
2099                        case 0x2:
2100                        case 0x10:
2101                        case 0x11:
2102                                qla82xx_mbx_completion(vha, MSW(stat));
2103                                status |= MBX_INTERRUPT;
2104                                break;
2105                        case 0x12:
2106                                mb[0] = MSW(stat);
2107                                mb[1] = rd_reg_word(&reg->mailbox_out[1]);
2108                                mb[2] = rd_reg_word(&reg->mailbox_out[2]);
2109                                mb[3] = rd_reg_word(&reg->mailbox_out[3]);
2110                                qla2x00_async_event(vha, rsp, mb);
2111                                break;
2112                        case 0x13:
2113                                qla24xx_process_response_queue(vha, rsp);
2114                                break;
2115                        default:
2116                                ql_dbg(ql_dbg_async, vha, 0x5041,
2117                                    "Unrecognized interrupt type (%d).\n",
2118                                    stat & 0xff);
2119                                break;
2120                        }
2121                }
2122                wrt_reg_dword(&reg->host_int, 0);
2123        } while (0);
2124
2125        qla2x00_handle_mbx_completion(ha, status);
2126        spin_unlock_irqrestore(&ha->hardware_lock, flags);
2127
2128        return IRQ_HANDLED;
2129}
2130
2131irqreturn_t
2132qla82xx_msix_rsp_q(int irq, void *dev_id)
2133{
2134        scsi_qla_host_t *vha;
2135        struct qla_hw_data *ha;
2136        struct rsp_que *rsp;
2137        struct device_reg_82xx __iomem *reg;
2138        unsigned long flags;
2139        uint32_t host_int = 0;
2140
2141        rsp = (struct rsp_que *) dev_id;
2142        if (!rsp) {
2143                printk(KERN_INFO
2144                        "%s(): NULL response queue pointer.\n", __func__);
2145                return IRQ_NONE;
2146        }
2147
2148        ha = rsp->hw;
2149        reg = &ha->iobase->isp82;
2150        spin_lock_irqsave(&ha->hardware_lock, flags);
2151        vha = pci_get_drvdata(ha->pdev);
2152        host_int = rd_reg_dword(&reg->host_int);
2153        if (qla2x00_check_reg32_for_disconnect(vha, host_int))
2154                goto out;
2155        qla24xx_process_response_queue(vha, rsp);
2156        wrt_reg_dword(&reg->host_int, 0);
2157out:
2158        spin_unlock_irqrestore(&ha->hardware_lock, flags);
2159        return IRQ_HANDLED;
2160}
2161
2162void
2163qla82xx_poll(int irq, void *dev_id)
2164{
2165        scsi_qla_host_t *vha;
2166        struct qla_hw_data *ha;
2167        struct rsp_que *rsp;
2168        struct device_reg_82xx __iomem *reg;
2169        int status = 0;
2170        uint32_t stat;
2171        uint32_t host_int = 0;
2172        uint16_t mb[8];
2173        unsigned long flags;
2174
2175        rsp = (struct rsp_que *) dev_id;
2176        if (!rsp) {
2177                printk(KERN_INFO
2178                        "%s(): NULL response queue pointer.\n", __func__);
2179                return;
2180        }
2181        ha = rsp->hw;
2182
2183        reg = &ha->iobase->isp82;
2184        spin_lock_irqsave(&ha->hardware_lock, flags);
2185        vha = pci_get_drvdata(ha->pdev);
2186
2187        host_int = rd_reg_dword(&reg->host_int);
2188        if (qla2x00_check_reg32_for_disconnect(vha, host_int))
2189                goto out;
2190        if (host_int) {
2191                stat = rd_reg_dword(&reg->host_status);
2192                switch (stat & 0xff) {
2193                case 0x1:
2194                case 0x2:
2195                case 0x10:
2196                case 0x11:
2197                        qla82xx_mbx_completion(vha, MSW(stat));
2198                        status |= MBX_INTERRUPT;
2199                        break;
2200                case 0x12:
2201                        mb[0] = MSW(stat);
2202                        mb[1] = rd_reg_word(&reg->mailbox_out[1]);
2203                        mb[2] = rd_reg_word(&reg->mailbox_out[2]);
2204                        mb[3] = rd_reg_word(&reg->mailbox_out[3]);
2205                        qla2x00_async_event(vha, rsp, mb);
2206                        break;
2207                case 0x13:
2208                        qla24xx_process_response_queue(vha, rsp);
2209                        break;
2210                default:
2211                        ql_dbg(ql_dbg_p3p, vha, 0xb013,
2212                            "Unrecognized interrupt type (%d).\n",
2213                            stat * 0xff);
2214                        break;
2215                }
2216                wrt_reg_dword(&reg->host_int, 0);
2217        }
2218out:
2219        spin_unlock_irqrestore(&ha->hardware_lock, flags);
2220}
2221
2222void
2223qla82xx_enable_intrs(struct qla_hw_data *ha)
2224{
2225        scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2226
2227        qla82xx_mbx_intr_enable(vha);
2228        spin_lock_irq(&ha->hardware_lock);
2229        if (IS_QLA8044(ha))
2230                qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 0);
2231        else
2232                qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2233        spin_unlock_irq(&ha->hardware_lock);
2234        ha->interrupts_on = 1;
2235}
2236
2237void
2238qla82xx_disable_intrs(struct qla_hw_data *ha)
2239{
2240        scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2241
2242        if (ha->interrupts_on)
2243                qla82xx_mbx_intr_disable(vha);
2244
2245        spin_lock_irq(&ha->hardware_lock);
2246        if (IS_QLA8044(ha))
2247                qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 1);
2248        else
2249                qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
2250        spin_unlock_irq(&ha->hardware_lock);
2251        ha->interrupts_on = 0;
2252}
2253
2254void qla82xx_init_flags(struct qla_hw_data *ha)
2255{
2256        struct qla82xx_legacy_intr_set *nx_legacy_intr;
2257
2258        /* ISP 8021 initializations */
2259        rwlock_init(&ha->hw_lock);
2260        ha->qdr_sn_window = -1;
2261        ha->ddr_mn_window = -1;
2262        ha->curr_window = 255;
2263        ha->portnum = PCI_FUNC(ha->pdev->devfn);
2264        nx_legacy_intr = &legacy_intr[ha->portnum];
2265        ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit;
2266        ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg;
2267        ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg;
2268        ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg;
2269}
2270
2271static inline void
2272qla82xx_set_idc_version(scsi_qla_host_t *vha)
2273{
2274        int idc_ver;
2275        uint32_t drv_active;
2276        struct qla_hw_data *ha = vha->hw;
2277
2278        drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2279        if (drv_active == (QLA82XX_DRV_ACTIVE << (ha->portnum * 4))) {
2280                qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
2281                    QLA82XX_IDC_VERSION);
2282                ql_log(ql_log_info, vha, 0xb082,
2283                    "IDC version updated to %d\n", QLA82XX_IDC_VERSION);
2284        } else {
2285                idc_ver = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_IDC_VERSION);
2286                if (idc_ver != QLA82XX_IDC_VERSION)
2287                        ql_log(ql_log_info, vha, 0xb083,
2288                            "qla2xxx driver IDC version %d is not compatible "
2289                            "with IDC version %d of the other drivers\n",
2290                            QLA82XX_IDC_VERSION, idc_ver);
2291        }
2292}
2293
2294inline void
2295qla82xx_set_drv_active(scsi_qla_host_t *vha)
2296{
2297        uint32_t drv_active;
2298        struct qla_hw_data *ha = vha->hw;
2299
2300        drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2301
2302        /* If reset value is all FF's, initialize DRV_ACTIVE */
2303        if (drv_active == 0xffffffff) {
2304                qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE,
2305                        QLA82XX_DRV_NOT_ACTIVE);
2306                drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2307        }
2308        drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
2309        qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2310}
2311
2312inline void
2313qla82xx_clear_drv_active(struct qla_hw_data *ha)
2314{
2315        uint32_t drv_active;
2316
2317        drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2318        drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
2319        qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2320}
2321
2322static inline int
2323qla82xx_need_reset(struct qla_hw_data *ha)
2324{
2325        uint32_t drv_state;
2326        int rval;
2327
2328        if (ha->flags.nic_core_reset_owner)
2329                return 1;
2330        else {
2331                drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2332                rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2333                return rval;
2334        }
2335}
2336
2337static inline void
2338qla82xx_set_rst_ready(struct qla_hw_data *ha)
2339{
2340        uint32_t drv_state;
2341        scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2342
2343        drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2344
2345        /* If reset value is all FF's, initialize DRV_STATE */
2346        if (drv_state == 0xffffffff) {
2347                qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY);
2348                drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2349        }
2350        drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2351        ql_dbg(ql_dbg_init, vha, 0x00bb,
2352            "drv_state = 0x%08x.\n", drv_state);
2353        qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2354}
2355
2356static inline void
2357qla82xx_clear_rst_ready(struct qla_hw_data *ha)
2358{
2359        uint32_t drv_state;
2360
2361        drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2362        drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2363        qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2364}
2365
2366static inline void
2367qla82xx_set_qsnt_ready(struct qla_hw_data *ha)
2368{
2369        uint32_t qsnt_state;
2370
2371        qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2372        qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2373        qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2374}
2375
2376void
2377qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha)
2378{
2379        struct qla_hw_data *ha = vha->hw;
2380        uint32_t qsnt_state;
2381
2382        qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2383        qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2384        qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2385}
2386
2387static int
2388qla82xx_load_fw(scsi_qla_host_t *vha)
2389{
2390        int rst;
2391        struct fw_blob *blob;
2392        struct qla_hw_data *ha = vha->hw;
2393
2394        if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) {
2395                ql_log(ql_log_fatal, vha, 0x009f,
2396                    "Error during CRB initialization.\n");
2397                return QLA_FUNCTION_FAILED;
2398        }
2399        udelay(500);
2400
2401        /* Bring QM and CAMRAM out of reset */
2402        rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
2403        rst &= ~((1 << 28) | (1 << 24));
2404        qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
2405
2406        /*
2407         * FW Load priority:
2408         * 1) Operational firmware residing in flash.
2409         * 2) Firmware via request-firmware interface (.bin file).
2410         */
2411        if (ql2xfwloadbin == 2)
2412                goto try_blob_fw;
2413
2414        ql_log(ql_log_info, vha, 0x00a0,
2415            "Attempting to load firmware from flash.\n");
2416
2417        if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) {
2418                ql_log(ql_log_info, vha, 0x00a1,
2419                    "Firmware loaded successfully from flash.\n");
2420                return QLA_SUCCESS;
2421        } else {
2422                ql_log(ql_log_warn, vha, 0x0108,
2423                    "Firmware load from flash failed.\n");
2424        }
2425
2426try_blob_fw:
2427        ql_log(ql_log_info, vha, 0x00a2,
2428            "Attempting to load firmware from blob.\n");
2429
2430        /* Load firmware blob. */
2431        blob = ha->hablob = qla2x00_request_firmware(vha);
2432        if (!blob) {
2433                ql_log(ql_log_fatal, vha, 0x00a3,
2434                    "Firmware image not present.\n");
2435                goto fw_load_failed;
2436        }
2437
2438        /* Validating firmware blob */
2439        if (qla82xx_validate_firmware_blob(vha,
2440                QLA82XX_FLASH_ROMIMAGE)) {
2441                /* Fallback to URI format */
2442                if (qla82xx_validate_firmware_blob(vha,
2443                        QLA82XX_UNIFIED_ROMIMAGE)) {
2444                        ql_log(ql_log_fatal, vha, 0x00a4,
2445                            "No valid firmware image found.\n");
2446                        return QLA_FUNCTION_FAILED;
2447                }
2448        }
2449
2450        if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) {
2451                ql_log(ql_log_info, vha, 0x00a5,
2452                    "Firmware loaded successfully from binary blob.\n");
2453                return QLA_SUCCESS;
2454        }
2455
2456        ql_log(ql_log_fatal, vha, 0x00a6,
2457               "Firmware load failed for binary blob.\n");
2458        blob->fw = NULL;
2459        blob = NULL;
2460
2461fw_load_failed:
2462        return QLA_FUNCTION_FAILED;
2463}
2464
2465int
2466qla82xx_start_firmware(scsi_qla_host_t *vha)
2467{
2468        uint16_t      lnk;
2469        struct qla_hw_data *ha = vha->hw;
2470
2471        /* scrub dma mask expansion register */
2472        qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE);
2473
2474        /* Put both the PEG CMD and RCV PEG to default state
2475         * of 0 before resetting the hardware
2476         */
2477        qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
2478        qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
2479
2480        /* Overwrite stale initialization register values */
2481        qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
2482        qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
2483
2484        if (qla82xx_load_fw(vha) != QLA_SUCCESS) {
2485                ql_log(ql_log_fatal, vha, 0x00a7,
2486                    "Error trying to start fw.\n");
2487                return QLA_FUNCTION_FAILED;
2488        }
2489
2490        /* Handshake with the card before we register the devices. */
2491        if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) {
2492                ql_log(ql_log_fatal, vha, 0x00aa,
2493                    "Error during card handshake.\n");
2494                return QLA_FUNCTION_FAILED;
2495        }
2496
2497        /* Negotiated Link width */
2498        pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
2499        ha->link_width = (lnk >> 4) & 0x3f;
2500
2501        /* Synchronize with Receive peg */
2502        return qla82xx_check_rcvpeg_state(ha);
2503}
2504
2505static __le32 *
2506qla82xx_read_flash_data(scsi_qla_host_t *vha, __le32 *dwptr, uint32_t faddr,
2507        uint32_t length)
2508{
2509        uint32_t i;
2510        uint32_t val;
2511        struct qla_hw_data *ha = vha->hw;
2512
2513        /* Dword reads to flash. */
2514        for (i = 0; i < length/4; i++, faddr += 4) {
2515                if (qla82xx_rom_fast_read(ha, faddr, &val)) {
2516                        ql_log(ql_log_warn, vha, 0x0106,
2517                            "Do ROM fast read failed.\n");
2518                        goto done_read;
2519                }
2520                dwptr[i] = cpu_to_le32(val);
2521        }
2522done_read:
2523        return dwptr;
2524}
2525
2526static int
2527qla82xx_unprotect_flash(struct qla_hw_data *ha)
2528{
2529        int ret;
2530        uint32_t val;
2531        scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2532
2533        ret = ql82xx_rom_lock_d(ha);
2534        if (ret < 0) {
2535                ql_log(ql_log_warn, vha, 0xb014,
2536                    "ROM Lock failed.\n");
2537                return ret;
2538        }
2539
2540        ret = qla82xx_read_status_reg(ha, &val);
2541        if (ret < 0)
2542                goto done_unprotect;
2543
2544        val &= ~(BLOCK_PROTECT_BITS << 2);
2545        ret = qla82xx_write_status_reg(ha, val);
2546        if (ret < 0) {
2547                val |= (BLOCK_PROTECT_BITS << 2);
2548                qla82xx_write_status_reg(ha, val);
2549        }
2550
2551        if (qla82xx_write_disable_flash(ha) != 0)
2552                ql_log(ql_log_warn, vha, 0xb015,
2553                    "Write disable failed.\n");
2554
2555done_unprotect:
2556        qla82xx_rom_unlock(ha);
2557        return ret;
2558}
2559
2560static int
2561qla82xx_protect_flash(struct qla_hw_data *ha)
2562{
2563        int ret;
2564        uint32_t val;
2565        scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2566
2567        ret = ql82xx_rom_lock_d(ha);
2568        if (ret < 0) {
2569                ql_log(ql_log_warn, vha, 0xb016,
2570                    "ROM Lock failed.\n");
2571                return ret;
2572        }
2573
2574        ret = qla82xx_read_status_reg(ha, &val);
2575        if (ret < 0)
2576                goto done_protect;
2577
2578        val |= (BLOCK_PROTECT_BITS << 2);
2579        /* LOCK all sectors */
2580        ret = qla82xx_write_status_reg(ha, val);
2581        if (ret < 0)
2582                ql_log(ql_log_warn, vha, 0xb017,
2583                    "Write status register failed.\n");
2584
2585        if (qla82xx_write_disable_flash(ha) != 0)
2586                ql_log(ql_log_warn, vha, 0xb018,
2587                    "Write disable failed.\n");
2588done_protect:
2589        qla82xx_rom_unlock(ha);
2590        return ret;
2591}
2592
2593static int
2594qla82xx_erase_sector(struct qla_hw_data *ha, int addr)
2595{
2596        int ret = 0;
2597        scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2598
2599        ret = ql82xx_rom_lock_d(ha);
2600        if (ret < 0) {
2601                ql_log(ql_log_warn, vha, 0xb019,
2602                    "ROM Lock failed.\n");
2603                return ret;
2604        }
2605
2606        qla82xx_flash_set_write_enable(ha);
2607        qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
2608        qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
2609        qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE);
2610
2611        if (qla82xx_wait_rom_done(ha)) {
2612                ql_log(ql_log_warn, vha, 0xb01a,
2613                    "Error waiting for rom done.\n");
2614                ret = -1;
2615                goto done;
2616        }
2617        ret = qla82xx_flash_wait_write_finish(ha);
2618done:
2619        qla82xx_rom_unlock(ha);
2620        return ret;
2621}
2622
2623/*
2624 * Address and length are byte address
2625 */
2626void *
2627qla82xx_read_optrom_data(struct scsi_qla_host *vha, void *buf,
2628        uint32_t offset, uint32_t length)
2629{
2630        scsi_block_requests(vha->host);
2631        qla82xx_read_flash_data(vha, buf, offset, length);
2632        scsi_unblock_requests(vha->host);
2633        return buf;
2634}
2635
2636static int
2637qla82xx_write_flash_data(struct scsi_qla_host *vha, __le32 *dwptr,
2638        uint32_t faddr, uint32_t dwords)
2639{
2640        int ret;
2641        uint32_t liter;
2642        uint32_t rest_addr;
2643        dma_addr_t optrom_dma;
2644        void *optrom = NULL;
2645        int page_mode = 0;
2646        struct qla_hw_data *ha = vha->hw;
2647
2648        ret = -1;
2649
2650        /* Prepare burst-capable write on supported ISPs. */
2651        if (page_mode && !(faddr & 0xfff) &&
2652            dwords > OPTROM_BURST_DWORDS) {
2653                optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2654                    &optrom_dma, GFP_KERNEL);
2655                if (!optrom) {
2656                        ql_log(ql_log_warn, vha, 0xb01b,
2657                            "Unable to allocate memory "
2658                            "for optrom burst write (%x KB).\n",
2659                            OPTROM_BURST_SIZE / 1024);
2660                }
2661        }
2662
2663        rest_addr = ha->fdt_block_size - 1;
2664
2665        ret = qla82xx_unprotect_flash(ha);
2666        if (ret) {
2667                ql_log(ql_log_warn, vha, 0xb01c,
2668                    "Unable to unprotect flash for update.\n");
2669                goto write_done;
2670        }
2671
2672        for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) {
2673                /* Are we at the beginning of a sector? */
2674                if ((faddr & rest_addr) == 0) {
2675
2676                        ret = qla82xx_erase_sector(ha, faddr);
2677                        if (ret) {
2678                                ql_log(ql_log_warn, vha, 0xb01d,
2679                                    "Unable to erase sector: address=%x.\n",
2680                                    faddr);
2681                                break;
2682                        }
2683                }
2684
2685                /* Go with burst-write. */
2686                if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
2687                        /* Copy data to DMA'ble buffer. */
2688                        memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
2689
2690                        ret = qla2x00_load_ram(vha, optrom_dma,
2691                            (ha->flash_data_off | faddr),
2692                            OPTROM_BURST_DWORDS);
2693                        if (ret != QLA_SUCCESS) {
2694                                ql_log(ql_log_warn, vha, 0xb01e,
2695                                    "Unable to burst-write optrom segment "
2696                                    "(%x/%x/%llx).\n", ret,
2697                                    (ha->flash_data_off | faddr),
2698                                    (unsigned long long)optrom_dma);
2699                                ql_log(ql_log_warn, vha, 0xb01f,
2700                                    "Reverting to slow-write.\n");
2701
2702                                dma_free_coherent(&ha->pdev->dev,
2703                                    OPTROM_BURST_SIZE, optrom, optrom_dma);
2704                                optrom = NULL;
2705                        } else {
2706                                liter += OPTROM_BURST_DWORDS - 1;
2707                                faddr += OPTROM_BURST_DWORDS - 1;
2708                                dwptr += OPTROM_BURST_DWORDS - 1;
2709                                continue;
2710                        }
2711                }
2712
2713                ret = qla82xx_write_flash_dword(ha, faddr,
2714                                                le32_to_cpu(*dwptr));
2715                if (ret) {
2716                        ql_dbg(ql_dbg_p3p, vha, 0xb020,
2717                            "Unable to program flash address=%x data=%x.\n",
2718                            faddr, *dwptr);
2719                        break;
2720                }
2721        }
2722
2723        ret = qla82xx_protect_flash(ha);
2724        if (ret)
2725                ql_log(ql_log_warn, vha, 0xb021,
2726                    "Unable to protect flash after update.\n");
2727write_done:
2728        if (optrom)
2729                dma_free_coherent(&ha->pdev->dev,
2730                    OPTROM_BURST_SIZE, optrom, optrom_dma);
2731        return ret;
2732}
2733
2734int
2735qla82xx_write_optrom_data(struct scsi_qla_host *vha, void *buf,
2736        uint32_t offset, uint32_t length)
2737{
2738        int rval;
2739
2740        /* Suspend HBA. */
2741        scsi_block_requests(vha->host);
2742        rval = qla82xx_write_flash_data(vha, buf, offset, length >> 2);
2743        scsi_unblock_requests(vha->host);
2744
2745        /* Convert return ISP82xx to generic */
2746        if (rval)
2747                rval = QLA_FUNCTION_FAILED;
2748        else
2749                rval = QLA_SUCCESS;
2750        return rval;
2751}
2752
2753void
2754qla82xx_start_iocbs(scsi_qla_host_t *vha)
2755{
2756        struct qla_hw_data *ha = vha->hw;
2757        struct req_que *req = ha->req_q_map[0];
2758        uint32_t dbval;
2759
2760        /* Adjust ring index. */
2761        req->ring_index++;
2762        if (req->ring_index == req->length) {
2763                req->ring_index = 0;
2764                req->ring_ptr = req->ring;
2765        } else
2766                req->ring_ptr++;
2767
2768        dbval = 0x04 | (ha->portnum << 5);
2769
2770        dbval = dbval | (req->id << 8) | (req->ring_index << 16);
2771        if (ql2xdbwr)
2772                qla82xx_wr_32(ha, (unsigned long)ha->nxdb_wr_ptr, dbval);
2773        else {
2774                wrt_reg_dword(ha->nxdb_wr_ptr, dbval);
2775                wmb();
2776                while (rd_reg_dword(ha->nxdb_rd_ptr) != dbval) {
2777                        wrt_reg_dword(ha->nxdb_wr_ptr, dbval);
2778                        wmb();
2779                }
2780        }
2781}
2782
2783static void
2784qla82xx_rom_lock_recovery(struct qla_hw_data *ha)
2785{
2786        scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2787        uint32_t lock_owner = 0;
2788
2789        if (qla82xx_rom_lock(ha)) {
2790                lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
2791                /* Someone else is holding the lock. */
2792                ql_log(ql_log_info, vha, 0xb022,
2793                    "Resetting rom_lock, Lock Owner %u.\n", lock_owner);
2794        }
2795        /*
2796         * Either we got the lock, or someone
2797         * else died while holding it.
2798         * In either case, unlock.
2799         */
2800        qla82xx_rom_unlock(ha);
2801}
2802
2803/*
2804 * qla82xx_device_bootstrap
2805 *    Initialize device, set DEV_READY, start fw
2806 *
2807 * Note:
2808 *      IDC lock must be held upon entry
2809 *
2810 * Return:
2811 *    Success : 0
2812 *    Failed  : 1
2813 */
2814static int
2815qla82xx_device_bootstrap(scsi_qla_host_t *vha)
2816{
2817        int rval = QLA_SUCCESS;
2818        int i;
2819        uint32_t old_count, count;
2820        struct qla_hw_data *ha = vha->hw;
2821        int need_reset = 0;
2822
2823        need_reset = qla82xx_need_reset(ha);
2824
2825        if (need_reset) {
2826                /* We are trying to perform a recovery here. */
2827                if (ha->flags.isp82xx_fw_hung)
2828                        qla82xx_rom_lock_recovery(ha);
2829        } else  {
2830                old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2831                for (i = 0; i < 10; i++) {
2832                        msleep(200);
2833                        count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2834                        if (count != old_count) {
2835                                rval = QLA_SUCCESS;
2836                                goto dev_ready;
2837                        }
2838                }
2839                qla82xx_rom_lock_recovery(ha);
2840        }
2841
2842        /* set to DEV_INITIALIZING */
2843        ql_log(ql_log_info, vha, 0x009e,
2844            "HW State: INITIALIZING.\n");
2845        qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
2846
2847        qla82xx_idc_unlock(ha);
2848        rval = qla82xx_start_firmware(vha);
2849        qla82xx_idc_lock(ha);
2850
2851        if (rval != QLA_SUCCESS) {
2852                ql_log(ql_log_fatal, vha, 0x00ad,
2853                    "HW State: FAILED.\n");
2854                qla82xx_clear_drv_active(ha);
2855                qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED);
2856                return rval;
2857        }
2858
2859dev_ready:
2860        ql_log(ql_log_info, vha, 0x00ae,
2861            "HW State: READY.\n");
2862        qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY);
2863
2864        return QLA_SUCCESS;
2865}
2866
2867/*
2868* qla82xx_need_qsnt_handler
2869*    Code to start quiescence sequence
2870*
2871* Note:
2872*      IDC lock must be held upon entry
2873*
2874* Return: void
2875*/
2876
2877static void
2878qla82xx_need_qsnt_handler(scsi_qla_host_t *vha)
2879{
2880        struct qla_hw_data *ha = vha->hw;
2881        uint32_t dev_state, drv_state, drv_active;
2882        unsigned long reset_timeout;
2883
2884        if (vha->flags.online) {
2885                /*Block any further I/O and wait for pending cmnds to complete*/
2886                qla2x00_quiesce_io(vha);
2887        }
2888
2889        /* Set the quiescence ready bit */
2890        qla82xx_set_qsnt_ready(ha);
2891
2892        /*wait for 30 secs for other functions to ack */
2893        reset_timeout = jiffies + (30 * HZ);
2894
2895        drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2896        drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2897        /* Its 2 that is written when qsnt is acked, moving one bit */
2898        drv_active = drv_active << 0x01;
2899
2900        while (drv_state != drv_active) {
2901
2902                if (time_after_eq(jiffies, reset_timeout)) {
2903                        /* quiescence timeout, other functions didn't ack
2904                         * changing the state to DEV_READY
2905                         */
2906                        ql_log(ql_log_info, vha, 0xb023,
2907                            "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d "
2908                            "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME,
2909                            drv_active, drv_state);
2910                        qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2911                            QLA8XXX_DEV_READY);
2912                        ql_log(ql_log_info, vha, 0xb025,
2913                            "HW State: DEV_READY.\n");
2914                        qla82xx_idc_unlock(ha);
2915                        qla2x00_perform_loop_resync(vha);
2916                        qla82xx_idc_lock(ha);
2917
2918                        qla82xx_clear_qsnt_ready(vha);
2919                        return;
2920                }
2921
2922                qla82xx_idc_unlock(ha);
2923                msleep(1000);
2924                qla82xx_idc_lock(ha);
2925
2926                drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2927                drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2928                drv_active = drv_active << 0x01;
2929        }
2930        dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2931        /* everyone acked so set the state to DEV_QUIESCENCE */
2932        if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
2933                ql_log(ql_log_info, vha, 0xb026,
2934                    "HW State: DEV_QUIESCENT.\n");
2935                qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_QUIESCENT);
2936        }
2937}
2938
2939/*
2940* qla82xx_wait_for_state_change
2941*    Wait for device state to change from given current state
2942*
2943* Note:
2944*     IDC lock must not be held upon entry
2945*
2946* Return:
2947*    Changed device state.
2948*/
2949uint32_t
2950qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state)
2951{
2952        struct qla_hw_data *ha = vha->hw;
2953        uint32_t dev_state;
2954
2955        do {
2956                msleep(1000);
2957                qla82xx_idc_lock(ha);
2958                dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2959                qla82xx_idc_unlock(ha);
2960        } while (dev_state == curr_state);
2961
2962        return dev_state;
2963}
2964
2965void
2966qla8xxx_dev_failed_handler(scsi_qla_host_t *vha)
2967{
2968        struct qla_hw_data *ha = vha->hw;
2969
2970        /* Disable the board */
2971        ql_log(ql_log_fatal, vha, 0x00b8,
2972            "Disabling the board.\n");
2973
2974        if (IS_QLA82XX(ha)) {
2975                qla82xx_clear_drv_active(ha);
2976                qla82xx_idc_unlock(ha);
2977        } else if (IS_QLA8044(ha)) {
2978                qla8044_clear_drv_active(ha);
2979                qla8044_idc_unlock(ha);
2980        }
2981
2982        /* Set DEV_FAILED flag to disable timer */
2983        vha->device_flags |= DFLG_DEV_FAILED;
2984        qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
2985        qla2x00_mark_all_devices_lost(vha);
2986        vha->flags.online = 0;
2987        vha->flags.init_done = 0;
2988}
2989
2990/*
2991 * qla82xx_need_reset_handler
2992 *    Code to start reset sequence
2993 *
2994 * Note:
2995 *      IDC lock must be held upon entry
2996 *
2997 * Return:
2998 *    Success : 0
2999 *    Failed  : 1
3000 */
3001static void
3002qla82xx_need_reset_handler(scsi_qla_host_t *vha)
3003{
3004        uint32_t dev_state, drv_state, drv_active;
3005        uint32_t active_mask = 0;
3006        unsigned long reset_timeout;
3007        struct qla_hw_data *ha = vha->hw;
3008        struct req_que *req = ha->req_q_map[0];
3009
3010        if (vha->flags.online) {
3011                qla82xx_idc_unlock(ha);
3012                qla2x00_abort_isp_cleanup(vha);
3013                ha->isp_ops->get_flash_version(vha, req->ring);
3014                ha->isp_ops->nvram_config(vha);
3015                qla82xx_idc_lock(ha);
3016        }
3017
3018        drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3019        if (!ha->flags.nic_core_reset_owner) {
3020                ql_dbg(ql_dbg_p3p, vha, 0xb028,
3021                    "reset_acknowledged by 0x%x\n", ha->portnum);
3022                qla82xx_set_rst_ready(ha);
3023        } else {
3024                active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
3025                drv_active &= active_mask;
3026                ql_dbg(ql_dbg_p3p, vha, 0xb029,
3027                    "active_mask: 0x%08x\n", active_mask);
3028        }
3029
3030        /* wait for 10 seconds for reset ack from all functions */
3031        reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
3032
3033        drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3034        drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3035        dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3036
3037        ql_dbg(ql_dbg_p3p, vha, 0xb02a,
3038            "drv_state: 0x%08x, drv_active: 0x%08x, "
3039            "dev_state: 0x%08x, active_mask: 0x%08x\n",
3040            drv_state, drv_active, dev_state, active_mask);
3041
3042        while (drv_state != drv_active &&
3043            dev_state != QLA8XXX_DEV_INITIALIZING) {
3044                if (time_after_eq(jiffies, reset_timeout)) {
3045                        ql_log(ql_log_warn, vha, 0x00b5,
3046                            "Reset timeout.\n");
3047                        break;
3048                }
3049                qla82xx_idc_unlock(ha);
3050                msleep(1000);
3051                qla82xx_idc_lock(ha);
3052                drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3053                drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3054                if (ha->flags.nic_core_reset_owner)
3055                        drv_active &= active_mask;
3056                dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3057        }
3058
3059        ql_dbg(ql_dbg_p3p, vha, 0xb02b,
3060            "drv_state: 0x%08x, drv_active: 0x%08x, "
3061            "dev_state: 0x%08x, active_mask: 0x%08x\n",
3062            drv_state, drv_active, dev_state, active_mask);
3063
3064        ql_log(ql_log_info, vha, 0x00b6,
3065            "Device state is 0x%x = %s.\n",
3066            dev_state,
3067            dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3068
3069        /* Force to DEV_COLD unless someone else is starting a reset */
3070        if (dev_state != QLA8XXX_DEV_INITIALIZING &&
3071            dev_state != QLA8XXX_DEV_COLD) {
3072                ql_log(ql_log_info, vha, 0x00b7,
3073                    "HW State: COLD/RE-INIT.\n");
3074                qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD);
3075                qla82xx_set_rst_ready(ha);
3076                if (ql2xmdenable) {
3077                        if (qla82xx_md_collect(vha))
3078                                ql_log(ql_log_warn, vha, 0xb02c,
3079                                    "Minidump not collected.\n");
3080                } else
3081                        ql_log(ql_log_warn, vha, 0xb04f,
3082                            "Minidump disabled.\n");
3083        }
3084}
3085
3086int
3087qla82xx_check_md_needed(scsi_qla_host_t *vha)
3088{
3089        struct qla_hw_data *ha = vha->hw;
3090        uint16_t fw_major_version, fw_minor_version, fw_subminor_version;
3091        int rval = QLA_SUCCESS;
3092
3093        fw_major_version = ha->fw_major_version;
3094        fw_minor_version = ha->fw_minor_version;
3095        fw_subminor_version = ha->fw_subminor_version;
3096
3097        rval = qla2x00_get_fw_version(vha);
3098        if (rval != QLA_SUCCESS)
3099                return rval;
3100
3101        if (ql2xmdenable) {
3102                if (!ha->fw_dumped) {
3103                        if ((fw_major_version != ha->fw_major_version ||
3104                            fw_minor_version != ha->fw_minor_version ||
3105                            fw_subminor_version != ha->fw_subminor_version) ||
3106                            (ha->prev_minidump_failed)) {
3107                                ql_dbg(ql_dbg_p3p, vha, 0xb02d,
3108                                    "Firmware version differs Previous version: %d:%d:%d - New version: %d:%d:%d, prev_minidump_failed: %d.\n",
3109                                    fw_major_version, fw_minor_version,
3110                                    fw_subminor_version,
3111                                    ha->fw_major_version,
3112                                    ha->fw_minor_version,
3113                                    ha->fw_subminor_version,
3114                                    ha->prev_minidump_failed);
3115                                /* Release MiniDump resources */
3116                                qla82xx_md_free(vha);
3117                                /* ALlocate MiniDump resources */
3118                                qla82xx_md_prep(vha);
3119                        }
3120                } else
3121                        ql_log(ql_log_info, vha, 0xb02e,
3122                            "Firmware dump available to retrieve\n");
3123        }
3124        return rval;
3125}
3126
3127
3128static int
3129qla82xx_check_fw_alive(scsi_qla_host_t *vha)
3130{
3131        uint32_t fw_heartbeat_counter;
3132        int status = 0;
3133
3134        fw_heartbeat_counter = qla82xx_rd_32(vha->hw,
3135                QLA82XX_PEG_ALIVE_COUNTER);
3136        /* all 0xff, assume AER/EEH in progress, ignore */
3137        if (fw_heartbeat_counter == 0xffffffff) {
3138                ql_dbg(ql_dbg_timer, vha, 0x6003,
3139                    "FW heartbeat counter is 0xffffffff, "
3140                    "returning status=%d.\n", status);
3141                return status;
3142        }
3143        if (vha->fw_heartbeat_counter == fw_heartbeat_counter) {
3144                vha->seconds_since_last_heartbeat++;
3145                /* FW not alive after 2 seconds */
3146                if (vha->seconds_since_last_heartbeat == 2) {
3147                        vha->seconds_since_last_heartbeat = 0;
3148                        status = 1;
3149                }
3150        } else
3151                vha->seconds_since_last_heartbeat = 0;
3152        vha->fw_heartbeat_counter = fw_heartbeat_counter;
3153        if (status)
3154                ql_dbg(ql_dbg_timer, vha, 0x6004,
3155                    "Returning status=%d.\n", status);
3156        return status;
3157}
3158
3159/*
3160 * qla82xx_device_state_handler
3161 *      Main state handler
3162 *
3163 * Note:
3164 *      IDC lock must be held upon entry
3165 *
3166 * Return:
3167 *    Success : 0
3168 *    Failed  : 1
3169 */
3170int
3171qla82xx_device_state_handler(scsi_qla_host_t *vha)
3172{
3173        uint32_t dev_state;
3174        uint32_t old_dev_state;
3175        int rval = QLA_SUCCESS;
3176        unsigned long dev_init_timeout;
3177        struct qla_hw_data *ha = vha->hw;
3178        int loopcount = 0;
3179
3180        qla82xx_idc_lock(ha);
3181        if (!vha->flags.init_done) {
3182                qla82xx_set_drv_active(vha);
3183                qla82xx_set_idc_version(vha);
3184        }
3185
3186        dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3187        old_dev_state = dev_state;
3188        ql_log(ql_log_info, vha, 0x009b,
3189            "Device state is 0x%x = %s.\n",
3190            dev_state,
3191            dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3192
3193        /* wait for 30 seconds for device to go ready */
3194        dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
3195
3196        while (1) {
3197
3198                if (time_after_eq(jiffies, dev_init_timeout)) {
3199                        ql_log(ql_log_fatal, vha, 0x009c,
3200                            "Device init failed.\n");
3201                        rval = QLA_FUNCTION_FAILED;
3202                        break;
3203                }
3204                dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3205                if (old_dev_state != dev_state) {
3206                        loopcount = 0;
3207                        old_dev_state = dev_state;
3208                }
3209                if (loopcount < 5) {
3210                        ql_log(ql_log_info, vha, 0x009d,
3211                            "Device state is 0x%x = %s.\n",
3212                            dev_state,
3213                            dev_state < MAX_STATES ? qdev_state(dev_state) :
3214                            "Unknown");
3215                }
3216
3217                switch (dev_state) {
3218                case QLA8XXX_DEV_READY:
3219                        ha->flags.nic_core_reset_owner = 0;
3220                        goto rel_lock;
3221                case QLA8XXX_DEV_COLD:
3222                        rval = qla82xx_device_bootstrap(vha);
3223                        break;
3224                case QLA8XXX_DEV_INITIALIZING:
3225                        qla82xx_idc_unlock(ha);
3226                        msleep(1000);
3227                        qla82xx_idc_lock(ha);
3228                        break;
3229                case QLA8XXX_DEV_NEED_RESET:
3230                        if (!ql2xdontresethba)
3231                                qla82xx_need_reset_handler(vha);
3232                        else {
3233                                qla82xx_idc_unlock(ha);
3234                                msleep(1000);
3235                                qla82xx_idc_lock(ha);
3236                        }
3237                        dev_init_timeout = jiffies +
3238                            (ha->fcoe_dev_init_timeout * HZ);
3239                        break;
3240                case QLA8XXX_DEV_NEED_QUIESCENT:
3241                        qla82xx_need_qsnt_handler(vha);
3242                        /* Reset timeout value after quiescence handler */
3243                        dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout
3244                                                         * HZ);
3245                        break;
3246                case QLA8XXX_DEV_QUIESCENT:
3247                        /* Owner will exit and other will wait for the state
3248                         * to get changed
3249                         */
3250                        if (ha->flags.quiesce_owner)
3251                                goto rel_lock;
3252
3253                        qla82xx_idc_unlock(ha);
3254                        msleep(1000);
3255                        qla82xx_idc_lock(ha);
3256
3257                        /* Reset timeout value after quiescence handler */
3258                        dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout
3259                                                         * HZ);
3260                        break;
3261                case QLA8XXX_DEV_FAILED:
3262                        qla8xxx_dev_failed_handler(vha);
3263                        rval = QLA_FUNCTION_FAILED;
3264                        goto exit;
3265                default:
3266                        qla82xx_idc_unlock(ha);
3267                        msleep(1000);
3268                        qla82xx_idc_lock(ha);
3269                }
3270                loopcount++;
3271        }
3272rel_lock:
3273        qla82xx_idc_unlock(ha);
3274exit:
3275        return rval;
3276}
3277
3278static int qla82xx_check_temp(scsi_qla_host_t *vha)
3279{
3280        uint32_t temp, temp_state, temp_val;
3281        struct qla_hw_data *ha = vha->hw;
3282
3283        temp = qla82xx_rd_32(ha, CRB_TEMP_STATE);
3284        temp_state = qla82xx_get_temp_state(temp);
3285        temp_val = qla82xx_get_temp_val(temp);
3286
3287        if (temp_state == QLA82XX_TEMP_PANIC) {
3288                ql_log(ql_log_warn, vha, 0x600e,
3289                    "Device temperature %d degrees C exceeds "
3290                    " maximum allowed. Hardware has been shut down.\n",
3291                    temp_val);
3292                return 1;
3293        } else if (temp_state == QLA82XX_TEMP_WARN) {
3294                ql_log(ql_log_warn, vha, 0x600f,
3295                    "Device temperature %d degrees C exceeds "
3296                    "operating range. Immediate action needed.\n",
3297                    temp_val);
3298        }
3299        return 0;
3300}
3301
3302int qla82xx_read_temperature(scsi_qla_host_t *vha)
3303{
3304        uint32_t temp;
3305
3306        temp = qla82xx_rd_32(vha->hw, CRB_TEMP_STATE);
3307        return qla82xx_get_temp_val(temp);
3308}
3309
3310void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha)
3311{
3312        struct qla_hw_data *ha = vha->hw;
3313
3314        if (ha->flags.mbox_busy) {
3315                ha->flags.mbox_int = 1;
3316                ha->flags.mbox_busy = 0;
3317                ql_log(ql_log_warn, vha, 0x6010,
3318                    "Doing premature completion of mbx command.\n");
3319                if (test_and_clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags))
3320                        complete(&ha->mbx_intr_comp);
3321        }
3322}
3323
3324void qla82xx_watchdog(scsi_qla_host_t *vha)
3325{
3326        uint32_t dev_state, halt_status;
3327        struct qla_hw_data *ha = vha->hw;
3328
3329        /* don't poll if reset is going on */
3330        if (!ha->flags.nic_core_reset_hdlr_active) {
3331                dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3332                if (qla82xx_check_temp(vha)) {
3333                        set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
3334                        ha->flags.isp82xx_fw_hung = 1;
3335                        qla82xx_clear_pending_mbx(vha);
3336                } else if (dev_state == QLA8XXX_DEV_NEED_RESET &&
3337                    !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) {
3338                        ql_log(ql_log_warn, vha, 0x6001,
3339                            "Adapter reset needed.\n");
3340                        set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
3341                } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT &&
3342                        !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) {
3343                        ql_log(ql_log_warn, vha, 0x6002,
3344                            "Quiescent needed.\n");
3345                        set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
3346                } else if (dev_state == QLA8XXX_DEV_FAILED &&
3347                        !test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) &&
3348                        vha->flags.online == 1) {
3349                        ql_log(ql_log_warn, vha, 0xb055,
3350                            "Adapter state is failed. Offlining.\n");
3351                        set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
3352                        ha->flags.isp82xx_fw_hung = 1;
3353                        qla82xx_clear_pending_mbx(vha);
3354                } else {
3355                        if (qla82xx_check_fw_alive(vha)) {
3356                                ql_dbg(ql_dbg_timer, vha, 0x6011,
3357                                    "disabling pause transmit on port 0 & 1.\n");
3358                                qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
3359                                    CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1);
3360                                halt_status = qla82xx_rd_32(ha,
3361                                    QLA82XX_PEG_HALT_STATUS1);
3362                                ql_log(ql_log_info, vha, 0x6005,
3363                                    "dumping hw/fw registers:.\n "
3364                                    " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n "
3365                                    " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n "
3366                                    " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n "
3367                                    " PEG_NET_4_PC: 0x%x.\n", halt_status,
3368                                    qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2),
3369                                    qla82xx_rd_32(ha,
3370                                            QLA82XX_CRB_PEG_NET_0 + 0x3c),
3371                                    qla82xx_rd_32(ha,
3372                                            QLA82XX_CRB_PEG_NET_1 + 0x3c),
3373                                    qla82xx_rd_32(ha,
3374                                            QLA82XX_CRB_PEG_NET_2 + 0x3c),
3375                                    qla82xx_rd_32(ha,
3376                                            QLA82XX_CRB_PEG_NET_3 + 0x3c),
3377                                    qla82xx_rd_32(ha,
3378                                            QLA82XX_CRB_PEG_NET_4 + 0x3c));
3379                                if (((halt_status & 0x1fffff00) >> 8) == 0x67)
3380                                        ql_log(ql_log_warn, vha, 0xb052,
3381                                            "Firmware aborted with "
3382                                            "error code 0x00006700. Device is "
3383                                            "being reset.\n");
3384                                if (halt_status & HALT_STATUS_UNRECOVERABLE) {
3385                                        set_bit(ISP_UNRECOVERABLE,
3386                                            &vha->dpc_flags);
3387                                } else {
3388                                        ql_log(ql_log_info, vha, 0x6006,
3389                                            "Detect abort  needed.\n");
3390                                        set_bit(ISP_ABORT_NEEDED,
3391                                            &vha->dpc_flags);
3392                                }
3393                                ha->flags.isp82xx_fw_hung = 1;
3394                                ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n");
3395                                qla82xx_clear_pending_mbx(vha);
3396                        }
3397                }
3398        }
3399}
3400
3401int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
3402{
3403        int rval = -1;
3404        struct qla_hw_data *ha = vha->hw;
3405
3406        if (IS_QLA82XX(ha))
3407                rval = qla82xx_device_state_handler(vha);
3408        else if (IS_QLA8044(ha)) {
3409                qla8044_idc_lock(ha);
3410                /* Decide the reset ownership */
3411                qla83xx_reset_ownership(vha);
3412                qla8044_idc_unlock(ha);
3413                rval = qla8044_device_state_handler(vha);
3414        }
3415        return rval;
3416}
3417
3418void
3419qla82xx_set_reset_owner(scsi_qla_host_t *vha)
3420{
3421        struct qla_hw_data *ha = vha->hw;
3422        uint32_t dev_state = 0;
3423
3424        if (IS_QLA82XX(ha))
3425                dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3426        else if (IS_QLA8044(ha))
3427                dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
3428
3429        if (dev_state == QLA8XXX_DEV_READY) {
3430                ql_log(ql_log_info, vha, 0xb02f,
3431                    "HW State: NEED RESET\n");
3432                if (IS_QLA82XX(ha)) {
3433                        qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3434                            QLA8XXX_DEV_NEED_RESET);
3435                        ha->flags.nic_core_reset_owner = 1;
3436                        ql_dbg(ql_dbg_p3p, vha, 0xb030,
3437                            "reset_owner is 0x%x\n", ha->portnum);
3438                } else if (IS_QLA8044(ha))
3439                        qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
3440                            QLA8XXX_DEV_NEED_RESET);
3441        } else
3442                ql_log(ql_log_info, vha, 0xb031,
3443                    "Device state is 0x%x = %s.\n",
3444                    dev_state,
3445                    dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3446}
3447
3448/*
3449 *  qla82xx_abort_isp
3450 *      Resets ISP and aborts all outstanding commands.
3451 *
3452 * Input:
3453 *      ha           = adapter block pointer.
3454 *
3455 * Returns:
3456 *      0 = success
3457 */
3458int
3459qla82xx_abort_isp(scsi_qla_host_t *vha)
3460{
3461        int rval = -1;
3462        struct qla_hw_data *ha = vha->hw;
3463
3464        if (vha->device_flags & DFLG_DEV_FAILED) {
3465                ql_log(ql_log_warn, vha, 0x8024,
3466                    "Device in failed state, exiting.\n");
3467                return QLA_SUCCESS;
3468        }
3469        ha->flags.nic_core_reset_hdlr_active = 1;
3470
3471        qla82xx_idc_lock(ha);
3472        qla82xx_set_reset_owner(vha);
3473        qla82xx_idc_unlock(ha);
3474
3475        if (IS_QLA82XX(ha))
3476                rval = qla82xx_device_state_handler(vha);
3477        else if (IS_QLA8044(ha)) {
3478                qla8044_idc_lock(ha);
3479                /* Decide the reset ownership */
3480                qla83xx_reset_ownership(vha);
3481                qla8044_idc_unlock(ha);
3482                rval = qla8044_device_state_handler(vha);
3483        }
3484
3485        qla82xx_idc_lock(ha);
3486        qla82xx_clear_rst_ready(ha);
3487        qla82xx_idc_unlock(ha);
3488
3489        if (rval == QLA_SUCCESS) {
3490                ha->flags.isp82xx_fw_hung = 0;
3491                ha->flags.nic_core_reset_hdlr_active = 0;
3492                qla82xx_restart_isp(vha);
3493        }
3494
3495        if (rval) {
3496                vha->flags.online = 1;
3497                if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
3498                        if (ha->isp_abort_cnt == 0) {
3499                                ql_log(ql_log_warn, vha, 0x8027,
3500                                    "ISP error recover failed - board "
3501                                    "disabled.\n");
3502                                /*
3503                                 * The next call disables the board
3504                                 * completely.
3505                                 */
3506                                ha->isp_ops->reset_adapter(vha);
3507                                vha->flags.online = 0;
3508                                clear_bit(ISP_ABORT_RETRY,
3509                                    &vha->dpc_flags);
3510                                rval = QLA_SUCCESS;
3511                        } else { /* schedule another ISP abort */
3512                                ha->isp_abort_cnt--;
3513                                ql_log(ql_log_warn, vha, 0x8036,
3514                                    "ISP abort - retry remaining %d.\n",
3515                                    ha->isp_abort_cnt);
3516                                rval = QLA_FUNCTION_FAILED;
3517                        }
3518                } else {
3519                        ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
3520                        ql_dbg(ql_dbg_taskm, vha, 0x8029,
3521                            "ISP error recovery - retrying (%d) more times.\n",
3522                            ha->isp_abort_cnt);
3523                        set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3524                        rval = QLA_FUNCTION_FAILED;
3525                }
3526        }
3527        return rval;
3528}
3529
3530/*
3531 *  qla82xx_fcoe_ctx_reset
3532 *      Perform a quick reset and aborts all outstanding commands.
3533 *      This will only perform an FCoE context reset and avoids a full blown
3534 *      chip reset.
3535 *
3536 * Input:
3537 *      ha = adapter block pointer.
3538 *      is_reset_path = flag for identifying the reset path.
3539 *
3540 * Returns:
3541 *      0 = success
3542 */
3543int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha)
3544{
3545        int rval = QLA_FUNCTION_FAILED;
3546
3547        if (vha->flags.online) {
3548                /* Abort all outstanding commands, so as to be requeued later */
3549                qla2x00_abort_isp_cleanup(vha);
3550        }
3551
3552        /* Stop currently executing firmware.
3553         * This will destroy existing FCoE context at the F/W end.
3554         */
3555        qla2x00_try_to_stop_firmware(vha);
3556
3557        /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */
3558        rval = qla82xx_restart_isp(vha);
3559
3560        return rval;
3561}
3562
3563/*
3564 * qla2x00_wait_for_fcoe_ctx_reset
3565 *    Wait till the FCoE context is reset.
3566 *
3567 * Note:
3568 *    Does context switching here.
3569 *    Release SPIN_LOCK (if any) before calling this routine.
3570 *
3571 * Return:
3572 *    Success (fcoe_ctx reset is done) : 0
3573 *    Failed  (fcoe_ctx reset not completed within max loop timout ) : 1
3574 */
3575int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha)
3576{
3577        int status = QLA_FUNCTION_FAILED;
3578        unsigned long wait_reset;
3579
3580        wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
3581        while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
3582            test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
3583            && time_before(jiffies, wait_reset)) {
3584
3585                set_current_state(TASK_UNINTERRUPTIBLE);
3586                schedule_timeout(HZ);
3587
3588                if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) &&
3589                    !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) {
3590                        status = QLA_SUCCESS;
3591                        break;
3592                }
3593        }
3594        ql_dbg(ql_dbg_p3p, vha, 0xb027,
3595               "%s: status=%d.\n", __func__, status);
3596
3597        return status;
3598}
3599
3600void
3601qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha)
3602{
3603        int i, fw_state = 0;
3604        unsigned long flags;
3605        struct qla_hw_data *ha = vha->hw;
3606
3607        /* Check if 82XX firmware is alive or not
3608         * We may have arrived here from NEED_RESET
3609         * detection only
3610         */
3611        if (!ha->flags.isp82xx_fw_hung) {
3612                for (i = 0; i < 2; i++) {
3613                        msleep(1000);
3614                        if (IS_QLA82XX(ha))
3615                                fw_state = qla82xx_check_fw_alive(vha);
3616                        else if (IS_QLA8044(ha))
3617                                fw_state = qla8044_check_fw_alive(vha);
3618                        if (fw_state) {
3619                                ha->flags.isp82xx_fw_hung = 1;
3620                                qla82xx_clear_pending_mbx(vha);
3621                                break;
3622                        }
3623                }
3624        }
3625        ql_dbg(ql_dbg_init, vha, 0x00b0,
3626            "Entered %s fw_hung=%d.\n",
3627            __func__, ha->flags.isp82xx_fw_hung);
3628
3629        /* Abort all commands gracefully if fw NOT hung */
3630        if (!ha->flags.isp82xx_fw_hung) {
3631                int cnt, que;
3632                srb_t *sp;
3633                struct req_que *req;
3634
3635                spin_lock_irqsave(&ha->hardware_lock, flags);
3636                for (que = 0; que < ha->max_req_queues; que++) {
3637                        req = ha->req_q_map[que];
3638                        if (!req)
3639                                continue;
3640                        for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
3641                                sp = req->outstanding_cmds[cnt];
3642                                if (sp) {
3643                                        if ((!sp->u.scmd.crc_ctx ||
3644                                            (sp->flags &
3645                                                SRB_FCP_CMND_DMA_VALID)) &&
3646                                                !ha->flags.isp82xx_fw_hung) {
3647                                                spin_unlock_irqrestore(
3648                                                    &ha->hardware_lock, flags);
3649                                                if (ha->isp_ops->abort_command(sp)) {
3650                                                        ql_log(ql_log_info, vha,
3651                                                            0x00b1,
3652                                                            "mbx abort failed.\n");
3653                                                } else {
3654                                                        ql_log(ql_log_info, vha,
3655                                                            0x00b2,
3656                                                            "mbx abort success.\n");
3657                                                }
3658                                                spin_lock_irqsave(&ha->hardware_lock, flags);
3659                                        }
3660                                }
3661                        }
3662                }
3663                spin_unlock_irqrestore(&ha->hardware_lock, flags);
3664
3665                /* Wait for pending cmds (physical and virtual) to complete */
3666                if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0,
3667                    WAIT_HOST) == QLA_SUCCESS) {
3668                        ql_dbg(ql_dbg_init, vha, 0x00b3,
3669                            "Done wait for "
3670                            "pending commands.\n");
3671                } else {
3672                        WARN_ON_ONCE(true);
3673                }
3674        }
3675}
3676
3677/* Minidump related functions */
3678static int
3679qla82xx_minidump_process_control(scsi_qla_host_t *vha,
3680        qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
3681{
3682        struct qla_hw_data *ha = vha->hw;
3683        struct qla82xx_md_entry_crb *crb_entry;
3684        uint32_t read_value, opcode, poll_time;
3685        uint32_t addr, index, crb_addr;
3686        unsigned long wtime;
3687        struct qla82xx_md_template_hdr *tmplt_hdr;
3688        uint32_t rval = QLA_SUCCESS;
3689        int i;
3690
3691        tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
3692        crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr;
3693        crb_addr = crb_entry->addr;
3694
3695        for (i = 0; i < crb_entry->op_count; i++) {
3696                opcode = crb_entry->crb_ctrl.opcode;
3697                if (opcode & QLA82XX_DBG_OPCODE_WR) {
3698                        qla82xx_md_rw_32(ha, crb_addr,
3699                            crb_entry->value_1, 1);
3700                        opcode &= ~QLA82XX_DBG_OPCODE_WR;
3701                }
3702
3703                if (opcode & QLA82XX_DBG_OPCODE_RW) {
3704                        read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3705                        qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3706                        opcode &= ~QLA82XX_DBG_OPCODE_RW;
3707                }
3708
3709                if (opcode & QLA82XX_DBG_OPCODE_AND) {
3710                        read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3711                        read_value &= crb_entry->value_2;
3712                        opcode &= ~QLA82XX_DBG_OPCODE_AND;
3713                        if (opcode & QLA82XX_DBG_OPCODE_OR) {
3714                                read_value |= crb_entry->value_3;
3715                                opcode &= ~QLA82XX_DBG_OPCODE_OR;
3716                        }
3717                        qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3718                }
3719
3720                if (opcode & QLA82XX_DBG_OPCODE_OR) {
3721                        read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3722                        read_value |= crb_entry->value_3;
3723                        qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3724                        opcode &= ~QLA82XX_DBG_OPCODE_OR;
3725                }
3726
3727                if (opcode & QLA82XX_DBG_OPCODE_POLL) {
3728                        poll_time = crb_entry->crb_strd.poll_timeout;
3729                        wtime = jiffies + poll_time;
3730                        read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3731
3732                        do {
3733                                if ((read_value & crb_entry->value_2)
3734                                    == crb_entry->value_1)
3735                                        break;
3736                                else if (time_after_eq(jiffies, wtime)) {
3737                                        /* capturing dump failed */
3738                                        rval = QLA_FUNCTION_FAILED;
3739                                        break;
3740                                } else
3741                                        read_value = qla82xx_md_rw_32(ha,
3742                                            crb_addr, 0, 0);
3743                        } while (1);
3744                        opcode &= ~QLA82XX_DBG_OPCODE_POLL;
3745                }
3746
3747                if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) {
3748                        if (crb_entry->crb_strd.state_index_a) {
3749                                index = crb_entry->crb_strd.state_index_a;
3750                                addr = tmplt_hdr->saved_state_array[index];
3751                        } else
3752                                addr = crb_addr;
3753
3754                        read_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3755                        index = crb_entry->crb_ctrl.state_index_v;
3756                        tmplt_hdr->saved_state_array[index] = read_value;
3757                        opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE;
3758                }
3759
3760                if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) {
3761                        if (crb_entry->crb_strd.state_index_a) {
3762                                index = crb_entry->crb_strd.state_index_a;
3763                                addr = tmplt_hdr->saved_state_array[index];
3764                        } else
3765                                addr = crb_addr;
3766
3767                        if (crb_entry->crb_ctrl.state_index_v) {
3768                                index = crb_entry->crb_ctrl.state_index_v;
3769                                read_value =
3770                                    tmplt_hdr->saved_state_array[index];
3771                        } else
3772                                read_value = crb_entry->value_1;
3773
3774                        qla82xx_md_rw_32(ha, addr, read_value, 1);
3775                        opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE;
3776                }
3777
3778                if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) {
3779                        index = crb_entry->crb_ctrl.state_index_v;
3780                        read_value = tmplt_hdr->saved_state_array[index];
3781                        read_value <<= crb_entry->crb_ctrl.shl;
3782                        read_value >>= crb_entry->crb_ctrl.shr;
3783                        if (crb_entry->value_2)
3784                                read_value &= crb_entry->value_2;
3785                        read_value |= crb_entry->value_3;
3786                        read_value += crb_entry->value_1;
3787                        tmplt_hdr->saved_state_array[index] = read_value;
3788                        opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE;
3789                }
3790                crb_addr += crb_entry->crb_strd.addr_stride;
3791        }
3792        return rval;
3793}
3794
3795static void
3796qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha,
3797        qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
3798{
3799        struct qla_hw_data *ha = vha->hw;
3800        uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3801        struct qla82xx_md_entry_rdocm *ocm_hdr;
3802        __le32 *data_ptr = *d_ptr;
3803
3804        ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr;
3805        r_addr = ocm_hdr->read_addr;
3806        r_stride = ocm_hdr->read_addr_stride;
3807        loop_cnt = ocm_hdr->op_count;
3808
3809        for (i = 0; i < loop_cnt; i++) {
3810                r_value = rd_reg_dword(r_addr + ha->nx_pcibase);
3811                *data_ptr++ = cpu_to_le32(r_value);
3812                r_addr += r_stride;
3813        }
3814        *d_ptr = data_ptr;
3815}
3816
3817static void
3818qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha,
3819        qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
3820{
3821        struct qla_hw_data *ha = vha->hw;
3822        uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
3823        struct qla82xx_md_entry_mux *mux_hdr;
3824        __le32 *data_ptr = *d_ptr;
3825
3826        mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr;
3827        r_addr = mux_hdr->read_addr;
3828        s_addr = mux_hdr->select_addr;
3829        s_stride = mux_hdr->select_value_stride;
3830        s_value = mux_hdr->select_value;
3831        loop_cnt = mux_hdr->op_count;
3832
3833        for (i = 0; i < loop_cnt; i++) {
3834                qla82xx_md_rw_32(ha, s_addr, s_value, 1);
3835                r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3836                *data_ptr++ = cpu_to_le32(s_value);
3837                *data_ptr++ = cpu_to_le32(r_value);
3838                s_value += s_stride;
3839        }
3840        *d_ptr = data_ptr;
3841}
3842
3843static void
3844qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha,
3845        qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
3846{
3847        struct qla_hw_data *ha = vha->hw;
3848        uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3849        struct qla82xx_md_entry_crb *crb_hdr;
3850        __le32 *data_ptr = *d_ptr;
3851
3852        crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr;
3853        r_addr = crb_hdr->addr;
3854        r_stride = crb_hdr->crb_strd.addr_stride;
3855        loop_cnt = crb_hdr->op_count;
3856
3857        for (i = 0; i < loop_cnt; i++) {
3858                r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3859                *data_ptr++ = cpu_to_le32(r_addr);
3860                *data_ptr++ = cpu_to_le32(r_value);
3861                r_addr += r_stride;
3862        }
3863        *d_ptr = data_ptr;
3864}
3865
3866static int
3867qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha,
3868        qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
3869{
3870        struct qla_hw_data *ha = vha->hw;
3871        uint32_t addr, r_addr, c_addr, t_r_addr;
3872        uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3873        unsigned long p_wait, w_time, p_mask;
3874        uint32_t c_value_w, c_value_r;
3875        struct qla82xx_md_entry_cache *cache_hdr;
3876        int rval = QLA_FUNCTION_FAILED;
3877        __le32 *data_ptr = *d_ptr;
3878
3879        cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
3880        loop_count = cache_hdr->op_count;
3881        r_addr = cache_hdr->read_addr;
3882        c_addr = cache_hdr->control_addr;
3883        c_value_w = cache_hdr->cache_ctrl.write_value;
3884
3885        t_r_addr = cache_hdr->tag_reg_addr;
3886        t_value = cache_hdr->addr_ctrl.init_tag_value;
3887        r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
3888        p_wait = cache_hdr->cache_ctrl.poll_wait;
3889        p_mask = cache_hdr->cache_ctrl.poll_mask;
3890
3891        for (i = 0; i < loop_count; i++) {
3892                qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
3893                if (c_value_w)
3894                        qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
3895
3896                if (p_mask) {
3897                        w_time = jiffies + p_wait;
3898                        do {
3899                                c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0);
3900                                if ((c_value_r & p_mask) == 0)
3901                                        break;
3902                                else if (time_after_eq(jiffies, w_time)) {
3903                                        /* capturing dump failed */
3904                                        ql_dbg(ql_dbg_p3p, vha, 0xb032,
3905                                            "c_value_r: 0x%x, poll_mask: 0x%lx, "
3906                                            "w_time: 0x%lx\n",
3907                                            c_value_r, p_mask, w_time);
3908                                        return rval;
3909                                }
3910                        } while (1);
3911                }
3912
3913                addr = r_addr;
3914                for (k = 0; k < r_cnt; k++) {
3915                        r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3916                        *data_ptr++ = cpu_to_le32(r_value);
3917                        addr += cache_hdr->read_ctrl.read_addr_stride;
3918                }
3919                t_value += cache_hdr->addr_ctrl.tag_value_stride;
3920        }
3921        *d_ptr = data_ptr;
3922        return QLA_SUCCESS;
3923}
3924
3925static void
3926qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha,
3927        qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
3928{
3929        struct qla_hw_data *ha = vha->hw;
3930        uint32_t addr, r_addr, c_addr, t_r_addr;
3931        uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3932        uint32_t c_value_w;
3933        struct qla82xx_md_entry_cache *cache_hdr;
3934        __le32 *data_ptr = *d_ptr;
3935
3936        cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
3937        loop_count = cache_hdr->op_count;
3938        r_addr = cache_hdr->read_addr;
3939        c_addr = cache_hdr->control_addr;
3940        c_value_w = cache_hdr->cache_ctrl.write_value;
3941
3942        t_r_addr = cache_hdr->tag_reg_addr;
3943        t_value = cache_hdr->addr_ctrl.init_tag_value;
3944        r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
3945
3946        for (i = 0; i < loop_count; i++) {
3947                qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
3948                qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
3949                addr = r_addr;
3950                for (k = 0; k < r_cnt; k++) {
3951                        r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3952                        *data_ptr++ = cpu_to_le32(r_value);
3953                        addr += cache_hdr->read_ctrl.read_addr_stride;
3954                }
3955                t_value += cache_hdr->addr_ctrl.tag_value_stride;
3956        }
3957        *d_ptr = data_ptr;
3958}
3959
3960static void
3961qla82xx_minidump_process_queue(scsi_qla_host_t *vha,
3962        qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
3963{
3964        struct qla_hw_data *ha = vha->hw;
3965        uint32_t s_addr, r_addr;
3966        uint32_t r_stride, r_value, r_cnt, qid = 0;
3967        uint32_t i, k, loop_cnt;
3968        struct qla82xx_md_entry_queue *q_hdr;
3969        __le32 *data_ptr = *d_ptr;
3970
3971        q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr;
3972        s_addr = q_hdr->select_addr;
3973        r_cnt = q_hdr->rd_strd.read_addr_cnt;
3974        r_stride = q_hdr->rd_strd.read_addr_stride;
3975        loop_cnt = q_hdr->op_count;
3976
3977        for (i = 0; i < loop_cnt; i++) {
3978                qla82xx_md_rw_32(ha, s_addr, qid, 1);
3979                r_addr = q_hdr->read_addr;
3980                for (k = 0; k < r_cnt; k++) {
3981                        r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3982                        *data_ptr++ = cpu_to_le32(r_value);
3983                        r_addr += r_stride;
3984                }
3985                qid += q_hdr->q_strd.queue_id_stride;
3986        }
3987        *d_ptr = data_ptr;
3988}
3989
3990static void
3991qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha,
3992        qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
3993{
3994        struct qla_hw_data *ha = vha->hw;
3995        uint32_t r_addr, r_value;
3996        uint32_t i, loop_cnt;
3997        struct qla82xx_md_entry_rdrom *rom_hdr;
3998        __le32 *data_ptr = *d_ptr;
3999
4000        rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr;
4001        r_addr = rom_hdr->read_addr;
4002        loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t);
4003
4004        for (i = 0; i < loop_cnt; i++) {
4005                qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW,
4006                    (r_addr & 0xFFFF0000), 1);
4007                r_value = qla82xx_md_rw_32(ha,
4008                    MD_DIRECT_ROM_READ_BASE +
4009                    (r_addr & 0x0000FFFF), 0, 0);
4010                *data_ptr++ = cpu_to_le32(r_value);
4011                r_addr += sizeof(uint32_t);
4012        }
4013        *d_ptr = data_ptr;
4014}
4015
4016static int
4017qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha,
4018        qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
4019{
4020        struct qla_hw_data *ha = vha->hw;
4021        uint32_t r_addr, r_value, r_data;
4022        uint32_t i, j, loop_cnt;
4023        struct qla82xx_md_entry_rdmem *m_hdr;
4024        unsigned long flags;
4025        int rval = QLA_FUNCTION_FAILED;
4026        __le32 *data_ptr = *d_ptr;
4027
4028        m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr;
4029        r_addr = m_hdr->read_addr;
4030        loop_cnt = m_hdr->read_data_size/16;
4031
4032        if (r_addr & 0xf) {
4033                ql_log(ql_log_warn, vha, 0xb033,
4034                    "Read addr 0x%x not 16 bytes aligned\n", r_addr);
4035                return rval;
4036        }
4037
4038        if (m_hdr->read_data_size % 16) {
4039                ql_log(ql_log_warn, vha, 0xb034,
4040                    "Read data[0x%x] not multiple of 16 bytes\n",
4041                    m_hdr->read_data_size);
4042                return rval;
4043        }
4044
4045        ql_dbg(ql_dbg_p3p, vha, 0xb035,
4046            "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
4047            __func__, r_addr, m_hdr->read_data_size, loop_cnt);
4048
4049        write_lock_irqsave(&ha->hw_lock, flags);
4050        for (i = 0; i < loop_cnt; i++) {
4051                qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1);
4052                r_value = 0;
4053                qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1);
4054                r_value = MIU_TA_CTL_ENABLE;
4055                qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
4056                r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
4057                qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
4058
4059                for (j = 0; j < MAX_CTL_CHECK; j++) {
4060                        r_value = qla82xx_md_rw_32(ha,
4061                            MD_MIU_TEST_AGT_CTRL, 0, 0);
4062                        if ((r_value & MIU_TA_CTL_BUSY) == 0)
4063                                break;
4064                }
4065
4066                if (j >= MAX_CTL_CHECK) {
4067                        printk_ratelimited(KERN_ERR
4068                            "failed to read through agent\n");
4069                        write_unlock_irqrestore(&ha->hw_lock, flags);
4070                        return rval;
4071                }
4072
4073                for (j = 0; j < 4; j++) {
4074                        r_data = qla82xx_md_rw_32(ha,
4075                            MD_MIU_TEST_AGT_RDDATA[j], 0, 0);
4076                        *data_ptr++ = cpu_to_le32(r_data);
4077                }
4078                r_addr += 16;
4079        }
4080        write_unlock_irqrestore(&ha->hw_lock, flags);
4081        *d_ptr = data_ptr;
4082        return QLA_SUCCESS;
4083}
4084
4085int
4086qla82xx_validate_template_chksum(scsi_qla_host_t *vha)
4087{
4088        struct qla_hw_data *ha = vha->hw;
4089        uint64_t chksum = 0;
4090        uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr;
4091        int count = ha->md_template_size/sizeof(uint32_t);
4092
4093        while (count-- > 0)
4094                chksum += *d_ptr++;
4095        while (chksum >> 32)
4096                chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32);
4097        return ~chksum;
4098}
4099
4100static void
4101qla82xx_mark_entry_skipped(scsi_qla_host_t *vha,
4102        qla82xx_md_entry_hdr_t *entry_hdr, int index)
4103{
4104        entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG;
4105        ql_dbg(ql_dbg_p3p, vha, 0xb036,
4106            "Skipping entry[%d]: "
4107            "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4108            index, entry_hdr->entry_type,
4109            entry_hdr->d_ctrl.entry_capture_mask);
4110}
4111
4112int
4113qla82xx_md_collect(scsi_qla_host_t *vha)
4114{
4115        struct qla_hw_data *ha = vha->hw;
4116        int no_entry_hdr = 0;
4117        qla82xx_md_entry_hdr_t *entry_hdr;
4118        struct qla82xx_md_template_hdr *tmplt_hdr;
4119        __le32 *data_ptr;
4120        uint32_t total_data_size = 0, f_capture_mask, data_collected = 0;
4121        int i = 0, rval = QLA_FUNCTION_FAILED;
4122
4123        tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
4124        data_ptr = ha->md_dump;
4125
4126        if (ha->fw_dumped) {
4127                ql_log(ql_log_warn, vha, 0xb037,
4128                    "Firmware has been previously dumped (%p) "
4129                    "-- ignoring request.\n", ha->fw_dump);
4130                goto md_failed;
4131        }
4132
4133        ha->fw_dumped = false;
4134
4135        if (!ha->md_tmplt_hdr || !ha->md_dump) {
4136                ql_log(ql_log_warn, vha, 0xb038,
4137                    "Memory not allocated for minidump capture\n");
4138                goto md_failed;
4139        }
4140
4141        if (ha->flags.isp82xx_no_md_cap) {
4142                ql_log(ql_log_warn, vha, 0xb054,
4143                    "Forced reset from application, "
4144                    "ignore minidump capture\n");
4145                ha->flags.isp82xx_no_md_cap = 0;
4146                goto md_failed;
4147        }
4148
4149        if (qla82xx_validate_template_chksum(vha)) {
4150                ql_log(ql_log_info, vha, 0xb039,
4151                    "Template checksum validation error\n");
4152                goto md_failed;
4153        }
4154
4155        no_entry_hdr = tmplt_hdr->num_of_entries;
4156        ql_dbg(ql_dbg_p3p, vha, 0xb03a,
4157            "No of entry headers in Template: 0x%x\n", no_entry_hdr);
4158
4159        ql_dbg(ql_dbg_p3p, vha, 0xb03b,
4160            "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level);
4161
4162        f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF;
4163
4164        /* Validate whether required debug level is set */
4165        if ((f_capture_mask & 0x3) != 0x3) {
4166                ql_log(ql_log_warn, vha, 0xb03c,
4167                    "Minimum required capture mask[0x%x] level not set\n",
4168                    f_capture_mask);
4169                goto md_failed;
4170        }
4171        tmplt_hdr->driver_capture_mask = ql2xmdcapmask;
4172
4173        tmplt_hdr->driver_info[0] = vha->host_no;
4174        tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) |
4175            (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) |
4176            QLA_DRIVER_BETA_VER;
4177
4178        total_data_size = ha->md_dump_size;
4179
4180        ql_dbg(ql_dbg_p3p, vha, 0xb03d,
4181            "Total minidump data_size 0x%x to be captured\n", total_data_size);
4182
4183        /* Check whether template obtained is valid */
4184        if (tmplt_hdr->entry_type != QLA82XX_TLHDR) {
4185                ql_log(ql_log_warn, vha, 0xb04e,
4186                    "Bad template header entry type: 0x%x obtained\n",
4187                    tmplt_hdr->entry_type);
4188                goto md_failed;
4189        }
4190
4191        entry_hdr = (qla82xx_md_entry_hdr_t *)
4192            (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset);
4193
4194        /* Walk through the entry headers */
4195        for (i = 0; i < no_entry_hdr; i++) {
4196
4197                if (data_collected > total_data_size) {
4198                        ql_log(ql_log_warn, vha, 0xb03e,
4199                            "More MiniDump data collected: [0x%x]\n",
4200                            data_collected);
4201                        goto md_failed;
4202                }
4203
4204                if (!(entry_hdr->d_ctrl.entry_capture_mask &
4205                    ql2xmdcapmask)) {
4206                        entry_hdr->d_ctrl.driver_flags |=
4207                            QLA82XX_DBG_SKIPPED_FLAG;
4208                        ql_dbg(ql_dbg_p3p, vha, 0xb03f,
4209                            "Skipping entry[%d]: "
4210                            "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4211                            i, entry_hdr->entry_type,
4212                            entry_hdr->d_ctrl.entry_capture_mask);
4213                        goto