linux/drivers/irqchip/irq-tb10x.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Abilis Systems interrupt controller driver
   4 *
   5 * Copyright (C) Abilis Systems 2012
   6 *
   7 * Author: Christian Ruppert <christian.ruppert@abilis.com>
   8 */
   9
  10#include <linux/interrupt.h>
  11#include <linux/irqdomain.h>
  12#include <linux/irq.h>
  13#include <linux/irqchip.h>
  14#include <linux/of_irq.h>
  15#include <linux/of_address.h>
  16#include <linux/of_platform.h>
  17#include <linux/io.h>
  18#include <linux/slab.h>
  19#include <linux/bitops.h>
  20
  21#define AB_IRQCTL_INT_ENABLE   0x00
  22#define AB_IRQCTL_INT_STATUS   0x04
  23#define AB_IRQCTL_SRC_MODE     0x08
  24#define AB_IRQCTL_SRC_POLARITY 0x0C
  25#define AB_IRQCTL_INT_MODE     0x10
  26#define AB_IRQCTL_INT_POLARITY 0x14
  27#define AB_IRQCTL_INT_FORCE    0x18
  28
  29#define AB_IRQCTL_MAXIRQ       32
  30
  31static inline void ab_irqctl_writereg(struct irq_chip_generic *gc, u32 reg,
  32        u32 val)
  33{
  34        irq_reg_writel(gc, val, reg);
  35}
  36
  37static inline u32 ab_irqctl_readreg(struct irq_chip_generic *gc, u32 reg)
  38{
  39        return irq_reg_readl(gc, reg);
  40}
  41
  42static int tb10x_irq_set_type(struct irq_data *data, unsigned int flow_type)
  43{
  44        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
  45        uint32_t im, mod, pol;
  46
  47        im = data->mask;
  48
  49        irq_gc_lock(gc);
  50
  51        mod = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_MODE) | im;
  52        pol = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_POLARITY) | im;
  53
  54        switch (flow_type & IRQF_TRIGGER_MASK) {
  55        case IRQ_TYPE_EDGE_FALLING:
  56                pol ^= im;
  57                break;
  58        case IRQ_TYPE_LEVEL_HIGH:
  59                mod ^= im;
  60                break;
  61        case IRQ_TYPE_NONE:
  62                flow_type = IRQ_TYPE_LEVEL_LOW;
  63                fallthrough;
  64        case IRQ_TYPE_LEVEL_LOW:
  65                mod ^= im;
  66                pol ^= im;
  67                break;
  68        case IRQ_TYPE_EDGE_RISING:
  69                break;
  70        default:
  71                irq_gc_unlock(gc);
  72                pr_err("%s: Cannot assign multiple trigger modes to IRQ %d.\n",
  73                        __func__, data->irq);
  74                return -EBADR;
  75        }
  76
  77        irqd_set_trigger_type(data, flow_type);
  78        irq_setup_alt_chip(data, flow_type);
  79
  80        ab_irqctl_writereg(gc, AB_IRQCTL_SRC_MODE, mod);
  81        ab_irqctl_writereg(gc, AB_IRQCTL_SRC_POLARITY, pol);
  82        ab_irqctl_writereg(gc, AB_IRQCTL_INT_STATUS, im);
  83
  84        irq_gc_unlock(gc);
  85
  86        return IRQ_SET_MASK_OK;
  87}
  88
  89static void tb10x_irq_cascade(struct irq_desc *desc)
  90{
  91        struct irq_domain *domain = irq_desc_get_handler_data(desc);
  92        unsigned int irq = irq_desc_get_irq(desc);
  93
  94        generic_handle_irq(irq_find_mapping(domain, irq));
  95}
  96
  97static int __init of_tb10x_init_irq(struct device_node *ictl,
  98                                        struct device_node *parent)
  99{
 100        int i, ret, nrirqs = of_irq_count(ictl);
 101        struct resource mem;
 102        struct irq_chip_generic *gc;
 103        struct irq_domain *domain;
 104        void __iomem *reg_base;
 105
 106        if (of_address_to_resource(ictl, 0, &mem)) {
 107                pr_err("%pOFn: No registers declared in DeviceTree.\n",
 108                        ictl);
 109                return -EINVAL;
 110        }
 111
 112        if (!request_mem_region(mem.start, resource_size(&mem),
 113                ictl->full_name)) {
 114                pr_err("%pOFn: Request mem region failed.\n", ictl);
 115                return -EBUSY;
 116        }
 117
 118        reg_base = ioremap(mem.start, resource_size(&mem));
 119        if (!reg_base) {
 120                ret = -EBUSY;
 121                pr_err("%pOFn: ioremap failed.\n", ictl);
 122                goto ioremap_fail;
 123        }
 124
 125        domain = irq_domain_add_linear(ictl, AB_IRQCTL_MAXIRQ,
 126                                        &irq_generic_chip_ops, NULL);
 127        if (!domain) {
 128                ret = -ENOMEM;
 129                pr_err("%pOFn: Could not register interrupt domain.\n",
 130                        ictl);
 131                goto irq_domain_add_fail;
 132        }
 133
 134        ret = irq_alloc_domain_generic_chips(domain, AB_IRQCTL_MAXIRQ,
 135                                2, ictl->name, handle_level_irq,
 136                                IRQ_NOREQUEST, IRQ_NOPROBE,
 137                                IRQ_GC_INIT_MASK_CACHE);
 138        if (ret) {
 139                pr_err("%pOFn: Could not allocate generic interrupt chip.\n",
 140                        ictl);
 141                goto gc_alloc_fail;
 142        }
 143
 144        gc = domain->gc->gc[0];
 145        gc->reg_base                         = reg_base;
 146
 147        gc->chip_types[0].type               = IRQ_TYPE_LEVEL_MASK;
 148        gc->chip_types[0].chip.irq_mask      = irq_gc_mask_clr_bit;
 149        gc->chip_types[0].chip.irq_unmask    = irq_gc_mask_set_bit;
 150        gc->chip_types[0].chip.irq_set_type  = tb10x_irq_set_type;
 151        gc->chip_types[0].regs.mask          = AB_IRQCTL_INT_ENABLE;
 152
 153        gc->chip_types[1].type               = IRQ_TYPE_EDGE_BOTH;
 154        gc->chip_types[1].chip.name          = gc->chip_types[0].chip.name;
 155        gc->chip_types[1].chip.irq_ack       = irq_gc_ack_set_bit;
 156        gc->chip_types[1].chip.irq_mask      = irq_gc_mask_clr_bit;
 157        gc->chip_types[1].chip.irq_unmask    = irq_gc_mask_set_bit;
 158        gc->chip_types[1].chip.irq_set_type  = tb10x_irq_set_type;
 159        gc->chip_types[1].regs.ack           = AB_IRQCTL_INT_STATUS;
 160        gc->chip_types[1].regs.mask          = AB_IRQCTL_INT_ENABLE;
 161        gc->chip_types[1].handler            = handle_edge_irq;
 162
 163        for (i = 0; i < nrirqs; i++) {
 164                unsigned int irq = irq_of_parse_and_map(ictl, i);
 165
 166                irq_set_chained_handler_and_data(irq, tb10x_irq_cascade,
 167                                                 domain);
 168        }
 169
 170        ab_irqctl_writereg(gc, AB_IRQCTL_INT_ENABLE, 0);
 171        ab_irqctl_writereg(gc, AB_IRQCTL_INT_MODE, 0);
 172        ab_irqctl_writereg(gc, AB_IRQCTL_INT_POLARITY, 0);
 173        ab_irqctl_writereg(gc, AB_IRQCTL_INT_STATUS, ~0UL);
 174
 175        return 0;
 176
 177gc_alloc_fail:
 178        irq_domain_remove(domain);
 179irq_domain_add_fail:
 180        iounmap(reg_base);
 181ioremap_fail:
 182        release_mem_region(mem.start, resource_size(&mem));
 183        return ret;
 184}
 185IRQCHIP_DECLARE(tb10x_intc, "abilis,tb10x-ictl", of_tb10x_init_irq);
 186