linux/drivers/irqchip/irq-imx-irqsteer.c
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   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2017 NXP
   4 * Copyright (C) 2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
   5 */
   6
   7#include <linux/clk.h>
   8#include <linux/interrupt.h>
   9#include <linux/irq.h>
  10#include <linux/irqchip/chained_irq.h>
  11#include <linux/irqdomain.h>
  12#include <linux/kernel.h>
  13#include <linux/of_irq.h>
  14#include <linux/of_platform.h>
  15#include <linux/spinlock.h>
  16
  17#define CTRL_STRIDE_OFF(_t, _r) (_t * 4 * _r)
  18#define CHANCTRL                0x0
  19#define CHANMASK(n, t)          (CTRL_STRIDE_OFF(t, 0) + 0x4 * (n) + 0x4)
  20#define CHANSET(n, t)           (CTRL_STRIDE_OFF(t, 1) + 0x4 * (n) + 0x4)
  21#define CHANSTATUS(n, t)        (CTRL_STRIDE_OFF(t, 2) + 0x4 * (n) + 0x4)
  22#define CHAN_MINTDIS(t)         (CTRL_STRIDE_OFF(t, 3) + 0x4)
  23#define CHAN_MASTRSTAT(t)       (CTRL_STRIDE_OFF(t, 3) + 0x8)
  24
  25#define CHAN_MAX_OUTPUT_INT     0x8
  26
  27struct irqsteer_data {
  28        void __iomem            *regs;
  29        struct clk              *ipg_clk;
  30        int                     irq[CHAN_MAX_OUTPUT_INT];
  31        int                     irq_count;
  32        raw_spinlock_t          lock;
  33        int                     reg_num;
  34        int                     channel;
  35        struct irq_domain       *domain;
  36        u32                     *saved_reg;
  37};
  38
  39static int imx_irqsteer_get_reg_index(struct irqsteer_data *data,
  40                                      unsigned long irqnum)
  41{
  42        return (data->reg_num - irqnum / 32 - 1);
  43}
  44
  45static void imx_irqsteer_irq_unmask(struct irq_data *d)
  46{
  47        struct irqsteer_data *data = d->chip_data;
  48        int idx = imx_irqsteer_get_reg_index(data, d->hwirq);
  49        unsigned long flags;
  50        u32 val;
  51
  52        raw_spin_lock_irqsave(&data->lock, flags);
  53        val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num));
  54        val |= BIT(d->hwirq % 32);
  55        writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));
  56        raw_spin_unlock_irqrestore(&data->lock, flags);
  57}
  58
  59static void imx_irqsteer_irq_mask(struct irq_data *d)
  60{
  61        struct irqsteer_data *data = d->chip_data;
  62        int idx = imx_irqsteer_get_reg_index(data, d->hwirq);
  63        unsigned long flags;
  64        u32 val;
  65
  66        raw_spin_lock_irqsave(&data->lock, flags);
  67        val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num));
  68        val &= ~BIT(d->hwirq % 32);
  69        writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));
  70        raw_spin_unlock_irqrestore(&data->lock, flags);
  71}
  72
  73static struct irq_chip imx_irqsteer_irq_chip = {
  74        .name           = "irqsteer",
  75        .irq_mask       = imx_irqsteer_irq_mask,
  76        .irq_unmask     = imx_irqsteer_irq_unmask,
  77};
  78
  79static int imx_irqsteer_irq_map(struct irq_domain *h, unsigned int irq,
  80                                irq_hw_number_t hwirq)
  81{
  82        irq_set_status_flags(irq, IRQ_LEVEL);
  83        irq_set_chip_data(irq, h->host_data);
  84        irq_set_chip_and_handler(irq, &imx_irqsteer_irq_chip, handle_level_irq);
  85
  86        return 0;
  87}
  88
  89static const struct irq_domain_ops imx_irqsteer_domain_ops = {
  90        .map            = imx_irqsteer_irq_map,
  91        .xlate          = irq_domain_xlate_onecell,
  92};
  93
  94static int imx_irqsteer_get_hwirq_base(struct irqsteer_data *data, u32 irq)
  95{
  96        int i;
  97
  98        for (i = 0; i < data->irq_count; i++) {
  99                if (data->irq[i] == irq)
 100                        return i * 64;
 101        }
 102
 103        return -EINVAL;
 104}
 105
 106static void imx_irqsteer_irq_handler(struct irq_desc *desc)
 107{
 108        struct irqsteer_data *data = irq_desc_get_handler_data(desc);
 109        int hwirq;
 110        int irq, i;
 111
 112        chained_irq_enter(irq_desc_get_chip(desc), desc);
 113
 114        irq = irq_desc_get_irq(desc);
 115        hwirq = imx_irqsteer_get_hwirq_base(data, irq);
 116        if (hwirq < 0) {
 117                pr_warn("%s: unable to get hwirq base for irq %d\n",
 118                        __func__, irq);
 119                return;
 120        }
 121
 122        for (i = 0; i < 2; i++, hwirq += 32) {
 123                int idx = imx_irqsteer_get_reg_index(data, hwirq);
 124                unsigned long irqmap;
 125                int pos, virq;
 126
 127                if (hwirq >= data->reg_num * 32)
 128                        break;
 129
 130                irqmap = readl_relaxed(data->regs +
 131                                       CHANSTATUS(idx, data->reg_num));
 132
 133                for_each_set_bit(pos, &irqmap, 32) {
 134                        virq = irq_find_mapping(data->domain, pos + hwirq);
 135                        if (virq)
 136                                generic_handle_irq(virq);
 137                }
 138        }
 139
 140        chained_irq_exit(irq_desc_get_chip(desc), desc);
 141}
 142
 143static int imx_irqsteer_probe(struct platform_device *pdev)
 144{
 145        struct device_node *np = pdev->dev.of_node;
 146        struct irqsteer_data *data;
 147        u32 irqs_num;
 148        int i, ret;
 149
 150        data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
 151        if (!data)
 152                return -ENOMEM;
 153
 154        data->regs = devm_platform_ioremap_resource(pdev, 0);
 155        if (IS_ERR(data->regs)) {
 156                dev_err(&pdev->dev, "failed to initialize reg\n");
 157                return PTR_ERR(data->regs);
 158        }
 159
 160        data->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
 161        if (IS_ERR(data->ipg_clk))
 162                return dev_err_probe(&pdev->dev, PTR_ERR(data->ipg_clk),
 163                                     "failed to get ipg clk\n");
 164
 165        raw_spin_lock_init(&data->lock);
 166
 167        ret = of_property_read_u32(np, "fsl,num-irqs", &irqs_num);
 168        if (ret)
 169                return ret;
 170        ret = of_property_read_u32(np, "fsl,channel", &data->channel);
 171        if (ret)
 172                return ret;
 173
 174        /*
 175         * There is one output irq for each group of 64 inputs.
 176         * One register bit map can represent 32 input interrupts.
 177         */
 178        data->irq_count = DIV_ROUND_UP(irqs_num, 64);
 179        data->reg_num = irqs_num / 32;
 180
 181        if (IS_ENABLED(CONFIG_PM_SLEEP)) {
 182                data->saved_reg = devm_kzalloc(&pdev->dev,
 183                                        sizeof(u32) * data->reg_num,
 184                                        GFP_KERNEL);
 185                if (!data->saved_reg)
 186                        return -ENOMEM;
 187        }
 188
 189        ret = clk_prepare_enable(data->ipg_clk);
 190        if (ret) {
 191                dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret);
 192                return ret;
 193        }
 194
 195        /* steer all IRQs into configured channel */
 196        writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);
 197
 198        data->domain = irq_domain_add_linear(np, data->reg_num * 32,
 199                                             &imx_irqsteer_domain_ops, data);
 200        if (!data->domain) {
 201                dev_err(&pdev->dev, "failed to create IRQ domain\n");
 202                ret = -ENOMEM;
 203                goto out;
 204        }
 205
 206        if (!data->irq_count || data->irq_count > CHAN_MAX_OUTPUT_INT) {
 207                ret = -EINVAL;
 208                goto out;
 209        }
 210
 211        for (i = 0; i < data->irq_count; i++) {
 212                data->irq[i] = irq_of_parse_and_map(np, i);
 213                if (!data->irq[i]) {
 214                        ret = -EINVAL;
 215                        goto out;
 216                }
 217
 218                irq_set_chained_handler_and_data(data->irq[i],
 219                                                 imx_irqsteer_irq_handler,
 220                                                 data);
 221        }
 222
 223        platform_set_drvdata(pdev, data);
 224
 225        return 0;
 226out:
 227        clk_disable_unprepare(data->ipg_clk);
 228        return ret;
 229}
 230
 231static int imx_irqsteer_remove(struct platform_device *pdev)
 232{
 233        struct irqsteer_data *irqsteer_data = platform_get_drvdata(pdev);
 234        int i;
 235
 236        for (i = 0; i < irqsteer_data->irq_count; i++)
 237                irq_set_chained_handler_and_data(irqsteer_data->irq[i],
 238                                                 NULL, NULL);
 239
 240        irq_domain_remove(irqsteer_data->domain);
 241
 242        clk_disable_unprepare(irqsteer_data->ipg_clk);
 243
 244        return 0;
 245}
 246
 247#ifdef CONFIG_PM_SLEEP
 248static void imx_irqsteer_save_regs(struct irqsteer_data *data)
 249{
 250        int i;
 251
 252        for (i = 0; i < data->reg_num; i++)
 253                data->saved_reg[i] = readl_relaxed(data->regs +
 254                                                CHANMASK(i, data->reg_num));
 255}
 256
 257static void imx_irqsteer_restore_regs(struct irqsteer_data *data)
 258{
 259        int i;
 260
 261        writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);
 262        for (i = 0; i < data->reg_num; i++)
 263                writel_relaxed(data->saved_reg[i],
 264                               data->regs + CHANMASK(i, data->reg_num));
 265}
 266
 267static int imx_irqsteer_suspend(struct device *dev)
 268{
 269        struct irqsteer_data *irqsteer_data = dev_get_drvdata(dev);
 270
 271        imx_irqsteer_save_regs(irqsteer_data);
 272        clk_disable_unprepare(irqsteer_data->ipg_clk);
 273
 274        return 0;
 275}
 276
 277static int imx_irqsteer_resume(struct device *dev)
 278{
 279        struct irqsteer_data *irqsteer_data = dev_get_drvdata(dev);
 280        int ret;
 281
 282        ret = clk_prepare_enable(irqsteer_data->ipg_clk);
 283        if (ret) {
 284                dev_err(dev, "failed to enable ipg clk: %d\n", ret);
 285                return ret;
 286        }
 287        imx_irqsteer_restore_regs(irqsteer_data);
 288
 289        return 0;
 290}
 291#endif
 292
 293static const struct dev_pm_ops imx_irqsteer_pm_ops = {
 294        SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_irqsteer_suspend, imx_irqsteer_resume)
 295};
 296
 297static const struct of_device_id imx_irqsteer_dt_ids[] = {
 298        { .compatible = "fsl,imx-irqsteer", },
 299        {},
 300};
 301
 302static struct platform_driver imx_irqsteer_driver = {
 303        .driver = {
 304                .name = "imx-irqsteer",
 305                .of_match_table = imx_irqsteer_dt_ids,
 306                .pm = &imx_irqsteer_pm_ops,
 307        },
 308        .probe = imx_irqsteer_probe,
 309        .remove = imx_irqsteer_remove,
 310};
 311builtin_platform_driver(imx_irqsteer_driver);
 312