linux/drivers/irqchip/irq-bcm7120-l2.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Broadcom BCM7120 style Level 2 interrupt controller driver
   4 *
   5 * Copyright (C) 2014 Broadcom Corporation
   6 */
   7
   8#define pr_fmt(fmt)     KBUILD_MODNAME  ": " fmt
   9
  10#include <linux/init.h>
  11#include <linux/slab.h>
  12#include <linux/module.h>
  13#include <linux/kernel.h>
  14#include <linux/platform_device.h>
  15#include <linux/of.h>
  16#include <linux/of_irq.h>
  17#include <linux/of_address.h>
  18#include <linux/of_platform.h>
  19#include <linux/interrupt.h>
  20#include <linux/irq.h>
  21#include <linux/io.h>
  22#include <linux/irqdomain.h>
  23#include <linux/reboot.h>
  24#include <linux/bitops.h>
  25#include <linux/irqchip.h>
  26#include <linux/irqchip/chained_irq.h>
  27
  28/* Register offset in the L2 interrupt controller */
  29#define IRQEN           0x00
  30#define IRQSTAT         0x04
  31
  32#define MAX_WORDS       4
  33#define MAX_MAPPINGS    (MAX_WORDS * 2)
  34#define IRQS_PER_WORD   32
  35
  36struct bcm7120_l1_intc_data {
  37        struct bcm7120_l2_intc_data *b;
  38        u32 irq_map_mask[MAX_WORDS];
  39};
  40
  41struct bcm7120_l2_intc_data {
  42        unsigned int n_words;
  43        void __iomem *map_base[MAX_MAPPINGS];
  44        void __iomem *pair_base[MAX_WORDS];
  45        int en_offset[MAX_WORDS];
  46        int stat_offset[MAX_WORDS];
  47        struct irq_domain *domain;
  48        bool can_wake;
  49        u32 irq_fwd_mask[MAX_WORDS];
  50        struct bcm7120_l1_intc_data *l1_data;
  51        int num_parent_irqs;
  52        const __be32 *map_mask_prop;
  53};
  54
  55static void bcm7120_l2_intc_irq_handle(struct irq_desc *desc)
  56{
  57        struct bcm7120_l1_intc_data *data = irq_desc_get_handler_data(desc);
  58        struct bcm7120_l2_intc_data *b = data->b;
  59        struct irq_chip *chip = irq_desc_get_chip(desc);
  60        unsigned int idx;
  61
  62        chained_irq_enter(chip, desc);
  63
  64        for (idx = 0; idx < b->n_words; idx++) {
  65                int base = idx * IRQS_PER_WORD;
  66                struct irq_chip_generic *gc =
  67                        irq_get_domain_generic_chip(b->domain, base);
  68                unsigned long pending;
  69                int hwirq;
  70
  71                irq_gc_lock(gc);
  72                pending = irq_reg_readl(gc, b->stat_offset[idx]) &
  73                                            gc->mask_cache &
  74                                            data->irq_map_mask[idx];
  75                irq_gc_unlock(gc);
  76
  77                for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
  78                        generic_handle_irq(irq_find_mapping(b->domain,
  79                                           base + hwirq));
  80                }
  81        }
  82
  83        chained_irq_exit(chip, desc);
  84}
  85
  86static void bcm7120_l2_intc_suspend(struct irq_chip_generic *gc)
  87{
  88        struct bcm7120_l2_intc_data *b = gc->private;
  89        struct irq_chip_type *ct = gc->chip_types;
  90
  91        irq_gc_lock(gc);
  92        if (b->can_wake)
  93                irq_reg_writel(gc, gc->mask_cache | gc->wake_active,
  94                               ct->regs.mask);
  95        irq_gc_unlock(gc);
  96}
  97
  98static void bcm7120_l2_intc_resume(struct irq_chip_generic *gc)
  99{
 100        struct irq_chip_type *ct = gc->chip_types;
 101
 102        /* Restore the saved mask */
 103        irq_gc_lock(gc);
 104        irq_reg_writel(gc, gc->mask_cache, ct->regs.mask);
 105        irq_gc_unlock(gc);
 106}
 107
 108static int bcm7120_l2_intc_init_one(struct device_node *dn,
 109                                        struct bcm7120_l2_intc_data *data,
 110                                        int irq, u32 *valid_mask)
 111{
 112        struct bcm7120_l1_intc_data *l1_data = &data->l1_data[irq];
 113        int parent_irq;
 114        unsigned int idx;
 115
 116        parent_irq = irq_of_parse_and_map(dn, irq);
 117        if (!parent_irq) {
 118                pr_err("failed to map interrupt %d\n", irq);
 119                return -EINVAL;
 120        }
 121
 122        /* For multiple parent IRQs with multiple words, this looks like:
 123         * <irq0_w0 irq0_w1 irq1_w0 irq1_w1 ...>
 124         *
 125         * We need to associate a given parent interrupt with its corresponding
 126         * map_mask in order to mask the status register with it because we
 127         * have the same handler being called for multiple parent interrupts.
 128         *
 129         * This is typically something needed on BCM7xxx (STB chips).
 130         */
 131        for (idx = 0; idx < data->n_words; idx++) {
 132                if (data->map_mask_prop) {
 133                        l1_data->irq_map_mask[idx] |=
 134                                be32_to_cpup(data->map_mask_prop +
 135                                             irq * data->n_words + idx);
 136                } else {
 137                        l1_data->irq_map_mask[idx] = 0xffffffff;
 138                }
 139                valid_mask[idx] |= l1_data->irq_map_mask[idx];
 140        }
 141
 142        l1_data->b = data;
 143
 144        irq_set_chained_handler_and_data(parent_irq,
 145                                         bcm7120_l2_intc_irq_handle, l1_data);
 146        if (data->can_wake)
 147                enable_irq_wake(parent_irq);
 148
 149        return 0;
 150}
 151
 152static int __init bcm7120_l2_intc_iomap_7120(struct device_node *dn,
 153                                             struct bcm7120_l2_intc_data *data)
 154{
 155        int ret;
 156
 157        data->map_base[0] = of_iomap(dn, 0);
 158        if (!data->map_base[0]) {
 159                pr_err("unable to map registers\n");
 160                return -ENOMEM;
 161        }
 162
 163        data->pair_base[0] = data->map_base[0];
 164        data->en_offset[0] = IRQEN;
 165        data->stat_offset[0] = IRQSTAT;
 166        data->n_words = 1;
 167
 168        ret = of_property_read_u32_array(dn, "brcm,int-fwd-mask",
 169                                         data->irq_fwd_mask, data->n_words);
 170        if (ret != 0 && ret != -EINVAL) {
 171                /* property exists but has the wrong number of words */
 172                pr_err("invalid brcm,int-fwd-mask property\n");
 173                return -EINVAL;
 174        }
 175
 176        data->map_mask_prop = of_get_property(dn, "brcm,int-map-mask", &ret);
 177        if (!data->map_mask_prop ||
 178            (ret != (sizeof(__be32) * data->num_parent_irqs * data->n_words))) {
 179                pr_err("invalid brcm,int-map-mask property\n");
 180                return -EINVAL;
 181        }
 182
 183        return 0;
 184}
 185
 186static int __init bcm7120_l2_intc_iomap_3380(struct device_node *dn,
 187                                             struct bcm7120_l2_intc_data *data)
 188{
 189        unsigned int gc_idx;
 190
 191        for (gc_idx = 0; gc_idx < MAX_WORDS; gc_idx++) {
 192                unsigned int map_idx = gc_idx * 2;
 193                void __iomem *en = of_iomap(dn, map_idx + 0);
 194                void __iomem *stat = of_iomap(dn, map_idx + 1);
 195                void __iomem *base = min(en, stat);
 196
 197                data->map_base[map_idx + 0] = en;
 198                data->map_base[map_idx + 1] = stat;
 199
 200                if (!base)
 201                        break;
 202
 203                data->pair_base[gc_idx] = base;
 204                data->en_offset[gc_idx] = en - base;
 205                data->stat_offset[gc_idx] = stat - base;
 206        }
 207
 208        if (!gc_idx) {
 209                pr_err("unable to map registers\n");
 210                return -EINVAL;
 211        }
 212
 213        data->n_words = gc_idx;
 214        return 0;
 215}
 216
 217static int __init bcm7120_l2_intc_probe(struct device_node *dn,
 218                                 struct device_node *parent,
 219                                 int (*iomap_regs_fn)(struct device_node *,
 220                                        struct bcm7120_l2_intc_data *),
 221                                 const char *intc_name)
 222{
 223        unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
 224        struct bcm7120_l2_intc_data *data;
 225        struct irq_chip_generic *gc;
 226        struct irq_chip_type *ct;
 227        int ret = 0;
 228        unsigned int idx, irq, flags;
 229        u32 valid_mask[MAX_WORDS] = { };
 230
 231        data = kzalloc(sizeof(*data), GFP_KERNEL);
 232        if (!data)
 233                return -ENOMEM;
 234
 235        data->num_parent_irqs = of_irq_count(dn);
 236        if (data->num_parent_irqs <= 0) {
 237                pr_err("invalid number of parent interrupts\n");
 238                ret = -ENOMEM;
 239                goto out_unmap;
 240        }
 241
 242        data->l1_data = kcalloc(data->num_parent_irqs, sizeof(*data->l1_data),
 243                                GFP_KERNEL);
 244        if (!data->l1_data) {
 245                ret = -ENOMEM;
 246                goto out_free_l1_data;
 247        }
 248
 249        ret = iomap_regs_fn(dn, data);
 250        if (ret < 0)
 251                goto out_free_l1_data;
 252
 253        data->can_wake = of_property_read_bool(dn, "brcm,irq-can-wake");
 254
 255        for (irq = 0; irq < data->num_parent_irqs; irq++) {
 256                ret = bcm7120_l2_intc_init_one(dn, data, irq, valid_mask);
 257                if (ret)
 258                        goto out_free_l1_data;
 259        }
 260
 261        data->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * data->n_words,
 262                                             &irq_generic_chip_ops, NULL);
 263        if (!data->domain) {
 264                ret = -ENOMEM;
 265                goto out_free_l1_data;
 266        }
 267
 268        /* MIPS chips strapped for BE will automagically configure the
 269         * peripheral registers for CPU-native byte order.
 270         */
 271        flags = IRQ_GC_INIT_MASK_CACHE;
 272        if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
 273                flags |= IRQ_GC_BE_IO;
 274
 275        ret = irq_alloc_domain_generic_chips(data->domain, IRQS_PER_WORD, 1,
 276                                dn->full_name, handle_level_irq, clr, 0, flags);
 277        if (ret) {
 278                pr_err("failed to allocate generic irq chip\n");
 279                goto out_free_domain;
 280        }
 281
 282        for (idx = 0; idx < data->n_words; idx++) {
 283                irq = idx * IRQS_PER_WORD;
 284                gc = irq_get_domain_generic_chip(data->domain, irq);
 285
 286                gc->unused = 0xffffffff & ~valid_mask[idx];
 287                gc->private = data;
 288                ct = gc->chip_types;
 289
 290                gc->reg_base = data->pair_base[idx];
 291                ct->regs.mask = data->en_offset[idx];
 292
 293                /* gc->reg_base is defined and so is gc->writel */
 294                irq_reg_writel(gc, data->irq_fwd_mask[idx],
 295                               data->en_offset[idx]);
 296
 297                ct->chip.irq_mask = irq_gc_mask_clr_bit;
 298                ct->chip.irq_unmask = irq_gc_mask_set_bit;
 299                ct->chip.irq_ack = irq_gc_noop;
 300                gc->suspend = bcm7120_l2_intc_suspend;
 301                gc->resume = bcm7120_l2_intc_resume;
 302
 303                /*
 304                 * Initialize mask-cache, in case we need it for
 305                 * saving/restoring fwd mask even w/o any child interrupts
 306                 * installed
 307                 */
 308                gc->mask_cache = irq_reg_readl(gc, ct->regs.mask);
 309
 310                if (data->can_wake) {
 311                        /* This IRQ chip can wake the system, set all
 312                         * relevant child interrupts in wake_enabled mask
 313                         */
 314                        gc->wake_enabled = 0xffffffff;
 315                        gc->wake_enabled &= ~gc->unused;
 316                        ct->chip.irq_set_wake = irq_gc_set_wake;
 317                }
 318        }
 319
 320        pr_info("registered %s intc (%pOF, parent IRQ(s): %d)\n",
 321                intc_name, dn, data->num_parent_irqs);
 322
 323        return 0;
 324
 325out_free_domain:
 326        irq_domain_remove(data->domain);
 327out_free_l1_data:
 328        kfree(data->l1_data);
 329out_unmap:
 330        for (idx = 0; idx < MAX_MAPPINGS; idx++) {
 331                if (data->map_base[idx])
 332                        iounmap(data->map_base[idx]);
 333        }
 334        kfree(data);
 335        return ret;
 336}
 337
 338static int __init bcm7120_l2_intc_probe_7120(struct device_node *dn,
 339                                             struct device_node *parent)
 340{
 341        return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_7120,
 342                                     "BCM7120 L2");
 343}
 344
 345static int __init bcm7120_l2_intc_probe_3380(struct device_node *dn,
 346                                             struct device_node *parent)
 347{
 348        return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_3380,
 349                                     "BCM3380 L2");
 350}
 351
 352IRQCHIP_DECLARE(bcm7120_l2_intc, "brcm,bcm7120-l2-intc",
 353                bcm7120_l2_intc_probe_7120);
 354
 355IRQCHIP_DECLARE(bcm3380_l2_intc, "brcm,bcm3380-l2-intc",
 356                bcm7120_l2_intc_probe_3380);
 357