linux/drivers/edac/skx_common.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 *
   4 * Shared code by both skx_edac and i10nm_edac. Originally split out
   5 * from the skx_edac driver.
   6 *
   7 * This file is linked into both skx_edac and i10nm_edac drivers. In
   8 * order to avoid link errors, this file must be like a pure library
   9 * without including symbols and defines which would otherwise conflict,
  10 * when linked once into a module and into a built-in object, at the
  11 * same time. For example, __this_module symbol references when that
  12 * file is being linked into a built-in object.
  13 *
  14 * Copyright (c) 2018, Intel Corporation.
  15 */
  16
  17#include <linux/acpi.h>
  18#include <linux/dmi.h>
  19#include <linux/adxl.h>
  20#include <acpi/nfit.h>
  21#include <asm/mce.h>
  22#include "edac_module.h"
  23#include "skx_common.h"
  24
  25static const char * const component_names[] = {
  26        [INDEX_SOCKET]  = "ProcessorSocketId",
  27        [INDEX_MEMCTRL] = "MemoryControllerId",
  28        [INDEX_CHANNEL] = "ChannelId",
  29        [INDEX_DIMM]    = "DimmSlotId",
  30};
  31
  32static int component_indices[ARRAY_SIZE(component_names)];
  33static int adxl_component_count;
  34static const char * const *adxl_component_names;
  35static u64 *adxl_values;
  36static char *adxl_msg;
  37
  38static char skx_msg[MSG_SIZE];
  39static skx_decode_f skx_decode;
  40static skx_show_retry_log_f skx_show_retry_rd_err_log;
  41static u64 skx_tolm, skx_tohm;
  42static LIST_HEAD(dev_edac_list);
  43
  44int __init skx_adxl_get(void)
  45{
  46        const char * const *names;
  47        int i, j;
  48
  49        names = adxl_get_component_names();
  50        if (!names) {
  51                skx_printk(KERN_NOTICE, "No firmware support for address translation.\n");
  52                return -ENODEV;
  53        }
  54
  55        for (i = 0; i < INDEX_MAX; i++) {
  56                for (j = 0; names[j]; j++) {
  57                        if (!strcmp(component_names[i], names[j])) {
  58                                component_indices[i] = j;
  59                                break;
  60                        }
  61                }
  62
  63                if (!names[j])
  64                        goto err;
  65        }
  66
  67        adxl_component_names = names;
  68        while (*names++)
  69                adxl_component_count++;
  70
  71        adxl_values = kcalloc(adxl_component_count, sizeof(*adxl_values),
  72                              GFP_KERNEL);
  73        if (!adxl_values) {
  74                adxl_component_count = 0;
  75                return -ENOMEM;
  76        }
  77
  78        adxl_msg = kzalloc(MSG_SIZE, GFP_KERNEL);
  79        if (!adxl_msg) {
  80                adxl_component_count = 0;
  81                kfree(adxl_values);
  82                return -ENOMEM;
  83        }
  84
  85        return 0;
  86err:
  87        skx_printk(KERN_ERR, "'%s' is not matched from DSM parameters: ",
  88                   component_names[i]);
  89        for (j = 0; names[j]; j++)
  90                skx_printk(KERN_CONT, "%s ", names[j]);
  91        skx_printk(KERN_CONT, "\n");
  92
  93        return -ENODEV;
  94}
  95
  96void __exit skx_adxl_put(void)
  97{
  98        kfree(adxl_values);
  99        kfree(adxl_msg);
 100}
 101
 102static bool skx_adxl_decode(struct decoded_addr *res)
 103{
 104        struct skx_dev *d;
 105        int i, len = 0;
 106
 107        if (res->addr >= skx_tohm || (res->addr >= skx_tolm &&
 108                                      res->addr < BIT_ULL(32))) {
 109                edac_dbg(0, "Address 0x%llx out of range\n", res->addr);
 110                return false;
 111        }
 112
 113        if (adxl_decode(res->addr, adxl_values)) {
 114                edac_dbg(0, "Failed to decode 0x%llx\n", res->addr);
 115                return false;
 116        }
 117
 118        res->socket  = (int)adxl_values[component_indices[INDEX_SOCKET]];
 119        res->imc     = (int)adxl_values[component_indices[INDEX_MEMCTRL]];
 120        res->channel = (int)adxl_values[component_indices[INDEX_CHANNEL]];
 121        res->dimm    = (int)adxl_values[component_indices[INDEX_DIMM]];
 122
 123        if (res->imc > NUM_IMC - 1) {
 124                skx_printk(KERN_ERR, "Bad imc %d\n", res->imc);
 125                return false;
 126        }
 127
 128        list_for_each_entry(d, &dev_edac_list, list) {
 129                if (d->imc[0].src_id == res->socket) {
 130                        res->dev = d;
 131                        break;
 132                }
 133        }
 134
 135        if (!res->dev) {
 136                skx_printk(KERN_ERR, "No device for src_id %d imc %d\n",
 137                           res->socket, res->imc);
 138                return false;
 139        }
 140
 141        for (i = 0; i < adxl_component_count; i++) {
 142                if (adxl_values[i] == ~0x0ull)
 143                        continue;
 144
 145                len += snprintf(adxl_msg + len, MSG_SIZE - len, " %s:0x%llx",
 146                                adxl_component_names[i], adxl_values[i]);
 147                if (MSG_SIZE - len <= 0)
 148                        break;
 149        }
 150
 151        return true;
 152}
 153
 154void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log)
 155{
 156        skx_decode = decode;
 157        skx_show_retry_rd_err_log = show_retry_log;
 158}
 159
 160int skx_get_src_id(struct skx_dev *d, int off, u8 *id)
 161{
 162        u32 reg;
 163
 164        if (pci_read_config_dword(d->util_all, off, &reg)) {
 165                skx_printk(KERN_ERR, "Failed to read src id\n");
 166                return -ENODEV;
 167        }
 168
 169        *id = GET_BITFIELD(reg, 12, 14);
 170        return 0;
 171}
 172
 173int skx_get_node_id(struct skx_dev *d, u8 *id)
 174{
 175        u32 reg;
 176
 177        if (pci_read_config_dword(d->util_all, 0xf4, &reg)) {
 178                skx_printk(KERN_ERR, "Failed to read node id\n");
 179                return -ENODEV;
 180        }
 181
 182        *id = GET_BITFIELD(reg, 0, 2);
 183        return 0;
 184}
 185
 186static int get_width(u32 mtr)
 187{
 188        switch (GET_BITFIELD(mtr, 8, 9)) {
 189        case 0:
 190                return DEV_X4;
 191        case 1:
 192                return DEV_X8;
 193        case 2:
 194                return DEV_X16;
 195        }
 196        return DEV_UNKNOWN;
 197}
 198
 199/*
 200 * We use the per-socket device @cfg->did to count how many sockets are present,
 201 * and to detemine which PCI buses are associated with each socket. Allocate
 202 * and build the full list of all the skx_dev structures that we need here.
 203 */
 204int skx_get_all_bus_mappings(struct res_config *cfg, struct list_head **list)
 205{
 206        struct pci_dev *pdev, *prev;
 207        struct skx_dev *d;
 208        u32 reg;
 209        int ndev = 0;
 210
 211        prev = NULL;
 212        for (;;) {
 213                pdev = pci_get_device(PCI_VENDOR_ID_INTEL, cfg->decs_did, prev);
 214                if (!pdev)
 215                        break;
 216                ndev++;
 217                d = kzalloc(sizeof(*d), GFP_KERNEL);
 218                if (!d) {
 219                        pci_dev_put(pdev);
 220                        return -ENOMEM;
 221                }
 222
 223                if (pci_read_config_dword(pdev, cfg->busno_cfg_offset, &reg)) {
 224                        kfree(d);
 225                        pci_dev_put(pdev);
 226                        skx_printk(KERN_ERR, "Failed to read bus idx\n");
 227                        return -ENODEV;
 228                }
 229
 230                d->bus[0] = GET_BITFIELD(reg, 0, 7);
 231                d->bus[1] = GET_BITFIELD(reg, 8, 15);
 232                if (cfg->type == SKX) {
 233                        d->seg = pci_domain_nr(pdev->bus);
 234                        d->bus[2] = GET_BITFIELD(reg, 16, 23);
 235                        d->bus[3] = GET_BITFIELD(reg, 24, 31);
 236                } else {
 237                        d->seg = GET_BITFIELD(reg, 16, 23);
 238                }
 239
 240                edac_dbg(2, "busses: 0x%x, 0x%x, 0x%x, 0x%x\n",
 241                         d->bus[0], d->bus[1], d->bus[2], d->bus[3]);
 242                list_add_tail(&d->list, &dev_edac_list);
 243                prev = pdev;
 244        }
 245
 246        if (list)
 247                *list = &dev_edac_list;
 248        return ndev;
 249}
 250
 251int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm)
 252{
 253        struct pci_dev *pdev;
 254        u32 reg;
 255
 256        pdev = pci_get_device(PCI_VENDOR_ID_INTEL, did, NULL);
 257        if (!pdev) {
 258                edac_dbg(2, "Can't get tolm/tohm\n");
 259                return -ENODEV;
 260        }
 261
 262        if (pci_read_config_dword(pdev, off[0], &reg)) {
 263                skx_printk(KERN_ERR, "Failed to read tolm\n");
 264                goto fail;
 265        }
 266        skx_tolm = reg;
 267
 268        if (pci_read_config_dword(pdev, off[1], &reg)) {
 269                skx_printk(KERN_ERR, "Failed to read lower tohm\n");
 270                goto fail;
 271        }
 272        skx_tohm = reg;
 273
 274        if (pci_read_config_dword(pdev, off[2], &reg)) {
 275                skx_printk(KERN_ERR, "Failed to read upper tohm\n");
 276                goto fail;
 277        }
 278        skx_tohm |= (u64)reg << 32;
 279
 280        pci_dev_put(pdev);
 281        *tolm = skx_tolm;
 282        *tohm = skx_tohm;
 283        edac_dbg(2, "tolm = 0x%llx tohm = 0x%llx\n", skx_tolm, skx_tohm);
 284        return 0;
 285fail:
 286        pci_dev_put(pdev);
 287        return -ENODEV;
 288}
 289
 290static int skx_get_dimm_attr(u32 reg, int lobit, int hibit, int add,
 291                             int minval, int maxval, const char *name)
 292{
 293        u32 val = GET_BITFIELD(reg, lobit, hibit);
 294
 295        if (val < minval || val > maxval) {
 296                edac_dbg(2, "bad %s = %d (raw=0x%x)\n", name, val, reg);
 297                return -EINVAL;
 298        }
 299        return val + add;
 300}
 301
 302#define numrank(reg)    skx_get_dimm_attr(reg, 12, 13, 0, 0, 2, "ranks")
 303#define numrow(reg)     skx_get_dimm_attr(reg, 2, 4, 12, 1, 6, "rows")
 304#define numcol(reg)     skx_get_dimm_attr(reg, 0, 1, 10, 0, 2, "cols")
 305
 306int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,
 307                      struct skx_imc *imc, int chan, int dimmno,
 308                      struct res_config *cfg)
 309{
 310        int  banks, ranks, rows, cols, npages;
 311        enum mem_type mtype;
 312        u64 size;
 313
 314        ranks = numrank(mtr);
 315        rows = numrow(mtr);
 316        cols = numcol(mtr);
 317
 318        if (cfg->support_ddr5 && (amap & 0x8)) {
 319                banks = 32;
 320                mtype = MEM_DDR5;
 321        } else {
 322                banks = 16;
 323                mtype = MEM_DDR4;
 324        }
 325
 326        /*
 327         * Compute size in 8-byte (2^3) words, then shift to MiB (2^20)
 328         */
 329        size = ((1ull << (rows + cols + ranks)) * banks) >> (20 - 3);
 330        npages = MiB_TO_PAGES(size);
 331
 332        edac_dbg(0, "mc#%d: channel %d, dimm %d, %lld MiB (%d pages) bank: %d, rank: %d, row: 0x%x, col: 0x%x\n",
 333                 imc->mc, chan, dimmno, size, npages,
 334                 banks, 1 << ranks, rows, cols);
 335
 336        imc->chan[chan].dimms[dimmno].close_pg = GET_BITFIELD(mcmtr, 0, 0);
 337        imc->chan[chan].dimms[dimmno].bank_xor_enable = GET_BITFIELD(mcmtr, 9, 9);
 338        imc->chan[chan].dimms[dimmno].fine_grain_bank = GET_BITFIELD(amap, 0, 0);
 339        imc->chan[chan].dimms[dimmno].rowbits = rows;
 340        imc->chan[chan].dimms[dimmno].colbits = cols;
 341
 342        dimm->nr_pages = npages;
 343        dimm->grain = 32;
 344        dimm->dtype = get_width(mtr);
 345        dimm->mtype = mtype;
 346        dimm->edac_mode = EDAC_SECDED; /* likely better than this */
 347        snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u",
 348                 imc->src_id, imc->lmc, chan, dimmno);
 349
 350        return 1;
 351}
 352
 353int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc,
 354                        int chan, int dimmno, const char *mod_str)
 355{
 356        int smbios_handle;
 357        u32 dev_handle;
 358        u16 flags;
 359        u64 size = 0;
 360
 361        dev_handle = ACPI_NFIT_BUILD_DEVICE_HANDLE(dimmno, chan, imc->lmc,
 362                                                   imc->src_id, 0);
 363
 364        smbios_handle = nfit_get_smbios_id(dev_handle, &flags);
 365        if (smbios_handle == -EOPNOTSUPP) {
 366                pr_warn_once("%s: Can't find size of NVDIMM. Try enabling CONFIG_ACPI_NFIT\n", mod_str);
 367                goto unknown_size;
 368        }
 369
 370        if (smbios_handle < 0) {
 371                skx_printk(KERN_ERR, "Can't find handle for NVDIMM ADR=0x%x\n", dev_handle);
 372                goto unknown_size;
 373        }
 374
 375        if (flags & ACPI_NFIT_MEM_MAP_FAILED) {
 376                skx_printk(KERN_ERR, "NVDIMM ADR=0x%x is not mapped\n", dev_handle);
 377                goto unknown_size;
 378        }
 379
 380        size = dmi_memdev_size(smbios_handle);
 381        if (size == ~0ull)
 382                skx_printk(KERN_ERR, "Can't find size for NVDIMM ADR=0x%x/SMBIOS=0x%x\n",
 383                           dev_handle, smbios_handle);
 384
 385unknown_size:
 386        dimm->nr_pages = size >> PAGE_SHIFT;
 387        dimm->grain = 32;
 388        dimm->dtype = DEV_UNKNOWN;
 389        dimm->mtype = MEM_NVDIMM;
 390        dimm->edac_mode = EDAC_SECDED; /* likely better than this */
 391
 392        edac_dbg(0, "mc#%d: channel %d, dimm %d, %llu MiB (%u pages)\n",
 393                 imc->mc, chan, dimmno, size >> 20, dimm->nr_pages);
 394
 395        snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u",
 396                 imc->src_id, imc->lmc, chan, dimmno);
 397
 398        return (size == 0 || size == ~0ull) ? 0 : 1;
 399}
 400
 401int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev,
 402                     const char *ctl_name, const char *mod_str,
 403                     get_dimm_config_f get_dimm_config,
 404                     struct res_config *cfg)
 405{
 406        struct mem_ctl_info *mci;
 407        struct edac_mc_layer layers[2];
 408        struct skx_pvt *pvt;
 409        int rc;
 410
 411        /* Allocate a new MC control structure */
 412        layers[0].type = EDAC_MC_LAYER_CHANNEL;
 413        layers[0].size = NUM_CHANNELS;
 414        layers[0].is_virt_csrow = false;
 415        layers[1].type = EDAC_MC_LAYER_SLOT;
 416        layers[1].size = NUM_DIMMS;
 417        layers[1].is_virt_csrow = true;
 418        mci = edac_mc_alloc(imc->mc, ARRAY_SIZE(layers), layers,
 419                            sizeof(struct skx_pvt));
 420
 421        if (unlikely(!mci))
 422                return -ENOMEM;
 423
 424        edac_dbg(0, "MC#%d: mci = %p\n", imc->mc, mci);
 425
 426        /* Associate skx_dev and mci for future usage */
 427        imc->mci = mci;
 428        pvt = mci->pvt_info;
 429        pvt->imc = imc;
 430
 431        mci->ctl_name = kasprintf(GFP_KERNEL, "%s#%d IMC#%d", ctl_name,
 432                                  imc->node_id, imc->lmc);
 433        if (!mci->ctl_name) {
 434                rc = -ENOMEM;
 435                goto fail0;
 436        }
 437
 438        mci->mtype_cap = MEM_FLAG_DDR4 | MEM_FLAG_NVDIMM;
 439        if (cfg->support_ddr5)
 440                mci->mtype_cap |= MEM_FLAG_DDR5;
 441        mci->edac_ctl_cap = EDAC_FLAG_NONE;
 442        mci->edac_cap = EDAC_FLAG_NONE;
 443        mci->mod_name = mod_str;
 444        mci->dev_name = pci_name(pdev);
 445        mci->ctl_page_to_phys = NULL;
 446
 447        rc = get_dimm_config(mci, cfg);
 448        if (rc < 0)
 449                goto fail;
 450
 451        /* Record ptr to the generic device */
 452        mci->pdev = &pdev->dev;
 453
 454        /* Add this new MC control structure to EDAC's list of MCs */
 455        if (unlikely(edac_mc_add_mc(mci))) {
 456                edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
 457                rc = -EINVAL;
 458                goto fail;
 459        }
 460
 461        return 0;
 462
 463fail:
 464        kfree(mci->ctl_name);
 465fail0:
 466        edac_mc_free(mci);
 467        imc->mci = NULL;
 468        return rc;
 469}
 470
 471static void skx_unregister_mci(struct skx_imc *imc)
 472{
 473        struct mem_ctl_info *mci = imc->mci;
 474
 475        if (!mci)
 476                return;
 477
 478        edac_dbg(0, "MC%d: mci = %p\n", imc->mc, mci);
 479
 480        /* Remove MC sysfs nodes */
 481        edac_mc_del_mc(mci->pdev);
 482
 483        edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
 484        kfree(mci->ctl_name);
 485        edac_mc_free(mci);
 486}
 487
 488static void skx_mce_output_error(struct mem_ctl_info *mci,
 489                                 const struct mce *m,
 490                                 struct decoded_addr *res)
 491{
 492        enum hw_event_mc_err_type tp_event;
 493        char *optype;
 494        bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
 495        bool overflow = GET_BITFIELD(m->status, 62, 62);
 496        bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
 497        bool recoverable;
 498        int len;
 499        u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
 500        u32 mscod = GET_BITFIELD(m->status, 16, 31);
 501        u32 errcode = GET_BITFIELD(m->status, 0, 15);
 502        u32 optypenum = GET_BITFIELD(m->status, 4, 6);
 503
 504        recoverable = GET_BITFIELD(m->status, 56, 56);
 505
 506        if (uncorrected_error) {
 507                core_err_cnt = 1;
 508                if (ripv) {
 509                        tp_event = HW_EVENT_ERR_UNCORRECTED;
 510                } else {
 511                        tp_event = HW_EVENT_ERR_FATAL;
 512                }
 513        } else {
 514                tp_event = HW_EVENT_ERR_CORRECTED;
 515        }
 516
 517        /*
 518         * According to Intel Architecture spec vol 3B,
 519         * Table 15-10 "IA32_MCi_Status [15:0] Compound Error Code Encoding"
 520         * memory errors should fit one of these masks:
 521         *      000f 0000 1mmm cccc (binary)
 522         *      000f 0010 1mmm cccc (binary)    [RAM used as cache]
 523         * where:
 524         *      f = Correction Report Filtering Bit. If 1, subsequent errors
 525         *          won't be shown
 526         *      mmm = error type
 527         *      cccc = channel
 528         * If the mask doesn't match, report an error to the parsing logic
 529         */
 530        if (!((errcode & 0xef80) == 0x80 || (errcode & 0xef80) == 0x280)) {
 531                optype = "Can't parse: it is not a mem";
 532        } else {
 533                switch (optypenum) {
 534                case 0:
 535                        optype = "generic undef request error";
 536                        break;
 537                case 1:
 538                        optype = "memory read error";
 539                        break;
 540                case 2:
 541                        optype = "memory write error";
 542                        break;
 543                case 3:
 544                        optype = "addr/cmd error";
 545                        break;
 546                case 4:
 547                        optype = "memory scrubbing error";
 548                        break;
 549                default:
 550                        optype = "reserved";
 551                        break;
 552                }
 553        }
 554        if (adxl_component_count) {
 555                len = snprintf(skx_msg, MSG_SIZE, "%s%s err_code:0x%04x:0x%04x %s",
 556                         overflow ? " OVERFLOW" : "",
 557                         (uncorrected_error && recoverable) ? " recoverable" : "",
 558                         mscod, errcode, adxl_msg);
 559        } else {
 560                len = snprintf(skx_msg, MSG_SIZE,
 561                         "%s%s err_code:0x%04x:0x%04x socket:%d imc:%d rank:%d bg:%d ba:%d row:0x%x col:0x%x",
 562                         overflow ? " OVERFLOW" : "",
 563                         (uncorrected_error && recoverable) ? " recoverable" : "",
 564                         mscod, errcode,
 565                         res->socket, res->imc, res->rank,
 566                         res->bank_group, res->bank_address, res->row, res->column);
 567        }
 568
 569        if (skx_show_retry_rd_err_log)
 570                skx_show_retry_rd_err_log(res, skx_msg + len, MSG_SIZE - len);
 571
 572        edac_dbg(0, "%s\n", skx_msg);
 573
 574        /* Call the helper to output message */
 575        edac_mc_handle_error(tp_event, mci, core_err_cnt,
 576                             m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
 577                             res->channel, res->dimm, -1,
 578                             optype, skx_msg);
 579}
 580
 581int skx_mce_check_error(struct notifier_block *nb, unsigned long val,
 582                        void *data)
 583{
 584        struct mce *mce = (struct mce *)data;
 585        struct decoded_addr res;
 586        struct mem_ctl_info *mci;
 587        char *type;
 588
 589        if (mce->kflags & MCE_HANDLED_CEC)
 590                return NOTIFY_DONE;
 591
 592        /* ignore unless this is memory related with an address */
 593        if ((mce->status & 0xefff) >> 7 != 1 || !(mce->status & MCI_STATUS_ADDRV))
 594                return NOTIFY_DONE;
 595
 596        memset(&res, 0, sizeof(res));
 597        res.addr = mce->addr;
 598
 599        if (adxl_component_count) {
 600                if (!skx_adxl_decode(&res))
 601                        return NOTIFY_DONE;
 602        } else if (!skx_decode || !skx_decode(&res)) {
 603                return NOTIFY_DONE;
 604        }
 605
 606        mci = res.dev->imc[res.imc].mci;
 607
 608        if (!mci)
 609                return NOTIFY_DONE;
 610
 611        if (mce->mcgstatus & MCG_STATUS_MCIP)
 612                type = "Exception";
 613        else
 614                type = "Event";
 615
 616        skx_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
 617
 618        skx_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: 0x%llx "
 619                           "Bank %d: 0x%llx\n", mce->extcpu, type,
 620                           mce->mcgstatus, mce->bank, mce->status);
 621        skx_mc_printk(mci, KERN_DEBUG, "TSC 0x%llx ", mce->tsc);
 622        skx_mc_printk(mci, KERN_DEBUG, "ADDR 0x%llx ", mce->addr);
 623        skx_mc_printk(mci, KERN_DEBUG, "MISC 0x%llx ", mce->misc);
 624
 625        skx_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:0x%x TIME %llu SOCKET "
 626                           "%u APIC 0x%x\n", mce->cpuvendor, mce->cpuid,
 627                           mce->time, mce->socketid, mce->apicid);
 628
 629        skx_mce_output_error(mci, mce, &res);
 630
 631        mce->kflags |= MCE_HANDLED_EDAC;
 632        return NOTIFY_DONE;
 633}
 634
 635void skx_remove(void)
 636{
 637        int i, j;
 638        struct skx_dev *d, *tmp;
 639
 640        edac_dbg(0, "\n");
 641
 642        list_for_each_entry_safe(d, tmp, &dev_edac_list, list) {
 643                list_del(&d->list);
 644                for (i = 0; i < NUM_IMC; i++) {
 645                        if (d->imc[i].mci)
 646                                skx_unregister_mci(&d->imc[i]);
 647
 648                        if (d->imc[i].mdev)
 649                                pci_dev_put(d->imc[i].mdev);
 650
 651                        if (d->imc[i].mbase)
 652                                iounmap(d->imc[i].mbase);
 653
 654                        for (j = 0; j < NUM_CHANNELS; j++) {
 655                                if (d->imc[i].chan[j].cdev)
 656                                        pci_dev_put(d->imc[i].chan[j].cdev);
 657                        }
 658                }
 659                if (d->util_all)
 660                        pci_dev_put(d->util_all);
 661                if (d->sad_all)
 662                        pci_dev_put(d->sad_all);
 663                if (d->uracu)
 664                        pci_dev_put(d->uracu);
 665
 666                kfree(d);
 667        }
 668}
 669