linux/drivers/crypto/qce/common.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
   4 */
   5
   6#include <linux/err.h>
   7#include <linux/interrupt.h>
   8#include <linux/types.h>
   9#include <crypto/scatterwalk.h>
  10#include <crypto/sha1.h>
  11#include <crypto/sha2.h>
  12
  13#include "cipher.h"
  14#include "common.h"
  15#include "core.h"
  16#include "regs-v5.h"
  17#include "sha.h"
  18
  19static inline u32 qce_read(struct qce_device *qce, u32 offset)
  20{
  21        return readl(qce->base + offset);
  22}
  23
  24static inline void qce_write(struct qce_device *qce, u32 offset, u32 val)
  25{
  26        writel(val, qce->base + offset);
  27}
  28
  29static inline void qce_write_array(struct qce_device *qce, u32 offset,
  30                                   const u32 *val, unsigned int len)
  31{
  32        int i;
  33
  34        for (i = 0; i < len; i++)
  35                qce_write(qce, offset + i * sizeof(u32), val[i]);
  36}
  37
  38static inline void
  39qce_clear_array(struct qce_device *qce, u32 offset, unsigned int len)
  40{
  41        int i;
  42
  43        for (i = 0; i < len; i++)
  44                qce_write(qce, offset + i * sizeof(u32), 0);
  45}
  46
  47static u32 qce_config_reg(struct qce_device *qce, int little)
  48{
  49        u32 beats = (qce->burst_size >> 3) - 1;
  50        u32 pipe_pair = qce->pipe_pair_id;
  51        u32 config;
  52
  53        config = (beats << REQ_SIZE_SHIFT) & REQ_SIZE_MASK;
  54        config |= BIT(MASK_DOUT_INTR_SHIFT) | BIT(MASK_DIN_INTR_SHIFT) |
  55                  BIT(MASK_OP_DONE_INTR_SHIFT) | BIT(MASK_ERR_INTR_SHIFT);
  56        config |= (pipe_pair << PIPE_SET_SELECT_SHIFT) & PIPE_SET_SELECT_MASK;
  57        config &= ~HIGH_SPD_EN_N_SHIFT;
  58
  59        if (little)
  60                config |= BIT(LITTLE_ENDIAN_MODE_SHIFT);
  61
  62        return config;
  63}
  64
  65void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len)
  66{
  67        __be32 *d = dst;
  68        const u8 *s = src;
  69        unsigned int n;
  70
  71        n = len / sizeof(u32);
  72        for (; n > 0; n--) {
  73                *d = cpu_to_be32p((const __u32 *) s);
  74                s += sizeof(__u32);
  75                d++;
  76        }
  77}
  78
  79static void qce_setup_config(struct qce_device *qce)
  80{
  81        u32 config;
  82
  83        /* get big endianness */
  84        config = qce_config_reg(qce, 0);
  85
  86        /* clear status */
  87        qce_write(qce, REG_STATUS, 0);
  88        qce_write(qce, REG_CONFIG, config);
  89}
  90
  91static inline void qce_crypto_go(struct qce_device *qce)
  92{
  93        qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT));
  94}
  95
  96#ifdef CONFIG_CRYPTO_DEV_QCE_SHA
  97static u32 qce_auth_cfg(unsigned long flags, u32 key_size)
  98{
  99        u32 cfg = 0;
 100
 101        if (IS_AES(flags) && (IS_CCM(flags) || IS_CMAC(flags)))
 102                cfg |= AUTH_ALG_AES << AUTH_ALG_SHIFT;
 103        else
 104                cfg |= AUTH_ALG_SHA << AUTH_ALG_SHIFT;
 105
 106        if (IS_CCM(flags) || IS_CMAC(flags)) {
 107                if (key_size == AES_KEYSIZE_128)
 108                        cfg |= AUTH_KEY_SZ_AES128 << AUTH_KEY_SIZE_SHIFT;
 109                else if (key_size == AES_KEYSIZE_256)
 110                        cfg |= AUTH_KEY_SZ_AES256 << AUTH_KEY_SIZE_SHIFT;
 111        }
 112
 113        if (IS_SHA1(flags) || IS_SHA1_HMAC(flags))
 114                cfg |= AUTH_SIZE_SHA1 << AUTH_SIZE_SHIFT;
 115        else if (IS_SHA256(flags) || IS_SHA256_HMAC(flags))
 116                cfg |= AUTH_SIZE_SHA256 << AUTH_SIZE_SHIFT;
 117        else if (IS_CMAC(flags))
 118                cfg |= AUTH_SIZE_ENUM_16_BYTES << AUTH_SIZE_SHIFT;
 119
 120        if (IS_SHA1(flags) || IS_SHA256(flags))
 121                cfg |= AUTH_MODE_HASH << AUTH_MODE_SHIFT;
 122        else if (IS_SHA1_HMAC(flags) || IS_SHA256_HMAC(flags) ||
 123                 IS_CBC(flags) || IS_CTR(flags))
 124                cfg |= AUTH_MODE_HMAC << AUTH_MODE_SHIFT;
 125        else if (IS_AES(flags) && IS_CCM(flags))
 126                cfg |= AUTH_MODE_CCM << AUTH_MODE_SHIFT;
 127        else if (IS_AES(flags) && IS_CMAC(flags))
 128                cfg |= AUTH_MODE_CMAC << AUTH_MODE_SHIFT;
 129
 130        if (IS_SHA(flags) || IS_SHA_HMAC(flags))
 131                cfg |= AUTH_POS_BEFORE << AUTH_POS_SHIFT;
 132
 133        if (IS_CCM(flags))
 134                cfg |= QCE_MAX_NONCE_WORDS << AUTH_NONCE_NUM_WORDS_SHIFT;
 135
 136        if (IS_CBC(flags) || IS_CTR(flags) || IS_CCM(flags) ||
 137            IS_CMAC(flags))
 138                cfg |= BIT(AUTH_LAST_SHIFT) | BIT(AUTH_FIRST_SHIFT);
 139
 140        return cfg;
 141}
 142
 143static int qce_setup_regs_ahash(struct crypto_async_request *async_req)
 144{
 145        struct ahash_request *req = ahash_request_cast(async_req);
 146        struct crypto_ahash *ahash = __crypto_ahash_cast(async_req->tfm);
 147        struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
 148        struct qce_alg_template *tmpl = to_ahash_tmpl(async_req->tfm);
 149        struct qce_device *qce = tmpl->qce;
 150        unsigned int digestsize = crypto_ahash_digestsize(ahash);
 151        unsigned int blocksize = crypto_tfm_alg_blocksize(async_req->tfm);
 152        __be32 auth[SHA256_DIGEST_SIZE / sizeof(__be32)] = {0};
 153        __be32 mackey[QCE_SHA_HMAC_KEY_SIZE / sizeof(__be32)] = {0};
 154        u32 auth_cfg = 0, config;
 155        unsigned int iv_words;
 156
 157        /* if not the last, the size has to be on the block boundary */
 158        if (!rctx->last_blk && req->nbytes % blocksize)
 159                return -EINVAL;
 160
 161        qce_setup_config(qce);
 162
 163        if (IS_CMAC(rctx->flags)) {
 164                qce_write(qce, REG_AUTH_SEG_CFG, 0);
 165                qce_write(qce, REG_ENCR_SEG_CFG, 0);
 166                qce_write(qce, REG_ENCR_SEG_SIZE, 0);
 167                qce_clear_array(qce, REG_AUTH_IV0, 16);
 168                qce_clear_array(qce, REG_AUTH_KEY0, 16);
 169                qce_clear_array(qce, REG_AUTH_BYTECNT0, 4);
 170
 171                auth_cfg = qce_auth_cfg(rctx->flags, rctx->authklen);
 172        }
 173
 174        if (IS_SHA_HMAC(rctx->flags) || IS_CMAC(rctx->flags)) {
 175                u32 authkey_words = rctx->authklen / sizeof(u32);
 176
 177                qce_cpu_to_be32p_array(mackey, rctx->authkey, rctx->authklen);
 178                qce_write_array(qce, REG_AUTH_KEY0, (u32 *)mackey,
 179                                authkey_words);
 180        }
 181
 182        if (IS_CMAC(rctx->flags))
 183                goto go_proc;
 184
 185        if (rctx->first_blk)
 186                memcpy(auth, rctx->digest, digestsize);
 187        else
 188                qce_cpu_to_be32p_array(auth, rctx->digest, digestsize);
 189
 190        iv_words = (IS_SHA1(rctx->flags) || IS_SHA1_HMAC(rctx->flags)) ? 5 : 8;
 191        qce_write_array(qce, REG_AUTH_IV0, (u32 *)auth, iv_words);
 192
 193        if (rctx->first_blk)
 194                qce_clear_array(qce, REG_AUTH_BYTECNT0, 4);
 195        else
 196                qce_write_array(qce, REG_AUTH_BYTECNT0,
 197                                (u32 *)rctx->byte_count, 2);
 198
 199        auth_cfg = qce_auth_cfg(rctx->flags, 0);
 200
 201        if (rctx->last_blk)
 202                auth_cfg |= BIT(AUTH_LAST_SHIFT);
 203        else
 204                auth_cfg &= ~BIT(AUTH_LAST_SHIFT);
 205
 206        if (rctx->first_blk)
 207                auth_cfg |= BIT(AUTH_FIRST_SHIFT);
 208        else
 209                auth_cfg &= ~BIT(AUTH_FIRST_SHIFT);
 210
 211go_proc:
 212        qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg);
 213        qce_write(qce, REG_AUTH_SEG_SIZE, req->nbytes);
 214        qce_write(qce, REG_AUTH_SEG_START, 0);
 215        qce_write(qce, REG_ENCR_SEG_CFG, 0);
 216        qce_write(qce, REG_SEG_SIZE, req->nbytes);
 217
 218        /* get little endianness */
 219        config = qce_config_reg(qce, 1);
 220        qce_write(qce, REG_CONFIG, config);
 221
 222        qce_crypto_go(qce);
 223
 224        return 0;
 225}
 226#endif
 227
 228#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
 229static u32 qce_encr_cfg(unsigned long flags, u32 aes_key_size)
 230{
 231        u32 cfg = 0;
 232
 233        if (IS_AES(flags)) {
 234                if (aes_key_size == AES_KEYSIZE_128)
 235                        cfg |= ENCR_KEY_SZ_AES128 << ENCR_KEY_SZ_SHIFT;
 236                else if (aes_key_size == AES_KEYSIZE_256)
 237                        cfg |= ENCR_KEY_SZ_AES256 << ENCR_KEY_SZ_SHIFT;
 238        }
 239
 240        if (IS_AES(flags))
 241                cfg |= ENCR_ALG_AES << ENCR_ALG_SHIFT;
 242        else if (IS_DES(flags) || IS_3DES(flags))
 243                cfg |= ENCR_ALG_DES << ENCR_ALG_SHIFT;
 244
 245        if (IS_DES(flags))
 246                cfg |= ENCR_KEY_SZ_DES << ENCR_KEY_SZ_SHIFT;
 247
 248        if (IS_3DES(flags))
 249                cfg |= ENCR_KEY_SZ_3DES << ENCR_KEY_SZ_SHIFT;
 250
 251        switch (flags & QCE_MODE_MASK) {
 252        case QCE_MODE_ECB:
 253                cfg |= ENCR_MODE_ECB << ENCR_MODE_SHIFT;
 254                break;
 255        case QCE_MODE_CBC:
 256                cfg |= ENCR_MODE_CBC << ENCR_MODE_SHIFT;
 257                break;
 258        case QCE_MODE_CTR:
 259                cfg |= ENCR_MODE_CTR << ENCR_MODE_SHIFT;
 260                break;
 261        case QCE_MODE_XTS:
 262                cfg |= ENCR_MODE_XTS << ENCR_MODE_SHIFT;
 263                break;
 264        case QCE_MODE_CCM:
 265                cfg |= ENCR_MODE_CCM << ENCR_MODE_SHIFT;
 266                cfg |= LAST_CCM_XFR << LAST_CCM_SHIFT;
 267                break;
 268        default:
 269                return ~0;
 270        }
 271
 272        return cfg;
 273}
 274
 275static void qce_xts_swapiv(__be32 *dst, const u8 *src, unsigned int ivsize)
 276{
 277        u8 swap[QCE_AES_IV_LENGTH];
 278        u32 i, j;
 279
 280        if (ivsize > QCE_AES_IV_LENGTH)
 281                return;
 282
 283        memset(swap, 0, QCE_AES_IV_LENGTH);
 284
 285        for (i = (QCE_AES_IV_LENGTH - ivsize), j = ivsize - 1;
 286             i < QCE_AES_IV_LENGTH; i++, j--)
 287                swap[i] = src[j];
 288
 289        qce_cpu_to_be32p_array(dst, swap, QCE_AES_IV_LENGTH);
 290}
 291
 292static void qce_xtskey(struct qce_device *qce, const u8 *enckey,
 293                       unsigned int enckeylen, unsigned int cryptlen)
 294{
 295        u32 xtskey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(u32)] = {0};
 296        unsigned int xtsklen = enckeylen / (2 * sizeof(u32));
 297
 298        qce_cpu_to_be32p_array((__be32 *)xtskey, enckey + enckeylen / 2,
 299                               enckeylen / 2);
 300        qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen);
 301
 302        /* Set data unit size to cryptlen. Anything else causes
 303         * crypto engine to return back incorrect results.
 304         */
 305        qce_write(qce, REG_ENCR_XTS_DU_SIZE, cryptlen);
 306}
 307
 308static int qce_setup_regs_skcipher(struct crypto_async_request *async_req)
 309{
 310        struct skcipher_request *req = skcipher_request_cast(async_req);
 311        struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req);
 312        struct qce_cipher_ctx *ctx = crypto_tfm_ctx(async_req->tfm);
 313        struct qce_alg_template *tmpl = to_cipher_tmpl(crypto_skcipher_reqtfm(req));
 314        struct qce_device *qce = tmpl->qce;
 315        __be32 enckey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(__be32)] = {0};
 316        __be32 enciv[QCE_MAX_IV_SIZE / sizeof(__be32)] = {0};
 317        unsigned int enckey_words, enciv_words;
 318        unsigned int keylen;
 319        u32 encr_cfg = 0, auth_cfg = 0, config;
 320        unsigned int ivsize = rctx->ivsize;
 321        unsigned long flags = rctx->flags;
 322
 323        qce_setup_config(qce);
 324
 325        if (IS_XTS(flags))
 326                keylen = ctx->enc_keylen / 2;
 327        else
 328                keylen = ctx->enc_keylen;
 329
 330        qce_cpu_to_be32p_array(enckey, ctx->enc_key, keylen);
 331        enckey_words = keylen / sizeof(u32);
 332
 333        qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg);
 334
 335        encr_cfg = qce_encr_cfg(flags, keylen);
 336
 337        if (IS_DES(flags)) {
 338                enciv_words = 2;
 339                enckey_words = 2;
 340        } else if (IS_3DES(flags)) {
 341                enciv_words = 2;
 342                enckey_words = 6;
 343        } else if (IS_AES(flags)) {
 344                if (IS_XTS(flags))
 345                        qce_xtskey(qce, ctx->enc_key, ctx->enc_keylen,
 346                                   rctx->cryptlen);
 347                enciv_words = 4;
 348        } else {
 349                return -EINVAL;
 350        }
 351
 352        qce_write_array(qce, REG_ENCR_KEY0, (u32 *)enckey, enckey_words);
 353
 354        if (!IS_ECB(flags)) {
 355                if (IS_XTS(flags))
 356                        qce_xts_swapiv(enciv, rctx->iv, ivsize);
 357                else
 358                        qce_cpu_to_be32p_array(enciv, rctx->iv, ivsize);
 359
 360                qce_write_array(qce, REG_CNTR0_IV0, (u32 *)enciv, enciv_words);
 361        }
 362
 363        if (IS_ENCRYPT(flags))
 364                encr_cfg |= BIT(ENCODE_SHIFT);
 365
 366        qce_write(qce, REG_ENCR_SEG_CFG, encr_cfg);
 367        qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen);
 368        qce_write(qce, REG_ENCR_SEG_START, 0);
 369
 370        if (IS_CTR(flags)) {
 371                qce_write(qce, REG_CNTR_MASK, ~0);
 372                qce_write(qce, REG_CNTR_MASK0, ~0);
 373                qce_write(qce, REG_CNTR_MASK1, ~0);
 374                qce_write(qce, REG_CNTR_MASK2, ~0);
 375        }
 376
 377        qce_write(qce, REG_SEG_SIZE, rctx->cryptlen);
 378
 379        /* get little endianness */
 380        config = qce_config_reg(qce, 1);
 381        qce_write(qce, REG_CONFIG, config);
 382
 383        qce_crypto_go(qce);
 384
 385        return 0;
 386}
 387#endif
 388
 389int qce_start(struct crypto_async_request *async_req, u32 type)
 390{
 391        switch (type) {
 392#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
 393        case CRYPTO_ALG_TYPE_SKCIPHER:
 394                return qce_setup_regs_skcipher(async_req);
 395#endif
 396#ifdef CONFIG_CRYPTO_DEV_QCE_SHA
 397        case CRYPTO_ALG_TYPE_AHASH:
 398                return qce_setup_regs_ahash(async_req);
 399#endif
 400        default:
 401                return -EINVAL;
 402        }
 403}
 404
 405#define STATUS_ERRORS   \
 406                (BIT(SW_ERR_SHIFT) | BIT(AXI_ERR_SHIFT) | BIT(HSD_ERR_SHIFT))
 407
 408int qce_check_status(struct qce_device *qce, u32 *status)
 409{
 410        int ret = 0;
 411
 412        *status = qce_read(qce, REG_STATUS);
 413
 414        /*
 415         * Don't use result dump status. The operation may not be complete.
 416         * Instead, use the status we just read from device. In case, we need to
 417         * use result_status from result dump the result_status needs to be byte
 418         * swapped, since we set the device to little endian.
 419         */
 420        if (*status & STATUS_ERRORS || !(*status & BIT(OPERATION_DONE_SHIFT)))
 421                ret = -ENXIO;
 422
 423        return ret;
 424}
 425
 426void qce_get_version(struct qce_device *qce, u32 *major, u32 *minor, u32 *step)
 427{
 428        u32 val;
 429
 430        val = qce_read(qce, REG_VERSION);
 431        *major = (val & CORE_MAJOR_REV_MASK) >> CORE_MAJOR_REV_SHIFT;
 432        *minor = (val & CORE_MINOR_REV_MASK) >> CORE_MINOR_REV_SHIFT;
 433        *step = (val & CORE_STEP_REV_MASK) >> CORE_STEP_REV_SHIFT;
 434}
 435