linux/drivers/crypto/hisilicon/qm.h
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   1/* SPDX-License-Identifier: GPL-2.0 */
   2/* Copyright (c) 2019 HiSilicon Limited. */
   3#ifndef HISI_ACC_QM_H
   4#define HISI_ACC_QM_H
   5
   6#include <linux/bitfield.h>
   7#include <linux/iopoll.h>
   8#include <linux/module.h>
   9#include <linux/pci.h>
  10
  11#define QM_QNUM_V1                      4096
  12#define QM_QNUM_V2                      1024
  13#define QM_MAX_VFS_NUM_V2               63
  14
  15/* qm user domain */
  16#define QM_ARUSER_M_CFG_1               0x100088
  17#define AXUSER_SNOOP_ENABLE             BIT(30)
  18#define AXUSER_CMD_TYPE                 GENMASK(14, 12)
  19#define AXUSER_CMD_SMMU_NORMAL          1
  20#define AXUSER_NS                       BIT(6)
  21#define AXUSER_NO                       BIT(5)
  22#define AXUSER_FP                       BIT(4)
  23#define AXUSER_SSV                      BIT(0)
  24#define AXUSER_BASE                     (AXUSER_SNOOP_ENABLE |          \
  25                                        FIELD_PREP(AXUSER_CMD_TYPE,     \
  26                                        AXUSER_CMD_SMMU_NORMAL) |       \
  27                                        AXUSER_NS | AXUSER_NO | AXUSER_FP)
  28#define QM_ARUSER_M_CFG_ENABLE          0x100090
  29#define ARUSER_M_CFG_ENABLE             0xfffffffe
  30#define QM_AWUSER_M_CFG_1               0x100098
  31#define QM_AWUSER_M_CFG_ENABLE          0x1000a0
  32#define AWUSER_M_CFG_ENABLE             0xfffffffe
  33#define QM_WUSER_M_CFG_ENABLE           0x1000a8
  34#define WUSER_M_CFG_ENABLE              0xffffffff
  35
  36/* qm cache */
  37#define QM_CACHE_CTL                    0x100050
  38#define SQC_CACHE_ENABLE                BIT(0)
  39#define CQC_CACHE_ENABLE                BIT(1)
  40#define SQC_CACHE_WB_ENABLE             BIT(4)
  41#define SQC_CACHE_WB_THRD               GENMASK(10, 5)
  42#define CQC_CACHE_WB_ENABLE             BIT(11)
  43#define CQC_CACHE_WB_THRD               GENMASK(17, 12)
  44#define QM_AXI_M_CFG                    0x1000ac
  45#define AXI_M_CFG                       0xffff
  46#define QM_AXI_M_CFG_ENABLE             0x1000b0
  47#define AM_CFG_SINGLE_PORT_MAX_TRANS    0x300014
  48#define AXI_M_CFG_ENABLE                0xffffffff
  49#define QM_PEH_AXUSER_CFG               0x1000cc
  50#define QM_PEH_AXUSER_CFG_ENABLE        0x1000d0
  51#define PEH_AXUSER_CFG                  0x401001
  52#define PEH_AXUSER_CFG_ENABLE           0xffffffff
  53
  54#define QM_AXI_RRESP                    BIT(0)
  55#define QM_AXI_BRESP                    BIT(1)
  56#define QM_ECC_MBIT                     BIT(2)
  57#define QM_ECC_1BIT                     BIT(3)
  58#define QM_ACC_GET_TASK_TIMEOUT         BIT(4)
  59#define QM_ACC_DO_TASK_TIMEOUT          BIT(5)
  60#define QM_ACC_WB_NOT_READY_TIMEOUT     BIT(6)
  61#define QM_SQ_CQ_VF_INVALID             BIT(7)
  62#define QM_CQ_VF_INVALID                BIT(8)
  63#define QM_SQ_VF_INVALID                BIT(9)
  64#define QM_DB_TIMEOUT                   BIT(10)
  65#define QM_OF_FIFO_OF                   BIT(11)
  66#define QM_DB_RANDOM_INVALID            BIT(12)
  67#define QM_MAILBOX_TIMEOUT              BIT(13)
  68#define QM_FLR_TIMEOUT                  BIT(14)
  69
  70#define QM_BASE_NFE     (QM_AXI_RRESP | QM_AXI_BRESP | QM_ECC_MBIT | \
  71                         QM_ACC_GET_TASK_TIMEOUT | QM_DB_TIMEOUT | \
  72                         QM_OF_FIFO_OF | QM_DB_RANDOM_INVALID | \
  73                         QM_MAILBOX_TIMEOUT | QM_FLR_TIMEOUT)
  74#define QM_BASE_CE                      QM_ECC_1BIT
  75
  76#define QM_Q_DEPTH                      1024
  77#define QM_MIN_QNUM                     2
  78#define HISI_ACC_SGL_SGE_NR_MAX         255
  79
  80/* page number for queue file region */
  81#define QM_DOORBELL_PAGE_NR             1
  82
  83/* uacce mode of the driver */
  84#define UACCE_MODE_NOUACCE              0 /* don't use uacce */
  85#define UACCE_MODE_SVA                  1 /* use uacce sva mode */
  86#define UACCE_MODE_DESC "0(default) means only register to crypto, 1 means both register to crypto and uacce"
  87
  88enum qm_stop_reason {
  89        QM_NORMAL,
  90        QM_SOFT_RESET,
  91        QM_FLR,
  92};
  93
  94enum qm_state {
  95        QM_INIT = 0,
  96        QM_START,
  97        QM_CLOSE,
  98        QM_STOP,
  99};
 100
 101enum qp_state {
 102        QP_INIT = 1,
 103        QP_START,
 104        QP_STOP,
 105        QP_CLOSE,
 106};
 107
 108enum qm_hw_ver {
 109        QM_HW_UNKNOWN = -1,
 110        QM_HW_V1 = 0x20,
 111        QM_HW_V2 = 0x21,
 112        QM_HW_V3 = 0x30,
 113};
 114
 115enum qm_fun_type {
 116        QM_HW_PF,
 117        QM_HW_VF,
 118};
 119
 120enum qm_debug_file {
 121        CURRENT_QM,
 122        CURRENT_Q,
 123        CLEAR_ENABLE,
 124        DEBUG_FILE_NUM,
 125};
 126
 127struct qm_dfx {
 128        atomic64_t err_irq_cnt;
 129        atomic64_t aeq_irq_cnt;
 130        atomic64_t abnormal_irq_cnt;
 131        atomic64_t create_qp_err_cnt;
 132        atomic64_t mb_err_cnt;
 133};
 134
 135struct debugfs_file {
 136        enum qm_debug_file index;
 137        struct mutex lock;
 138        struct qm_debug *debug;
 139};
 140
 141struct qm_debug {
 142        u32 curr_qm_qp_num;
 143        u32 sqe_mask_offset;
 144        u32 sqe_mask_len;
 145        struct qm_dfx dfx;
 146        struct dentry *debug_root;
 147        struct dentry *qm_d;
 148        struct debugfs_file files[DEBUG_FILE_NUM];
 149};
 150
 151struct qm_dma {
 152        void *va;
 153        dma_addr_t dma;
 154        size_t size;
 155};
 156
 157struct hisi_qm_status {
 158        u32 eq_head;
 159        bool eqc_phase;
 160        u32 aeq_head;
 161        bool aeqc_phase;
 162        atomic_t flags;
 163        int stop_reason;
 164};
 165
 166struct hisi_qm;
 167
 168struct hisi_qm_err_info {
 169        char *acpi_rst;
 170        u32 msi_wr_port;
 171        u32 ecc_2bits_mask;
 172        u32 dev_ce_mask;
 173        u32 ce;
 174        u32 nfe;
 175        u32 fe;
 176};
 177
 178struct hisi_qm_err_status {
 179        u32 is_qm_ecc_mbit;
 180        u32 is_dev_ecc_mbit;
 181};
 182
 183struct hisi_qm_err_ini {
 184        int (*hw_init)(struct hisi_qm *qm);
 185        void (*hw_err_enable)(struct hisi_qm *qm);
 186        void (*hw_err_disable)(struct hisi_qm *qm);
 187        u32 (*get_dev_hw_err_status)(struct hisi_qm *qm);
 188        void (*clear_dev_hw_err_status)(struct hisi_qm *qm, u32 err_sts);
 189        void (*open_axi_master_ooo)(struct hisi_qm *qm);
 190        void (*close_axi_master_ooo)(struct hisi_qm *qm);
 191        void (*log_dev_hw_err)(struct hisi_qm *qm, u32 err_sts);
 192        void (*err_info_init)(struct hisi_qm *qm);
 193};
 194
 195struct hisi_qm_list {
 196        struct mutex lock;
 197        struct list_head list;
 198        int (*register_to_crypto)(struct hisi_qm *qm);
 199        void (*unregister_from_crypto)(struct hisi_qm *qm);
 200};
 201
 202struct hisi_qm {
 203        enum qm_hw_ver ver;
 204        enum qm_fun_type fun_type;
 205        const char *dev_name;
 206        struct pci_dev *pdev;
 207        void __iomem *io_base;
 208        void __iomem *db_io_base;
 209        u32 sqe_size;
 210        u32 qp_base;
 211        u32 qp_num;
 212        u32 qp_in_used;
 213        u32 ctrl_qp_num;
 214        u32 max_qp_num;
 215        u32 vfs_num;
 216        u32 db_interval;
 217        struct list_head list;
 218        struct hisi_qm_list *qm_list;
 219
 220        struct qm_dma qdma;
 221        struct qm_sqc *sqc;
 222        struct qm_cqc *cqc;
 223        struct qm_eqe *eqe;
 224        struct qm_aeqe *aeqe;
 225        dma_addr_t sqc_dma;
 226        dma_addr_t cqc_dma;
 227        dma_addr_t eqe_dma;
 228        dma_addr_t aeqe_dma;
 229
 230        struct hisi_qm_status status;
 231        const struct hisi_qm_err_ini *err_ini;
 232        struct hisi_qm_err_info err_info;
 233        struct hisi_qm_err_status err_status;
 234        unsigned long misc_ctl; /* driver removing and reset sched */
 235
 236        struct rw_semaphore qps_lock;
 237        struct idr qp_idr;
 238        struct hisi_qp *qp_array;
 239
 240        struct mutex mailbox_lock;
 241
 242        const struct hisi_qm_hw_ops *ops;
 243
 244        struct qm_debug debug;
 245
 246        u32 error_mask;
 247
 248        struct workqueue_struct *wq;
 249        struct work_struct work;
 250        struct work_struct rst_work;
 251
 252        const char *algs;
 253        bool use_sva;
 254        bool is_frozen;
 255
 256        /* doorbell isolation enable */
 257        bool use_db_isolation;
 258        resource_size_t phys_base;
 259        resource_size_t db_phys_base;
 260        struct uacce_device *uacce;
 261        int mode;
 262};
 263
 264struct hisi_qp_status {
 265        atomic_t used;
 266        u16 sq_tail;
 267        u16 cq_head;
 268        bool cqc_phase;
 269        atomic_t flags;
 270};
 271
 272struct hisi_qp_ops {
 273        int (*fill_sqe)(void *sqe, void *q_parm, void *d_parm);
 274};
 275
 276struct hisi_qp {
 277        u32 qp_id;
 278        u8 alg_type;
 279        u8 req_type;
 280
 281        struct qm_dma qdma;
 282        void *sqe;
 283        struct qm_cqe *cqe;
 284        dma_addr_t sqe_dma;
 285        dma_addr_t cqe_dma;
 286
 287        struct hisi_qp_status qp_status;
 288        struct hisi_qp_ops *hw_ops;
 289        void *qp_ctx;
 290        void (*req_cb)(struct hisi_qp *qp, void *data);
 291        void (*event_cb)(struct hisi_qp *qp);
 292
 293        struct hisi_qm *qm;
 294        bool is_resetting;
 295        bool is_in_kernel;
 296        u16 pasid;
 297        struct uacce_queue *uacce_q;
 298};
 299
 300static inline int q_num_set(const char *val, const struct kernel_param *kp,
 301                            unsigned int device)
 302{
 303        struct pci_dev *pdev = pci_get_device(PCI_VENDOR_ID_HUAWEI,
 304                                              device, NULL);
 305        u32 n, q_num;
 306        int ret;
 307
 308        if (!val)
 309                return -EINVAL;
 310
 311        if (!pdev) {
 312                q_num = min_t(u32, QM_QNUM_V1, QM_QNUM_V2);
 313                pr_info("No device found currently, suppose queue number is %u\n",
 314                        q_num);
 315        } else {
 316                if (pdev->revision == QM_HW_V1)
 317                        q_num = QM_QNUM_V1;
 318                else
 319                        q_num = QM_QNUM_V2;
 320        }
 321
 322        ret = kstrtou32(val, 10, &n);
 323        if (ret || n < QM_MIN_QNUM || n > q_num)
 324                return -EINVAL;
 325
 326        return param_set_int(val, kp);
 327}
 328
 329static inline int vfs_num_set(const char *val, const struct kernel_param *kp)
 330{
 331        u32 n;
 332        int ret;
 333
 334        if (!val)
 335                return -EINVAL;
 336
 337        ret = kstrtou32(val, 10, &n);
 338        if (ret < 0)
 339                return ret;
 340
 341        if (n > QM_MAX_VFS_NUM_V2)
 342                return -EINVAL;
 343
 344        return param_set_int(val, kp);
 345}
 346
 347static inline int mode_set(const char *val, const struct kernel_param *kp)
 348{
 349        u32 n;
 350        int ret;
 351
 352        if (!val)
 353                return -EINVAL;
 354
 355        ret = kstrtou32(val, 10, &n);
 356        if (ret != 0 || (n != UACCE_MODE_SVA &&
 357                         n != UACCE_MODE_NOUACCE))
 358                return -EINVAL;
 359
 360        return param_set_int(val, kp);
 361}
 362
 363static inline int uacce_mode_set(const char *val, const struct kernel_param *kp)
 364{
 365        return mode_set(val, kp);
 366}
 367
 368static inline void hisi_qm_init_list(struct hisi_qm_list *qm_list)
 369{
 370        INIT_LIST_HEAD(&qm_list->list);
 371        mutex_init(&qm_list->lock);
 372}
 373
 374int hisi_qm_init(struct hisi_qm *qm);
 375void hisi_qm_uninit(struct hisi_qm *qm);
 376int hisi_qm_start(struct hisi_qm *qm);
 377int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r);
 378struct hisi_qp *hisi_qm_create_qp(struct hisi_qm *qm, u8 alg_type);
 379int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg);
 380int hisi_qm_stop_qp(struct hisi_qp *qp);
 381void hisi_qm_release_qp(struct hisi_qp *qp);
 382int hisi_qp_send(struct hisi_qp *qp, const void *msg);
 383int hisi_qm_get_free_qp_num(struct hisi_qm *qm);
 384int hisi_qm_get_vft(struct hisi_qm *qm, u32 *base, u32 *number);
 385void hisi_qm_debug_init(struct hisi_qm *qm);
 386enum qm_hw_ver hisi_qm_get_hw_version(struct pci_dev *pdev);
 387void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
 388int hisi_qm_sriov_enable(struct pci_dev *pdev, int max_vfs);
 389int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen);
 390int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs);
 391void hisi_qm_dev_err_init(struct hisi_qm *qm);
 392void hisi_qm_dev_err_uninit(struct hisi_qm *qm);
 393pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
 394                                          pci_channel_state_t state);
 395pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev);
 396void hisi_qm_reset_prepare(struct pci_dev *pdev);
 397void hisi_qm_reset_done(struct pci_dev *pdev);
 398
 399struct hisi_acc_sgl_pool;
 400struct hisi_acc_hw_sgl *hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
 401        struct scatterlist *sgl, struct hisi_acc_sgl_pool *pool,
 402        u32 index, dma_addr_t *hw_sgl_dma);
 403void hisi_acc_sg_buf_unmap(struct device *dev, struct scatterlist *sgl,
 404                           struct hisi_acc_hw_sgl *hw_sgl);
 405struct hisi_acc_sgl_pool *hisi_acc_create_sgl_pool(struct device *dev,
 406                                                   u32 count, u32 sge_nr);
 407void hisi_acc_free_sgl_pool(struct device *dev,
 408                            struct hisi_acc_sgl_pool *pool);
 409int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num,
 410                           u8 alg_type, int node, struct hisi_qp **qps);
 411void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num);
 412void hisi_qm_dev_shutdown(struct pci_dev *pdev);
 413void hisi_qm_wait_task_finish(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
 414int hisi_qm_alg_register(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
 415void hisi_qm_alg_unregister(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
 416#endif
 417